SiC461, SiC462, SiC463, SiC464

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4.5 V to 60 V Input, 2 A, 4 A, 6 A, 10 A
microBUCK® DC/DC Converter
FEATURES
• Versatile
- Single supply operation from 4.5 V to 60 V
input voltage
- Adjustable output voltage down to 0.8 V
- Scalable solution 2 A (SiC464), 4 A (SiC463),
6 A (SiC462), 10 A (SiC461)
- Output voltage tracking and sequencing with
pre-bias start up
- ± 1 % output voltage accuracy at -40 °C to +125 °C
• Highly efficient
LINKS TO ADDITIONAL RESOURCES - 98 % peak efficiency
- 4 μA supply current at shutdown
Design Tool Evaluation Design Tools
- 235 μA operating current, not switching
Boards • Highly configurable
- Adjustable switching frequency from 100 kHz to 2 MHz
DESCRIPTION - Adjustable soft start and adjustable current limit
The SiC46x is a family of wide input voltage, high efficiency - 3 modes of operation, forced continuous conduction,
synchronous buck regulators with integrated high side and power save or ultrasonic
low side power MOSFETs. Its power stage is capable of • Robust and reliable
supplying high continuous current at up to 2 MHz switching - Output over voltage protection
frequency. This regulator produces an adjustable output - Output under voltage / short circuit protection with auto
voltage down to 0.8 V from 4.5 V to 60 V input rail to retry
accommodate a variety of applications, including - Power good flag and over temperature protection
computing, consumer electronics, telecom, and industrial. - Supported by Vishay PowerCAD online design
SiC46x’s architecture allows for ultrafast transient response simulation
with minimum output capacitance and tight ripple regulation • Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
at very light load. The device enables loop stability
regardless of the type of output capacitor used, including APPLICATIONS
low ESR ceramic capacitors. The device also incorporates a • Industrial and automation
power saving scheme that significantly increases light load • Home automation
efficiency. The regulator integrates a full protection feature • Industrial and server computing
set, including over current protection (OCP), output
• Networking, telecom, and base station power supplies
overvoltage protection (OVP), short circuit protection (SCP),
output undervoltage protection (UVP) and over temperature • Unregulated wall transformer
protection (OTP). It also has UVLO for input rail and a user • Robotics
programmable soft start. • High end hobby electronics: remote control cars, planes,
and drones
The SiC46x family is available in 2 A, 4 A, 6 A, 10 A pin • Battery management systems
compatible 5 mm by 5 mm lead (Pb)-free power enhanced • Power tools
MLP55-27L package.
• Vending, ATM, and slot machines
TYPICAL APPLICATION CIRCUIT
100 10000
VIN = 48 V, VOUT = 12 V VIN = 24 V, VOUT = 12 V
98
96
94
eff - Efficiency (%)

CBOOT 1000
PGOOD

BOOT
EN

INPUT
VCIN
4.5 VDC to 60 VDC PHASE V OUT 92
2nd line
1st line
2nd line

V IN SW
V DD 90
CIN SiC46x Rx Cx VIN = 24 V, VOUT = 5 V
V DRV V SNS
Cy 88
MODE ULTRASONIC Rup
VIN = 48 V, VOUT = 5 V 100
SS V FB COUT 86
ILIMIT COMP Rdown
Css Rcomp 84
PGND
AGND
fSW

Rlimit
Ccomp 82
Rfsw
80 10
0 1 2 3 4 5 6
IOUT - Output Current (A)
Fig. 1 - Typical Application Circuit for SiC46x Fig. 2 - SiC462 Efficiency vs. Output Current

S21-1142-Rev. P, 29-Nov-2021 1 Document Number: 65124

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PIN CONFIGURATION

27 MODE

21 COMP

27 MODE
21 COMP
23 AGND

23 AGND
20 VSNS
20 VSNS
26 VDD
25 ILIM
24 fSW

26 VDD
22 VFB

25 ILIM
22 VFB

24 fSW
VCIN 1 1 1 VCIN
19 SS SS 19

PGOOD 2 28 AGND 18 ULTRASONIC ULTRASONIC 1 8 28 AGND 2 PGOOD

17 PGND PGND 1 7
EN 3 3 EN
16 VDRV VDRV 1 6
BOOT 4 15 GL GL 1 5 4 BOOT

30 14 SW SW 1 4 29
PHASE 5 VIN 29 PGND 30 PGND VIN 5 PHASE
13 SW SW 1 3
PHASE 6 6 6
6 PHASE
12 SW SW 1 2

PGND 11
PGND 10
PGND 9

VIN 8

VIN 7
VIN 7

VIN 8

PGND 9
PGND 10
PGND 11

Fig. 3 - SiC46x Pin Configuration

PIN DESCRIPTION
PIN NUMBER SYMBOL DESCRIPTION
Supply voltage for internal regulators VDD and VDRV. This pin should be tied to VIN, but can also be
1 VCIN
connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
2 PGOOD
resistor is required
Enable pin. Tie high/low to enable/disable the IC accordingly. This is a high voltage compatible pin,
3 EN
can be tied to 60 V
4 BOOT High side driver bootstrap voltage
5, 6 PHASE Return path of high side gate driver
7, 8, 29 VIN Power stage input voltage. Drain of high side MOSFET
9, 10, 11, 17, 30 PGND Power ground
12, 13, 14 SW Power stage switch node
15 GL Low side MOSFET gate signal
Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, VDRV is
16 VDRV
the LDO output. Connect a 4.7 μF decoupling capacitor to PGND
Float to disable ultrasonic mode, connect to VDD to enable. Depending on the operation mode set by
18 ULTRASONIC the mode pin, power save mode or forced continuous mode will be enabled when the ultrasonic
mode is disabled
Set the soft start ramp by connecting a capacitor to AGND. An internal current source will charge the
19 SS
capacitor
20 VSNS Power inductor signal feedback pin for system stability compensation
Output of the internal error amplifier. The feedback loop compensation network is connected from
21 COMP
this pin to the AGND pin
Feedback input for switching regulator used to program the output voltage - connect to an external
22 VFB
resistor divider from VOUT to AGND
23, 28 AGND Analog ground
24 fSW Set the on-time by connecting a resistor to AGND
25 ILIMIT Set the current limit by connecting a resistor to AGND
26 VDD Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND
27 MODE Set various operation modes by connecting a resistor to AGND. See specification table for details

S21-1142-Rev. P, 29-Nov-2021 2 Document Number: 65124

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ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE
SiC461ED-T1-GE3 PowerPAK® MLP55-27L SiC461
SiC461EVB Reference board
SiC462ED-T1-GE3 PowerPAK® MLP55-27L SiC462
SiC462EVB Reference board
SiC463ED-T1-GE3 PowerPAK® MLP55-27L SiC463
SiC463EVB Reference board
SiC464ED-T1-GE3 PowerPAK® MLP55-27L SiC464
SiC464EVB Reference board

PART MARKING INFORMATION

= pin 1 indicator
P/N = part number code
P/N = Siliconix logo
= ESD symbol
LL F = assembly factory code
Y = year code
FYWW WW = week code
LL = lot code

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

ELECTRICAL PARAMETER CONDITIONS LIMITS UNIT
VCIN, VIN Reference to PGND -0.3 to 66
EN Reference to AGND -0.3 to 60
SW / PHASE Reference to PGND -0.3 to 66
VDRV Reference to PGND -0.3 to 6
VDD Reference to AGND -0.3 to 6 V
SW / PHASE (AC) Reference to PGND; 100 ns -10 to 72
BOOT -0.3 to VPHASE + VDRV
AGND to PGND -0.3 to 0.3
All other pins Reference to AGND -0.3 to VDD + 0.3
Temperature
Junction temperature TJ -40 to +150
°C
Storage temperature TSTG -65 to +150
Power Dissipation
Thermal resistance from junction-to-ambient 12
°C/W
Thermal resistance from junction-to-case 2
ESD Protection
Human body model, JESD22-A114 2000
Electrostatic discharge protection V
Charged device model, JESD22-A101 500

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.

S21-1142-Rev. P, 29-Nov-2021 3 Document Number: 65124

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RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)

PARAMETER MIN. TYP. MAX. UNIT
Input voltage (VIN) 4.5 - 60
Control input voltage (VCIN) (1) 4.5 - 60
Enable (EN) 0 - 60
V
Bias supply (VDD) 4.75 5 5.25
Drive supply voltage (VDRV) 4.75 5.3 5.55
Output voltage (VOUT) 0.8 - 0.92 x VIN
Temperature
Recommended ambient temperature -40 to +105
°C
Operating junction temperature -40 to +125
Note
(1) For input voltages below 5 V, provide a separate supply to V
CIN of at least 5 V to prevent the internal VDD rail UVLO from triggering

ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Power Supplies
VIN = VCIN = 6 V to 60 V 4.75 5 5.25
VDD supply VDD V
VIN = VCIN = 5 V 4.7 5 -
VDD dropout VDD_DROPOUT VIN = VCIN = 5 V, IVDD = 1 mA - 70 - mV
VDD UVLO threshold, rising VDD_UVLO 4 4.25 4.5 V
VDD UVLO hysteresis VDD_UVLO_HYST - 225 - mV
Maximum VDD current IDD VIN = VCIN = 6 V to 60 V 3 - - mA
VIN = VCIN = 6 V to 60 V 4.75 5.3 5.55
VDRV supply VDRV V
VIN = VCIN = 5 V 4.8 5 5.2
VDRV dropout VDRV_DROPOUT VIN = VCIN = 5 V, IVDD = 10 mA - 160 - mV
Maximum VDRV current VDRV VIN = VCIN = 6 V to 60 V 30 - - mA
VDRV UVLO threshold, rising VDRV_UVLO 4 4.25 4.5 V
VDRV UVLO hysteresis VDRV_UVLO_HYST - 295 - mV
Input current IVCIN Non-switching, VFB > 0.8 V - 235 325
μA
Shutdown current IVCIN_SHDN VEN = 0 V - 4 8
Controller and Timing
TJ = 25 °C 796 800 804
Feedback voltage VFB m/V
TJ = -40 °C to +125 °C (1) 792 800 808
VFB input bias current IFB - 2 - nA
Transconductance gm - 0.3 - mS
COMP source current ICOMP_SOURCE 15 20 -
μA
COMP sink current ICOMP_SINK 15 20 -
Minimum on-time tON_MIN. - 90 110 ns
tON accuracy tON_ACCURACY -10 - 10 %
On-time range tON_RANGE 110 - 8000 ns
Ultrasonic mode enabled 20 - 2000
Frequency range fsw kHz
Ultrasonic mode disabled 0 - 2000
Minimum off-time tOFF_MIN. 190 250 310 ns
Soft start current ISS 3 5 7 μA
Soft start voltage VSS When VOUT reaches regulation - 1.5 - V

S21-1142-Rev. P, 29-Nov-2021 4 Document Number: 65124

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ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, VEN = 5 V, TJ = -40 °C to +125 °C, unless otherwise stated)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Fault Protections
SiC461 (10 A),
10.4 13 15.6
RILIM = 60 kΩ, TJ = -10 °C to +125 °C
SiC462 (6 A),
6.4 8 9.6
RILIM = 60 kΩ, TJ = -10 °C to +125 °C
Valley current limit IOCP A
SiC463 (4 A),
4.8 6 7.2
RILIM = 40 kΩ, TJ = -10 °C to +125 °C (2)
SiC464 (2 A),
3.2 4 4.8
RILIM = 60 kΩ, TJ = -10 °C to +125 °C
Output OVP threshold VOVP - 20 -
VFB with respect to 0.8 V reference %
Output UVP threshold VUVP - -80 -
TOTP_RISING Rising temperature - 150 -
Over temperature protection °C
TOTP_HYST Hysteresis - 35 -
Power Good
VFB_RISING_VTH_OV VFB rising above 0.8 V reference - 20 -
Power good output threshold %
VFB_FALLING_VTH_UV VFB falling below 0.8 V reference - -10 -
Power good hysteresis VFB_HYST - 50 - mV
Power good on resistance RON_PGOOD - 7.5 15 Ω
Power good delay time tDLY_PGOOD 15 25 35 μs
EN / MODE / Ultrasonic Threshold
EN logic high level VEN_H - 1.35 -
EN logic low level VEN_L - 1.2 - V
EN hysteresis VHYST - 0.15 -
EN pull down resistance REN - 5 - MΩ
Ultrasonic mode high Level VULTRASONIC_H 2 - -
V
Ultrasonic mode low level VULTRASONIC_L - - 0.8
Mode pull up current IMODE 3.75 5 6.25 μA
Power save mode enabled, VDD, VDRV
Mode 1 0 2 100
Pre-reg on
Power save mode disabled, VDD, VDRV
Mode 2 298 301 304
Pre-reg on
RMODE kΩ
Power save mode disabled, VDRV Pre-reg
Mode 3 494 499 504
off, VDD Pre-reg on, provide external VDRV
Power save mode enabled, VDRV Pre-reg off,
Mode 4 900 1000 1100
VDD Pre-reg on, provide external VDRV
Notes
(1) Guaranteed by design
(2) Guaranteed by design for SiC463 OCP measurements

S21-1142-Rev. P, 29-Nov-2021 5 Document Number: 65124

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FUNCTIONAL BLOCK DIAGRAM
VCIN BOOT VIN

VDRV VDRV Sync

regulator rectifier
VDD
VDD
regulator VDD UVLO HS UVLO

EN Enable

fSW tON
On time
ULTRASONIC generator Min. tOFF
VDD HS
driver
5 μA
PHASE

MODE MODE
SW
Control
VSNS logic
Ramp VDRV
PWM
COMP
COMP
VDD LS
0.8 V driver
5 μA Reference
PHASE Zero
crossing GL
SS OTA

PGOOD

VFB Over voltage

under voltage
VFB
Power good
ILIMIT Over Over
PHASE current temperature

AGND PGND

Fig. 4 - SiC46x Functional Block Diagram

OPERATIONAL DESCRIPTION
Device Overview Power Stage
SiC46x is a high efficiency synchronous buck regulator SiC46x integrates a high performance power stage with a
family capable of delivering up to 10 A continuous current. n-channel high side MOSFET and a n-channel low side
The device has programmable switching frequency of MOSFET optimized to achieve up to 98 % efficiency.
100 kHz to 2 MHz. The voltage mode, constant on time The power input voltage (VIN) can go up to 60 V and down
control scheme delivers fast transient response, minimizes as low as 4.5 V for power conversion.
the number of external components and enables loop
stability regardless of the type of output capacitor used, Control Scheme
including low ESR ceramic capacitors. The device also SiC46x employs a voltage mode COT control mechanism in
incorporates a power saving feature that enables diode conjunction with adaptive zero current detection which
emulation mode and frequency fold back as the load allows for power saving in discontinuous conduction mode
decreases. (DCM). The switching frequency, fSW, is set by an external
resistor to AGND, Rfsw. The SiC46x operates between
SiC46x has a full set of protection and monitoring features:
100 kHz to 2 MHz depending on VIN and VOUT conditions.
• Over current protection in pulse-by-pulse mode
V OUT
• Output overvoltage protection R fsw = --------------------------------------------
-
-12
• Output undervoltage protection with auto retry f sw × 190 × 10
• Over temperature protection with hysteresis Note, as long as VIN and VCIN are connected together, fSW
has no dependency on VIN as the on time is adjusted as VIN
• Dedicated enable pin for easy power sequencing
varies. During steady-state operation, feedback voltage
• Power good open drain output (VFB) is compared with internal reference (0.8 V typ.) and the
• This device is available in MLP55-27L package to deliver amplified error signal (VCOMP) is generated at the comp node
high power density and minimize PCB area by the external compensation components, RCOMP and
CCOMP. An externally generated ramp signal and VCOMP feed
into a comparator. Once VRAMP crosses VCOMP, an on-time

S21-1142-Rev. P, 29-Nov-2021 6 Document Number: 65124

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pulse is generated for a fixed time. During the on-time pulse,
the high side MOSFET will be turned on. Once the on-time VIN
pulse expires, the low side MOSFET will be turned on after
a dead time period. The low side MOSFET will stay on for a Q1
L
minimum duration equal to the minimum off-time (tOFF_MIN.)
and remains on until VRAMP crosses VCOMP. The cycle is then Q2 Rx Cx
repeated. COUT
CIN Cy
Fig. 6 illustrates the basic block diagram for voltage mode, Ripple R_FB_H Load
constant on time architecture with external ripple injection, based
controller EA REF
VRAMP, while Fig. 5 illustrates the basic operational principle. R_FB_L
RCOMP
CCOMP
VRAMP
Fig. 6 - SiC46x Control Block Diagram

VCOMP Below is the equation for calculating the VRAMP amplitude.

( V IN – V OUT ) × V OUT
V RAMP = ------------------------------------------------------
( V IN × f sw × C x × R x )
PWM
Fixed on-time VRAMP amplitude is a function of VIN, VOUT, and switching
Fig. 5 - SiC46x Operational Principle frequency and should be adjusted whenever VIN, VOUT, or
The need for ripple injection in this architecture is explained switching frequency is changed.
below. First, let us understand the basic principles of this For a given buck regulator design, VOUT and switching
control architecture: frequency is typically fixed, while the converter may be
expected to work for a wide VIN range. The VRAMP amplitude
• The reference of a basic voltage mode COT regulator will increase as VIN is increased and increase the power
is replaced with a high gain error amplifier loop. The loop dissipated by Rx. A proper selection of RX, package size and
ensures the DC component of the output voltage follows value, should take into account the maximum power
the internal accurate reference voltage, providing dissipation at the expected operating conditions.
excellent regulation In order to optimize the VRAMP amplitude over a desired VIN
• A second voltage feedback path via VSNS with a VRAMP range use the following procedure to calculate Rx, Cx, and
scheme ensures rapid correction of the transient Cy.
perturbation 1. The equation below calculates RX as a function of VIN,
• This establishes two voltage loops, one is the steady state VOUT, and maximum allowable power dissipated by RX.
voltage feedback path (via the FB pin) and the other is the V IN_MAX. × V OUT × ( 1 – D )
feed forward path (via the VSNS pin). The scheme gives the R x = --------------------------------------------------------------------
P RX_MAX.
user the fast transient response of a COT regulator and
the stable, jitter free, line and load regulation performance where PRX_MAX. is the maximum allowed power
of a PWM controller dissipation in Rx. Note, the maximum power dissipation
of a 0603 sized resistor is typically 25 mW. Power
Choosing the Ripple Injection Component Values
dissipation derating must be taken into account for high
For stability purposes the SiC46x requires adequate ripple ambient temperatures
injection amplitude. Adequate ripple amplitude is required 2. The equation below calculates CX_MIN. as a function of
for two main reasons: VIN and maximum allowed VRAMP amplitude.
1. To reduce jitter due to noise coupled into the system P RX_MAX.
2. To provide stable operation. Sub harmonic oscillation C X_MIN. = ---------------------------------------------------------------------------
V IN_MAX. × f sw × V RAMP_MAX.
can occur with constant on time ripple control if below
condition is not met where VRAMP_MAX. = 900 mV
3. Using VRAMP equation, calculate VRAMP_MIN. at minimum
t ON
ESR × C OUT > --------- VIN based on the Rx and the minimum Cx value
2 calculated above
Therefore, when the converter design uses an all ceramic 4. If VRAMP_MIN. is > 200 mV, set Cx to CX_MIN., otherwise set
output capacitor or other low ESR output capacitors, Cx to (Cx_MIN. x VRAMP_MIN./200 mV). If VRIPPLE_MIN. is
instability can occur. In order to avoid this, a VRAMP network < 100 mV, increase PRX_MAX. and recalculate RX and CX
is used to increase the equivalent RESR in order to satisfy the 5. Cy should be large enough not to distort the VRAMP and
above condition. The VRAMP amplitude must be large small enough not to load excessively the VRAMP network
enough to avoid instability or noise sensitivity but not too (Rx and Cx). Please use the follow formula:
large that it degrades transient performance. To ensure Cy = 1/(820 x fsw)
stable operation under CCM, DCM and ultrasonic mode, This procedure allows for a maximum range of operation.
minimum VRAMP amplitude of 100 mV is recommended for
the SiC46x family of regulators. A maximum VRAMP of
900 mV is recommended so as not to degrade transient
response.
S21-1142-Rev. P, 29-Nov-2021 7 Document Number: 65124
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Error Amplifier Compensation Value Selection (for reference only)
RCOMP and CCOMP in the Fig. 6 are the components used to compensate the control loop.
For optimal transient response, the crossover frequency should be:
• Set typically at 1/10th to 1/5th of the converter switching frequency (Vishay’s component calculator tool uses 1/10th the
converter switching frequency)
• Be above the LC filter resonance frequency which is 1/2 π LC

The procedure to select the RCOMP and CCOMP such that the above conditions are met is as follows:

1. Plot the magnitude and phase of the control to output transfer function using the equation below.
Control to output transfer function.

1 + sR C C o × ( 1 + sR x C x ) × ( 1 + sR y C y )
H(s) = A × --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 1 + ------ sL
- + s LC o × ( 1 + sR x C x ) × ( 1 + sR y C y ) + AR y C y s × 1 + s ×  R x C x + ------- + s × ( R x R c C x C o + LC o )
2 L 2
 Ro   R o

Where A = (2VIN x Rx x Cx x f)/VOUT, Rx, Cx, Cy are components for ripple injection as shown in Fig. 6 and Ry is the internal
impedance of the VSNS pin and is = 65 kΩ.
Co - output capacitance
Rc - output capacitor ESR

2. From the plot of the control to output transfer function, determine the gain and phase at the crossover frequency

3. Calculate the RCOMP using the equation

1
R COMP = --------------------------------------
G H × gm × r FB

where GH is the gain of the transfer function at cross over frequency, “gm” is the transconductance of the error amplifier
(300 μS) and rFB is the ratio of the feedback divider, rFB = R_FB_L/(R_FB_L + R_FB_H)

4. Select CCOMP based on the placement of the zero such that phase margin is sufficient at the cross over frequency. A phase
margin of over 60° is sufficient for converter stability. A good starting point is to place the compensation zero at 1/5th of the
LC pole
5 LC
C COMP = -------------------
R COMP
Once the component values are calculated, it is now possible to calculate the total loop gain. The total loop gain is the product
of the control to output transfer function and the error amplifier transfer function.
The transfer function of the error amplifier is given by the equation below.
( 1 + sR COMP C COMP ) × r FB
G ( s ) = gmR o × -----------------------------------------------------------------------------------------------------
( 1 + s × ( R COMP C COMP + R o C COMP ) )
Where Ro = 40 MΩ is the output resistance of the transconductance amplifier.
Total loop transfer function = H(s)G(s)

S21-1142-Rev. P, 29-Nov-2021 8 Document Number: 65124

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Power-Save Mode, Mode Pin, and Ultrasonic Pin Operation
To improve efficiency at light-loads, SiC46x provides a set To improve the converter efficiency, the user can choose to
of innovative implementations to reduce low side disable the internal VDRV regulator by picking either mode 3
re-circulating current and switching losses. The internal zero or mode 4 and connecting a 5 V supply to the VDRV pin. This
crossing detector monitors SW node voltage to determine reduces power dissipation in the SiC46x by eliminating the
when inductor current starts to flow negatively. In power VDRV linear regulator losses.
saving mode, as soon as inductor current crosses zero, the The mode pin supports several modes of operation as
device first deploys diode mode by turning off the low side shown in table 1. An internal current source is used to set
MOSFET. If load further decreases, switching frequency is the voltage on this pin using an external resistor:
reduced proportional to the load condition to save switching
losses while keeping output ripple within tolerance. If the TABLE 1 - OPERATION MODES
ultrasonic pin is tied to VDD, the minimum switching POWER SAVE INTERNAL VDRV
frequency in discontinuous mode is > 20 kHz to avoid MODE RANGE (kΩ)
MODE REGULATOR
switching frequencies in the audible range. If this feature is 1 0 to 100 Enabled ON
not required ultrasonic mode can be disabled by floating the 2 298 to 304 Disabled ON
ULTRASONIC pin. When ultrasonic mode is disabled, the 3 494 to 504 Disabled OFF (1)
regulator will operate in forced continuous mode or power 4 900 to 1100 Enabled OFF (1)
save mode where there is no limit to the lower frequency
limit. In this state, at zero load, switching frequency can go Note
(1) Connect a 5 V (± 5 %) supply to the V
as low as hundreds of hertz. DRV pin
The mode pin is not latched to any state and can be
changed on the fly.
OUTPUT MONITORING AND PROTECTION FEATURES
Output Over-Current Protection (OCP)
SiC46x has pulse-by-pulse over current limit control. The
inductor current is monitored during low side MOSFET Over Temperature Protection (OTP)
conduction time through RDS(on) sensing. After a pre-defined OTP is implemented by monitoring the junction
blanking time, the inductor current is compared with an temperature. If the junction temperature rises above 150 °C,
internal OCP threshold. If inductor current is higher than a OTP event is recognized and both high side and low
OCP threshold, high side MOSFET is kept off until the MOSFETs are turned off. After the junction temperature falls
inductor current falls below OCP threshold. below 115 °C (35 °C hysteresis), the device restarts by
OCP is enabled immediately after VDD passes UVLO level. initiating a soft start sequence.
OCP is set by an external resistor, RLIM to AGND. (See table 2) Sequencing of Input / Output Supplies
SiC46x has no sequencing requirements on its supplies or
enables (VIN, VCIN, VDD, VDRV, EN).
OCPthreshold Enable
The SiC46x has an enable pin to turn the part on and off.
Iload Driving this pin above 1.35 V enables the device, while
Iinductor driving the pin below 1.2 V disables the device.
The EN pin is internally pulled to AGND by a 5 MΩ resistor to
prevent unwanted turn on due to a floating GPIO.
GH Soft-Start
During soft start time period, inrush current is limited and the
Fig. 7 - Over-Current Protection Illustration output voltage is ramped gradually. The following control
scheme is implemented:
Output Undervoltage Protection (UVP) Once the VDD voltage reaches the UVLO trip point, an
internal “Soft start Reference” (SR) begins to ramp up. The
UVP is implemented by monitoring the FB pin. If the voltage
SR ramp rate is determined by the external soft start
level at FB drops below 0.16 V for more than 25 μs, a UVP
capacitor and an internal 5 μA current source tied to the soft
event is recognized and both high side and low side
start pin.
MOSFETs are turned off. After a duration equivalent to
The internal SR signal is used as a reference voltage to the
20 soft start periods, the IC attempts to re-start. If the fault
error amplifier (see functional block diagram). The control
condition still exists, the above cycle will be repeated.
scheme guarantees that the output voltage during the soft
UVP is only active after the completion of soft-start start interval will ramp up coincidently with the SR voltage.
sequence. The soft-start time, tSS, is adjustable by calculating a
Output Over Voltage Protection (OVP) capacitor value from the following equation.
OVP is implemented by monitoring the FB pin. If the voltage C ss x 0.8 V
level at FB rising above 0.96 V, a OVP event is recognized t ss = ------------------------------
and both high side and low side MOSFETs are turned off. 5 μA
Normal operation is resumed once FB voltage drop below During soft-start period, OCP is activated. Short circuit
0.91 V. protection is not active until soft-start is complete.

S21-1142-Rev. P, 29-Nov-2021 9 Document Number: 65124

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Pre-Bias Start-Up Power Good
In case of pre-bias startup, output is monitored through FB SiC46x’s power good is an open-drain output. Pull PGOOD
pin. If the sensed voltage on FB is higher than the internal pin high through a > 10K resistor to use this signal. Power
reference ramp value, control logic prevents high side and good window is shown in Fig. 9. If voltage on FB pin is out
low side MOSFETs from switching to avoid negative output of this window, PGOOD signal is de-asserted by pulling down
voltage spike and excessive current sinking through low to AGND. To prevent false triggering during transient events,
PGOOD has a 25 μs blanking time.
side MOSFET.

VFB_Rising_Vth_OV
(typ. = 0.96 V) VFB_Falling_Vth_OV
(typ. = 0.91 V)
Vref (0.8 V)
VFB_Falling_Vth_UV
VFB (typ. = 0.72 V) VFB_Rising_Vth_UV
(typ. = 0.77 V)

Pull-high
PG

Pull-low

Fig. 8 - Pre-Bias Start-Up Fig. 9 - PGOOD Window

EXAMPLE SCHEMATIC OF SiC462

EN

R_ EN _ H R_ EN _ L

560K DNP
R_ U _ SONIC

Zero ohm ultrasonic select

R_ boot

PGOOD
0.1 μF
3.3
C_ boot

R_ PGD

102K Css 33 nF
2
18

19
3

Rmode
EN

PHASE2

PHASE1

BOOT

ULTRASONIC

PGOOD

SS

Notes in small black text near 27

component values refer to Vishay Mode
1 2K
SiC46X spreadsheet calcualtor VCIN
references 29 26 Cdd 1 μF
VIN-PAD VDD
+ VIN 7
VIN1 Rlim
6 V to 60 V 8 25
VIN2 ILIMIT
60.4K
Cin _ D
24 R_ fsw
0.1μF 28
AGND-PAD fSW
30 52.3K
PGND-PAD SiC462
23
9 AGND
PGND1
10
PGND2 22 R_ FB_ L
11 VFB
PGND3 10 K470pF
17 21 232K
Cin PGND COMP
47 μF Rcomp
Ccomp
SW1

SW2

SW3

VSNS
VDRV
GL

AGND
12

13

14

20
15

16

Analog ground (AGND), and 52.3K R_ FB_ H

2.2nF
power ground (PGND) are 8.66K Cy 1.8nF
tied internally in the SiC46X
Rx 4.7μH
Cx
+ Vout = 5 V
L 0.1μF 64 μF 64 μF
Cdrv 4.7μF
Cout _ D Cout _ C Cout _ B

PGND

Fig. 10 - SiC462 Configured for 6 V to 60 V Input, 5 V Output at 6 A, 500 kHz Operation with Ultrasonic Power Save Mode Enabled
all Ceramic Output Capacitance Design

S21-1142-Rev. P, 29-Nov-2021 10 Document Number: 65124

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EXTERNAL COMPONENT SELECTION FOR THE SiC46x
This section explains external component selection for the higher or lower percentages of IOUT can be acceptable
SiC46x family of regulators. Component reference depending on application. This device allows choices larger
designators in any equation refer to the schematic shown in than 30 %.
Fig. 10. Other than the inductance the DCR and saturation current
The online simulation tool PowerCAD helps to make external parameters are key values. The DCR causes an I2R loss
component calculation simple. The user simply needs to which will decrease the system efficiency and generate
enter required operating conditions. heat. The saturation current has to be higher than the
maximum output current plus ½ of the ripple current. In an
Output Voltage Adjustment over current condition the inductor current may be very high.
If a different output voltage is needed, simply change the All this needs to be considered when selecting the inductor.
value of VOUT and solve for R_FB_H based on the following
Output Capacitor Selection
formula:
The SiC46x is stable with any type of output capacitors by
R _FB_L ( V OUT - V FB ) choosing the appropriate VRAMP components. This allows
R _FB_H = ----------------------------------------------------- the user to choose the output capacitance based on the
V FB
best trade off of board space, cost and application
where VFB is 0.8 V. R_FB_L should be a maximum of 10 kΩ to requirements.
prevent VOUT from drifting at no load. The output capacitors are chosen based upon required ESR
Switching Frequency Selection and capacitance. The maximum ESR requirement is
controlled by the output ripple voltage requirement and the
The following equation illustrates the relationship between DC tolerance. The output voltage has a DC value that is
frequency, VIN, VOUT, and Rfsw value: equal to the valley of the output ripple plus half of the
V OUT peak-to-peak ripple. A change in the output ripple voltage
R fsw = ---------------------------------------------------
– 12
- will lead to a change in DC voltage at the output. The
f sw x ( 190 x 10 )
relationship between output voltage ripple, output
Inductor Selection capacitance and ESR of the output capacitor is shown by
the following equation:
In order to determine the inductance, the ripple current must
first be defined. Low inductor values allow for the use of
V RIPPLE = I RIPPLE ( MAX. ) x  --------------------------------- + ESR
1
smaller package sizes but create higher ripple current which  8 x C o x f sw  (1)
can reduce efficiency. Higher inductor values will reduce the
ripple current and, for a given DC resistance, are more Where VRIPPLE is the maximum allowed output ripple
efficient. However, larger inductance translates directly into voltage; IRIPPLE(MAX.) is the maximum inductor ripple current;
larger packages and higher cost. Cost, size, output ripple, fsw is the switching frequency of the converter; Co is the total
and efficiency are all used in the selection process. output capacitance; ESR is the equivalent series resistance
The ripple current will also set the boundary for power save of the total output capacitors.
operation. The SiC46x will typically enter power save mode In addition to the output ripple voltage requirement, the
when the load current decreases to 1/2 of the ripple current. output capacitors need to meet transient requirements. A
For example, if ripple current is 1.8 A, power save operation worst case load release condition (from maximum load to no
will be active for loads less than 0.9 A. If ripple current is set load at the exact moment when inductor current is at the
at 30 % of maximum load current, power save will typically peak) determines the required capacitance. If the load
start at a load which is 15 % of maximum current. release is instantaneous (load changes from maximum to
zero within 1 μs), the output capacitor must absorb all the
The inductor value is typically selected to provide ripple
energy stored in the inductor. The peak voltage on the
current of 25 % to 50 % of the maximum load current. This capacitor, VPK, under this worst case condition can be
provides an optimal trade-off between cost, efficiency, and calculated by following equation:
transient performance. During the on-time, voltage across
2
L x  I OUT + --- x I RIPPLE(MAX.)
the inductor is (VIN - VOUT). The equations for determining 1
inductance are shown below.  2 
C OUT_MIN. = -------------------------------------------------------------------------------
- (2)
2 2
V OUT ( V PK ) - ( V OUT )
t ON = ------------------------
V IN x f sw During the load release time, the voltage across the inductor
and is approximately -VOUT. This causes a down-slope or falling
di/dt in the inductor. If the load di/dt is not much faster than
( V IN - V OUT ) x t ON the di/dt of the inductor, then the inductor current will tend
L = --------------------------------------------------
I OUT_MAX. x K to track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
where, K is the maximum percentage of ripple current. The
capacitor; therefore a smaller capacitance can be used. The
designer can quickly make a choice of inductor if the ripple
following can be used to calculate the required capacitance
percentage is decided, usually no more than 30 % however
for a given diLOAD/dt.

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Peak inductor current, ILPK, is shown by the next equation: final application specification. The input current needs to be
determined for the lowest operating input voltage,
1
I LPK = I MAX. + --- x I RIPPLE(MAX.)
2 I VCIN ( RMS ) =

di LOAD V OUT 2
D x ( 1 – D ) + ------ ×  ------------------------------------- × ( 1 – D ) × D
1 2
The slew rate of load current = ------------------- IO x
dt 12  L × ƒ sw × I OUT

I LPK I MAX. The minimum input capacitance can then be found,

L x -------------- - ------------------- x dt D x (1 - D)
V OUT dI LOAD C VIN_MIN. = I OUT x -----------------------------------------
C OUT_MIN. = I LPK x --------------------------------------------------------------- (3)
2 ( V PK - V OUT ) V IN_PK-PK x f sw

Based on application requirement, either equation (2) or If high ESR capacitors are used, it is good practice to also
equation (3) can be used to calculate the ideal output
add low ESR ceramic capacitance. A 4.7 μF ceramic input
capacitance to meet transition requirement. Compare this
capacitance is a suitable starting point.
calculated capacitance with the result from equation (1) and
Note, account for voltage derating of capacitance when
choose the larger value to meet both ripple and transition
requirement. using all ceramic input capacitors.

Enable Pin Voltage

Efficiency Measurement
The EN pin has an internal 5 MΩ pull down resistor
connected to AGND. In order to enable the device, an Fig. 11 to 39 in the following pages are the efficiency data
external signal greater than 1.4 V is required. The enable can for the SiC461, SiC462, SiC463, and SiC464.
also be used to set the minimum VCIN, VIN startup voltage by The measurements are taken based on the Vishay 6 layers,
connecting a voltage divider between VIN, EN, and PGND. An 2 ounce copper evaluation board.
automated calculator is available to assist in component The inductors used in the measurement are tabulated
selection. below.

Current Limit Resistor

TABLE 3 - INDUCTOR VALUES
The current limit is set by placing a resistor between ILIM and
DEVICE INDUCTANCE INDUCTOR PART DCR
AGND. The values can be found using the following equation: PART (μH) NUMBER (mΩ)
3.3 IHLP6767GZER3R3M11 2.79
K LIM
R LIM (kΩ ) = ---------------------------------------------------------------------------------------- 4.7 IHLP6767GZER4R7M11 3.98
( V IN – V OUT ) × V OUT SiC461 6.8 IHLP6767GZER6R8M11 5.86
I OUT_MAX. – ------------------------------------------------------
2 × f sw × V IN × L 8.2 IHLP6767GZER8R2M11 7.71
Where 10 IHLP6767GZER100M11 8.89
• IOUT_MAX. is desired DC current limit level 5.6 IHLP5050FDER5R6M51 8.51
6.8 IHLP5050FDER6R8M51 11.30
• KLIM is determined by Table 2
SiC462 8.2 IHLP5050FDER8R2M51 13.20
10 IHLP5050FDER100M51 16.60
TABLE 2 - KLIM VALUE 15 IHLP5050FDER150M51 24.00
PART NUMBER KLIM 10 IHLP5050FDER100M51 16.60
SiC461 780K SiC463 15 IHLP5050FDER150M51 24.00
SiC462 480K 22 IHLP5050FDER220M51 31.30
SiC463 240K 10 IHLP5050FDER100M51 16.60
SiC464 240K SiC464 15 IHLP5050FDER150M51 24.00
Note 22 IHLP5050FDER220M51 31.30
• It is suggested that the current limit setting not be higher than
2 times the rated current of the part. Be sure max. current limit
is within the saturation current of the inductor

Input Capacitance
In order to determine the minimum capacitance the input
voltage ripple needs to be specified; VIN_PK-PK ≤ 500 mV is a
suitable starting point. This magnitude is determined by the

S21-1142-Rev. P, 29-Nov-2021 12 Document Number: 65124

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC461 (10 A), unless otherwise noted)

100 100
VIN = 12 V, L = 3.3 μH VIN = 12 V, L = 3.3 μH
98 VIN = 24 V, L = 4.7 μH 97
VIN = 24 V, L = 4.7 μH
96 94

94 91

92 88
Efficiency (%)

Efficiency (%)
90 85
VIN = 36 V, L = 4.7 μH
88 82 VIN = 36 V, L = 4.7 μH

86 79
VIN = 48 V, L = 4.7 μH VIN = 48 V, L = 4.7 μH
84 76

82 73

80 70
0 1 2 3 4 5 6 7 8 9 10 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 11 - SiC461 Efficiency vs. Output Current, Fig. 14 - SiC461 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100
VIN = 24 V, L = 6.8 μH
98 97 VIN = 24 V, L = 6.8 μH

96 94

94 91
VIN = 36 V, L = 8.2 μH VIN = 36 V, L = 8.2 μH
92 88
Efficiency (%)

Efficiency (%)

VIN = 48 V, L = 10 μH
90 VIN = 48 V, L = 10 μH 85

88 82

86 79

84 76

82 73

80 70
0 1 2 3 4 5 6 7 8 9 10 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 12 - SiC461 Efficiency vs. Output Current, Fig. 15 - SiC461 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

100 100

90 90

80 80
Case Temperature(°C)

Case Temperature (°C)

70 70

60 60

50 50

40 40

30 30

20 20
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
Output Current (A) Output Current (A)

Fig. 13 - SiC461 Load Current vs. Case Temperature, Fig. 16 - SiC461 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1142-Rev. P, 29-Nov-2021 13 Document Number: 65124

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)

100 100
VIN = 12 V, L = 5.6 μH VIN = 12 V, L = 5.6 μH
98 VIN = 24 V, L = 6.8 μH 97
VIN = 24 V, L = 6.8 μH
96 94

94 91

92 88
Efficiency (%)

Efficiency (%)
90 85
VIN = 36 V, L = 8.2 μH
88 VIN = 48 V, L = 8.2 μH
82 VIN = 36 V, L = 8.2 μH

86 79
VIN = 48 V, L = 8.2 μH
84 76

82 73

80 70
0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.0 0.1 1.0

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 17 - SiC462 Efficiency vs. Output Current, Fig. 20 - SiC462 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100
VIN = 24 V, L = 10 μH VIN = 24 V , L = 10 μH
98 97

96 94

94 91
VIN = 36 V, L = 15 μH
92 88
Efficiency (%)

Efficiency (%)

VIN = 36 V, L = 15 μH
90 85
VIN = 48 V, L = 15 μH
88 82 VIN = 48 V, L = 15 μH

86 79

84 76

82 73

80 70
0.0 1.0 2.0 3.0 4.0 5.0 6.0 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 18 - SiC462 Efficiency vs. Output Current, Fig. 21 - SiC462 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

100 100

90 90

80 80
Case Temperature (°C)

Case Temperature (°C)

70 70

60 60

50 50

40 40

30 30

20 20
0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
Output Current (A) Output Current (A)

Fig. 19 - SiC462 Load Current vs. Case Temperature, Fig. 22 - SiC462 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1142-Rev. P, 29-Nov-2021 14 Document Number: 65124

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC463 (4 A), unless otherwise noted)

100 100
VIN = 24 V, L = 15 μH VIN = 12 V, L = 10 μH
VIN = 12 V, L = 10 μH VIN = 24 V, L = 15 μH
98 97

96 94

94 91

92 88
Efficiency (%)

Efficiency (%)
90 VIN = 36 V, L = 15 μH 85

88 82
VIN = 48 V, L = 15 μH VIN = 36 V, L = 15 μH
86 79

84 76 VIN = 48 V, L = 15 μH

82 73

80 70
0.0 1.0 2.0 3.0 4.0 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 23 - SiC463 Efficiency vs. Output Current, Fig. 26 - SiC463 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100
VIN = 24 V, L = 15 μH
98 97 VIN = 24 V, L = 15 μH

96 94

94 91
VIN = 36 V, L = 22 μH
92 88
Efficiency (%)

Efficiency (%)

VIN = 36 V, L = 22 μH
90 85
VIN = 48 V, L = 22 μH
88 VIN = 48 V, L = 22 mH 82

86 79

84 76

82 73

80 70
0.0 1.0 2.0 3.0 4.0 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 24 - SiC463 Efficiency vs. Output Current, Fig. 27 - SiC463 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

100 100

90 90

80 80
Case Temperature (°C)
Case Temperature (°C)

70 70

60 60

50 50

40 40

30 30

20 20
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Output Current (A) Output Current (A)

Fig. 25 - SiC463 Load Current vs. Case Temperature, Fig. 28 - SiC463 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1142-Rev. P, 29-Nov-2021 15 Document Number: 65124

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC464 (2 A), unless otherwise noted)

100 100
VIN = 12 V, L = 10 μH VIN = 12 V, L = 10 μH
98 VIN = 24 V, L = 15 μH 97 VIN = 24 V, L = 15 μH

96 94

94 91

92 88
Efficiency (%)

Efficiency (%)
90 VIN = 36 V, L = 15 μH 85

88 82
VIN = 36 V, L = 15 μH
86 79
VIN = 48 V, L = 15 μH VIN = 48 V, L = 15 μH
84 76

82 73

80 70
0.0 0.5 1.0 1.5 2.0 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 29 - SiC464 Efficiency vs. Output Current, Fig. 32 - SiC464 Efficiency vs. Output Current - Light Load,
VOUT = 5 V VOUT = 5 V

100 100
VIN = 24 V, L = 15 μH
VIN = 24 V, L = 15 μH
98 97

96 94

94 91

92 88
Efficiency (%)

Efficiency (%)

VIN = 36 V, L = 22 μH
VIN = 36 V, L = 22 μH
90 85
VIN = 48 V, L = 22 μH
88 VIN = 48 V, L = 22 μH 82

86 79

84 76

82 73

80 70
0.0 0.3 0.5 0.8 1.0 1.3 1.5 1.8 2.0 0.01 0.1 1

Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 30 - SiC464 Efficiency vs. Output Current, Fig. 33 - SiC464 Efficiency vs. Output Current - Light Load,
VOUT = 12 V VOUT = 12 V

100 100

90 90

80 80
Case Temperature (°C)

Case Temperature (°C)

70 70

60 60

50 50

40 40

30 30

20 20
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Output Current (A) Output Current (A)

Fig. 31 - SiC464 Load Current vs. Case Temperature, Fig. 34 - SiC464 Load Current vs. Case Temperature,
VIN = 48 V, VOUT = 5 V VIN = 48 V, VOUT = 12 V

S21-1142-Rev. P, 29-Nov-2021 16 Document Number: 65124

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)

1.04 1.04

1.03 1.03

1.02 1.02
Normalized Efficiency

Normalized Efficiency
1.01 1.01

1 1

0.99 0.99

0.98 0.98

0.97 0.97

0.96 0.96
200 250 300 350 400 450 500 550 600 650 700 0 100 200 300 400 500 600 700 800 900 1000
Switching Frequency (kHz) Switching Frequency (kHz)

Fig. 35 - SiC461 Efficiency vs. Switching Frequency Fig. 38 - SiC462 Efficiency vs. Switching Frequency

1.04 1.04

1.03 1.03

1.02 1.02
Normalized Efficiency

Normalized Efficiency

1.01 1.01

1 1

0.99 0.99

0.98 0.98

0.97 0.97

0.96 0.96
0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000
Switching Frequency (kHz) Switching Frequency (kHz)

Fig. 36 - SiC463 Efficiency vs. Switching Frequency Fig. 39 - SiC464 Efficiency vs. Switching Frequency

2.00 808
Normalized On-State Resistance, RDSON

1.75 806
Voltage Reference, VFB (mv)

1.50 804

1.25 802

1.00 800

0.75 798

0.50 796

0.25 794

0.00 792
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Fig. 37 - RDS(ON) vs. Temperature Fig. 40 - Voltage Reference vs. Temperature

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)

0.8 0.8

0.6 0.6

0.4 0.4
Line Regulation (%)

Load Regulation (%)

0.2 0.2

0.0 0.0

-0.2 -0.2

-0.4 -0.4

-0.6 -0.6

-0.8 -0.8
0 6 12 18 24 30 36 42 48 54 60 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
Input Voltage (V) Output Current (A)

Fig. 41 - Line Regulation Fig. 44 - Load Regulation

8.0 8.0
Shutdown Current, IVCIN_SHDN + IVIN_SHDN (uA)
Shutdown Current, IVCIN_SHDN + IVIN_SHDN (uA)

7.0 7.0

6.0 6.0

5.0 5.0

4.0 4.0

3.0 3.0

2.0 2.0

1.0 1.0

0.0 0.0
0 6 12 18 24 30 36 42 48 54 60 -60 -40 -20 0 20 40 60 80 100 120 140
Input Voltage, VCIN / VIN (V) Temperature (°C)

Fig. 42 - Shutdown Current vs. Input Voltage Fig. 45 - Shutdown Current vs. Junction Temperature

300 300

280 280
Input Current, IVCIN + IVIN (uA)
Input Current, IVCIN + IVIN (uA)

260 260

240 240

220 220

200 200

180 180

160 160

140 140
0 6 12 18 24 30 36 42 48 54 60 -60 -40 -20 0 20 40 60 80 100 120 140
Input Voltage, VCIN / VIN (V) Temperature (°C)

Fig. 43 - Input Current vs. Input Voltage Fig. 46 - Input Current vs. Junction Temperature

S21-1142-Rev. P, 29-Nov-2021 18 Document Number: 65124

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)

1.5 1.4
VEN = 5.0 V
1.5
1.3
1.4
EN Logic Threshold, VEN (V)

VIH_EN
1.2
1.4

EN Current, IEN (uA)

1.3 1.1

1.3 1.0
VIL_EN
1.2
0.9
1.2
0.8
1.1

1.1 0.7

1.0 0.6
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Fig. 47 - EN Logic Threshold vs. Junction Temperature Fig. 50 - EN Current vs. Junction Temperature

Fig. 48 - Load Transient (3 A to 6 A), Time = 100 μs/div Fig. 51 - Line Transient (8 V to 48 V), Time = 10 ms/div

Fig. 49 - Start-Up with EN, Time = 1 ms/div Fig. 52 - Start-up with VIN, Time = 5 ms/div

S21-1142-Rev. P, 29-Nov-2021 19 Document Number: 65124

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ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz, SiC462 (6 A), unless otherwise noted)

Fig. 53 - Output Ripple 2 A, Time = 5 μs/div Fig. 55 - Output Ripple 300 mA, Time = 5 μs/div

Fig. 54 - Output Ripple PSM, Time = 10 ms/div

S21-1142-Rev. P, 29-Nov-2021 20 Document Number: 65124

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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling Step 3: SW Plane

VIN Plane

Snubber
PGND Plane
VIN

VSWH

PGND Plane
VSWH

Fig. 58
Fig. 56 1. Connect output inductor to device with large plane to
lower resistance
5. Layout VIN and PGND planes as shown above
2. If any snubber network is required, place the
6. Ceramic capacitors should be placed between VIN and components on the bottom side as shown above
PGND, and very close to the device for best decoupling
effect
Step 4: VDD/VDRV Input Filter
7. Various ceramic capacitor values and package sizes
should be used to cover entire coupling spectrum
e.g. 1210 and 0603
8. Smaller capacitance values, closer to VIN pin(s), provide
better high frequency response
Step 2: VCIN Pin

AGND

Vcin decouple cap

P
G
N
D

AGND Plane

Fig. 59

1. CVDD cap should be placed between VDD and AGND to

Fig. 57
achieve best noise filtering
1. VCIN is the input pin for both internal LDO and tON block. 2. CVDRV cap should be placed close to VDRV and PGND pins
tON varies with input voltage and it is necessary to put a to reduce effects of trace impedance and provide
decoupling capacitor close to this pin maximum instantaneous driver current for low side
2. The connection can be made through a via and the MOSFET during switching cycle
capacitor can be placed at bottom layer

S21-1142-Rev. P, 29-Nov-2021 21 Document Number: 65124

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Step 5: BOOT Resistor and Capacitor Placement Step 6: Signal Routing

AGND
plane

PGND

F
B

s
i
Fig. 60 g
Ripple n
1. CBOOT and RBOOT need to be placed very close to the
injection a
device, between PHASE and BOOT pins l
circuit
2. In order to reduce parasitic inductance, it is
recommended to use 0402 chip size for the resistor and Fig. 61
the capacitor
1. Separate the small analog signal from high current path.
As shown above, the high current paths with high dv/dt,
di/dt are placed on the left side of the IC, while the small
control signals are placed on the right side of the IC. All
the components for small analog signal should be
placed closer to IC with minimum trace length
2. IC analog ground (AGND), pin 23, should have a single
connection to PGND. The AGND ground plane connected
to pin 23 helps to keep AGND quiet and improves noise
immunity
3. Feedback signal can be routed through inner layer. Make
sure this signal is far from SW node and shielded by
inner ground layer
4. Ripple injection circuit can be placed next to inductor.
Kelvin connection as shown above is recommended

S21-1142-Rev. P, 29-Nov-2021 22 Document Number: 65124

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Step 7: Adding Thermal Relief Vias and Duplicate Power Step 8: Ground Layer
Path Plane

VIN Plane AGND Plane

PGND Plane

PGND Plane

VSWH Fig. 63

Fig. 62 1. It is recommended to make the entire inner layer (next to

top layer) ground plane
1. Thermal relief vias can be added on the VIN and PGND 2. This ground plane provides shielding between noise
pads to utilize inner layers for high current and thermal source on top layer and signal trace within inner layer
dissipation 3. The ground plane can be broken into two sections, PGND
2. To achieve better thermal performance, additional vias and AGND
can be placed on VIN and PGND planes. It is also
necessary to duplicate the VIN and ground plane at
bottom layer to maximize the power dissipation
capability of the PCB
3. SW pad is a noise source and it is not recommended to
place vias on this pad
4. 8 mil vias on pads and 10 mil vias on planes are ideal via
sizes. The vias on pad may drain solder during assembly
and cause assembly issues. Please consult with the
assembly house for guideline

S21-1142-Rev. P, 29-Nov-2021 23 Document Number: 65124

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PRODUCT SUMMARY
Part number SiC461 SiC462 SiC463 SiC464
10 A, 4.5 V to 60 V input, 6 A, 4.5 V to 60 V input, 4 A, 4.5 V to 60 V input, 2 A, 4.5 V to 60 V input,
100 kHz to 2 MHz, 100 kHz to 2 MHz, 100 kHz to 2 MHz, 100 kHz to 2 MHz,
Description
synchronous buck synchronous buck synchronous buck synchronous buck
regulator regulator regulator regulator
Input voltage min. (V) 4.5 4.5 4.5 4.5
Input voltage max. (V) 60 60 60 60
Output voltage min. (V) 0.8 0.8 0.8 0.8
Output voltage max. (V) 0.92 x VIN 0.92 x VIN 0.92 x VIN 0.92 x VIN
Continuous current (A) 10 6 4 2
Switch frequency min. (kHz) 100 100 100 100
Switch frequency max. (kHz) 2000 2000 2000 2000
Pre-bias operation (yes / no) Yes Yes Yes Yes
Internal bias reg. (yes / no) Yes Yes Yes Yes
Compensation External External External External
Enable (yes / no) Yes Yes Yes Yes
PGOOD (yes / no) Yes Yes Yes Yes
Overcurrent protection Yes Yes Yes Yes
OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP, OVP, OCP, UVP/SCP,
Protection
OTP, UVLO OTP, UVLO OTP, UVLO OTP, UVLO
Selectable powersave / Selectable powersave / Selectable powersave / Selectable powersave /
Light load mode
ultrasonic ultrasonic ultrasonic ultrasonic
Peak efficiency (%) 98 98 98 98
Package type PowerPAK MLP55-27L PowerPAK MLP55-27L PowerPAK MLP55-27L PowerPAK MLP55-27L
Package size (W, L, H) (mm) 5 x 5 x 0.75 5 x 5 x 0.75 5 x 5 x 0.75 5 x 5 x 0.75
Status code 2 2 2 2
microBUCK microBUCK microBUCK microBUCK
Product type
(step down regulator) (step down regulator) (step down regulator) (step down regulator)
Computing, consumer, Computing, consumer, Computing, consumer, Computing, consumer,
Applications industrial, healthcare, industrial, healthcare, industrial, healthcare, industrial, healthcare,
networking networking networking networking

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?65124.

S21-1142-Rev. P, 29-Nov-2021 24 Document Number: 65124

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 Package Information
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PowerPAK® MLP55-27 Case Outline

Pin 1 dot 2x
D 0.10 C A A 0.08 C
by marking A K4 ex7 K4
A1

0.10 M C A B
27

20

20

27
A2

L
K4

K5
19 1
1 19
D2-1

K E2-1
K1
(4)

e1 x 3
ex4
MLP55-27L
E

(5 mm x 5 mm) D2-4

b1
e1
b

e2
K3

E2-3

E2-2
E2-4
ex2
K2

e
6 D2-3 D2-2
B 12 12 6

K4
K6

11
11

7
7

C F2
F1
K7 ex2 e3 K8
e1
Top view Side view
Bottom view

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.008 0.010 0.012
b1 0.15 0.20 0.25 0.006 0.008 0.010
D 5.00 BSC 0.197 BSC
e 0.50 BSC 0.020 BSC
e1 0.65 BSC 0.026 BSC
e2 1.00 BSC 0.039 BSC
e3 1.13 BSC 0.044 BSC
E 5.00 BSC 0.197 BSC
L 0.35 0.40 0.45 0.014 0.016 0.018
N (3) 28 28
D2-1 3.25 3.30 3.35 0.128 0.130 0.132
D2-2 0.95 1.00 1.05 0.037 0.039 0.041
D2-3 1.95 2.00 2.05 0.077 0.079 0.081
D2-4 1.37 1.42 1.47 0.054 0.056 0.058
E2-1 0.95 1.00 1.05 0.037 0.039 0.041
E2-2 2.55 2.60 2.65 0.100 0.102 0.104
E2-3 2.55 2.60 2.65 0.100 0.102 0.104
E2-4 1.58 1.63 1.68 0.062 0.064 0.066
F1 0.20 - 0.25 0.008 - 0.010
F2 min. 0.20 min. 0.008

Revision: 03-Dec-2018 1 Document Number: 69722

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MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
K 0.40 BSC 0.016 BSC
K1 0.70 BSC 0.028 BSC
K2 0.70 BSC 0.028 BSC
K3 0.30 BSC 0.012 BSC
K4 0.75 BSC 0.030 BSC
K5 0.80 BSC 0.0315 BSC
K6 0.60 BSC 0.024 BSC
K7 1.25 BSC 0.049 BSC
K8 0.975 BSC 0.038 BSC
ECN: T18-0594-Rev. C, 03-Dec-2018
DWG: 6056
Notes
(1) Use millimeters as the primary measurement
(2) Dimensioning and tolerances conform to ASME Y14.5M. - 1994
(3) N is the number of terminals
Nd is the number of terminals in x-direction
Ne is the number of terminals in y-direction
(4) Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
(5) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
(6) Exact shape and size of this feature is optional
(7) Package warpage max. 0.08 mm
(8) Applied only for terminals

Revision: 03-Dec-2018 2 Document Number: 69722

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Recommended Land Pattern
PowerPAK® MLP55-27L

1.25 0.5 x 7 = 3.5 1.25

0.35 0.35
0.95 3.4 0.95

0.5 0.5
27 20

0.35
0.35

0.3

0.75
0.8

1 19
1.1
0.65 x 3 = 1.95

0.5 x 4 = 2
0.3

1.52 0.88

0.58
5

0.97

0.65
1.02
1

2.7

0.5 x 2 = 1
1.73
0.5

6 0.98
0.5 0.5
0.65 1.13
12
0.75

0.6

7 11
0.5

0.5
0.15

0.5

0.95 1.1 2.1 0.95

0.3 0.3 0.3
5

All dimensions in millimeters

Component for MLP55-27L

Land pattern for MLP55-27L

Revision: 24-Jan-18 1 Document Number: 74550

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Disclaimer

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