Scribd
Upload
47 views4 pages

Tutorials Advance Computer Architecture Level 300 Coltech2 - 121547

The document contains questions from a computer architecture tutorial covering the following topics: 1. Data hazards, instruction execution steps, distributed shared memory disadvantages, synchronization benefits, multicore benefits, microprocessor characteristics, RISC and CISC architecture advantages and disadvantages, improving processor performance, and pipelining. It also contains multiple choice questions testing knowledge of RISC, CISC, processor types, architecture comparisons, and other computer architecture concepts.

Uploaded by

Joeybirlem
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
47 views4 pages

Tutorials Advance Computer Architecture Level 300 Coltech2 - 121547

The document contains questions from a computer architecture tutorial covering the following topics: 1. Data hazards, instruction execution steps, distributed shared memory disadvantages, synchronization benefits, multicore benefits, microprocessor characteristics, RISC and CISC architecture advantages and disadvantages, improving processor performance, and pipelining. It also contains multiple choice questions testing knowledge of RISC, CISC, processor types, architecture comparisons, and other computer architecture concepts.

Uploaded by

Joeybirlem
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Tutorials Advance Computer Architecture level 300 Coltech

Section A Structural

1. What are the possible types of data hazards?


2. Here are the four steps involved in instruction execution:
3. Give two disadvantages in Distributed Shared-Memory Architectures
4. Why do we need Synchronization?
5. Write the benefits of a multicore Architecture
6. Give the Characteristics of a micro processor
7. Give 3 advantages and disadvantages of a RISC and CISC architecture
8. Compare a RISC and CISC architecture
9. Give two ways in which we can improve the performance of a processor\
10. What is pipelining, briefly describe the stages of pipelining

1. What is the full form of RISC?


A. Read Instruction Set Architecture
B. Reduced Instruction Set Computer.
C. Register Instruction Set Computer.
D. None of the above
2. What is the full form of CISC?
A. Complex Instruction Set Computer.
B. Completed Instruction Set Computer.
C. Control Instruction Set Computer.
D. None of the above
3. Which Processors includes multi-clocks?
A. Complex Instruction Set Computer
B. Reduced Instruction Set Computer
C. ISA
D. ANNA
4. Which Processors Data transfer Register to register?
A. Complex Instruction Set Computer
B. Reduced Instruction Set Computer
C. ISA
D. ANNA
View Answer
5. The Sun micro systems processors usually follow _____ architecture.
A. CISC
B. ULTRA SPARC
C. ISA
D. RISC
6. Which of the following is true?
A. The RISC processor has a more complicated design than CISC.
B. Risc Focus on software
C. Cisc Focus on software
D. Risc has Variable sized instructions
7. Which processor requires more number of registers?
A. CISC
B. ISA
C. RISC
D. ANNA
8. Both the CISC and RISC architectures have been developed to reduce the ______
A. Semantic gap
B. Time Delay
C. Cost
D. Reduced Code
9. Which of the following is true about CISC processor?
A. Micro programmed control unit is found in CISC.
B. Data transfer is from memory to memory.
C. In this instructions are not register based.
D. All of the above
10. Out of the following which is not a CISC machine.
A. IBM 370/168
B. Motorola A567
C. Intel 80486
D. VAX 11/780
4. Which is the first company who defined RISC architecture?
a) Intel
b) IBM
c) Motorola
d) MIPS
5. Which of the following processors execute its instruction in a single cycle?
a) 8086
b) 8088
c) 8087
d) MIPS R2000

6. How is memory accessed in RISC architecture?


a) load and store instruction
b) opcode instruction
c) memory instruction
7. Which of the following has a Harvard architecture?
a) EDSAC
b) SSEM
c) PIC
d) CSIRAC

8. Which of the following statements are true for von Neumann architecture?
a) shared bus between the program memory and data memory
b) separate bus between the program memory and data memory
c) external bus for program memory and data memory
d) external bus for data memory only
9. What is CAM stands for?
a) content-addressable memory
b) complex addressable memory
c) computing addressable memory
d) concurrently addressable memory

10. Which of the following processors uses Harvard architecture?


a) TEXAS TMS320
b) 80386
c) 80286
d) 8086
11. Which company further developed the study of RISC architecture?
a) Intel
b) Motorola
c) university of Berkeley
d) MIPS
12. Princeton architecture is also known as
a) von Neumann architecture
b) Harvard
c) RISC
d) CISC

13. Who coined the term RISC?


a) David Patterson
b) von Neumann
c) Michael J Flynn
d) Harvard
14. Which of the following is an 8-bit RISC Harvard architecture?
a) AVR
b) Zilog80
c) 8051
d) Motorola 6800
15. Which of the following processors has CISC architecture?
a) AVR
b) Atmel
c) Blackfin
d) Zilog Z80
2). In non-pipelined execution, how the program instructions are executed?
- Sequentially
- Parallel
- Alternatively
- None of the above

You might also like