Instruction Set Reference

4.5.  Ampere Instruction Set

The Ampere architecture (Compute Capability 8.0and 8.6) has the following instruction set
format:
(instruction) (destination) (source1), (source2) ...

Valid destination and source locations include:

‣ RX for registers
‣ URX for uniform registers
‣ SRX for special system-controlled registers
‣ PX for predicate registers
‣ c[X][Y] for constant memory
Table 8 lists valid instructions for the Ampere GPUs.

Table 8. Ampere Instruction Set

Opcode Description
Floating Point Instructions
FADD FP32 Add
FADD32I FP32 Add
FCHK Floating-point Range Check
FFMA32I FP32 Fused Multiply and Add
FFMA FP32 Fused Multiply and Add

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Opcode Description
FMNMX FP32 Minimum/Maximum
FMUL FP32 Multiply
FMUL32I FP32 Multiply
FSEL Floating Point Select
FSET FP32 Compare And Set
FSETP FP32 Compare And Set Predicate
FSWZADD FP32 Swizzle Add
MUFU FP32 Multi Function Operation
HADD2 FP16 Add
HADD2_32I FP16 Add
HFMA2 FP16 Fused Mutiply Add
HFMA2_32I FP16 Fused Mutiply Add
HMMA Matrix Multiply and Accumulate
HMNMX2 FP16 Minimum / Maximum
HMUL2 FP16 Multiply
HMUL2_32I FP16 Multiply
HSET2 FP16 Compare And Set
HSETP2 FP16 Compare And Set Predicate
DADD FP64 Add
DFMA FP64 Fused Mutiply Add
DMMA Matrix Multiply and Accumulate
DMUL FP64 Multiply
DSETP FP64 Compare And Set Predicate
Integer Instructions
BMMA Bit Matrix Multiply and Accumulate
BMSK Bitfield Mask
BREV Bit Reverse
FLO Find Leading One
IABS Integer Absolute Value
IADD Integer Addition
IADD3 3-input Integer Addition
IADD32I Integer Addition
IDP Integer Dot Product and Accumulate
IDP4A Integer Dot Product and Accumulate
IMAD Integer Multiply And Add
IMMA Integer Matrix Multiply and Accumulate
IMNMX Integer Minimum/Maximum
IMUL Integer Multiply

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Opcode Description
IMUL32I Integer Multiply
ISCADD Scaled Integer Addition
ISCADD32I Scaled Integer Addition
ISETP Integer Compare And Set Predicate
LEA LOAD Effective Address
LOP Logic Operation
LOP3 Logic Operation
LOP32I Logic Operation
POPC Population count
SHF Funnel Shift
SHL Shift Left
SHR Shift Right
VABSDIFF Absolute Difference
VABSDIFF4 Absolute Difference
Conversion Instructions
F2F Floating Point To Floating Point Conversion
F2I Floating Point To Integer Conversion
I2F Integer To Floating Point Conversion
I2I Integer To Integer Conversion
I2IP Integer To Integer Conversion and Packing
I2FP Integer to FP32 Convert and Pack
F2IP FP32 Down-Convert to Integer and Pack
FRND Round To Integer
Movement Instructions
MOV Move
MOV32I Move
MOVM Move Matrix with Transposition or Expansion
PRMT Permute Register Pair
SEL Select Source with Predicate
SGXT Sign Extend
SHFL Warp Wide Register Shuffle
Predicate Instructions
PLOP3 Predicate Logic Operation
PSETP Combine Predicates and Set Predicate
P2R Move Predicate Register To Register
R2P Move Register To Predicate Register
Load/Store Instructions
LD Load from generic Memory

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Opcode Description
LDC Load Constant
LDG Load from Global Memory
LDGDEPBAR Global Load Dependency Barrier
LDGSTS Asynchronous Global to Shared Memcopy
LDL Load within Local Memory Window
LDS Load within Shared Memory Window
LDSM Load Matrix from Shared Memory with Element Size Expansion
ST Store to Generic Memory
STG Store to Global Memory
STL Store within Local or Shared Window
STS Store within Local or Shared Window
MATCH Match Register Values Across Thread Group
QSPC Query Space
ATOM Atomic Operation on Generic Memory
ATOMS Atomic Operation on Shared Memory
ATOMG Atomic Operation on Global Memory
RED Reduction Operation on Generic Memory
CCTL Cache Control
CCTLL Cache Control
ERRBAR Error Barrier
MEMBAR Memory Barrier
CCTLT Texture Cache Control
Uniform Datapath Instructions
R2UR Move from Vector Register to a Uniform Register
REDUX Reduction of a Vector Register into a Uniform Register
S2UR Move Special Register to Uniform Register
UBMSK Uniform Bitfield Mask
UBREV Uniform Bit Reverse
UCLEA Load Effective Address for a Constant
UF2FP Uniform FP32 Down-convert and Pack
UFLO Uniform Find Leading One
UIADD3 Uniform Integer Addition
UIADD3.64 Uniform Integer Addition
UIMAD Uniform Integer Multiplication
UISETP Integer Compare and Set Uniform Predicate
ULDC Load from Constant Memory into a Uniform Register
ULEA Uniform Load Effective Address
ULOP Logic Operation

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Opcode Description
ULOP3 Logic Operation
ULOP32I Logic Operation
UMOV Uniform Move
UP2UR Uniform Predicate to Uniform Register
UPLOP3 Uniform Predicate Logic Operation
UPOPC Uniform Population Count
UPRMT Uniform Byte Permute
UPSETP Uniform Predicate Logic Operation
UR2UP Uniform Register to Uniform Predicate
USEL Uniform Select
USGXT Uniform Sign Extend
USHF Uniform Funnel Shift
USHL Uniform Left Shift
USHR Uniform Right Shift
VOTEU Voting across SIMD Thread Group with Results in Uniform
Destination
Texture Instructions
TEX Texture Fetch
TLD Texture Load
TLD4 Texture Load 4
TMML Texture MipMap Level
TXD Texture Fetch With Derivatives
TXQ Texture Query
Surface Instructions
SUATOM Atomic Op on Surface Memory
SULD Surface Load
SUQUERY Surface Query
SURED Reduction Op on Surface Memory
SUST Surface Store
Control Instructions
BMOV Move Convergence Barrier State
BPT BreakPoint/Trap
BRA Relative Branch
BREAK Break out of the Specified Convergence Barrier
BRX Relative Branch Indirect
BRXU Relative Branch with Uniform Register Based Offset
BSSY Barrier Set Convergence Synchronization Point
BSYNC Synchronize Threads on a Convergence Barrier

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Opcode Description
CALL Call Function
EXIT Exit Program
JMP Absolute Jump
JMX Absolute Jump Indirect
JMXU Absolute Jump with Uniform Register Based Offset
KILL Kill Thread
NANOSLEEP Suspend Execution
RET Return From Subroutine
RPCMOV PC Register Move
RTT Return From Trap
WARPSYNC Synchronize Threads in Warp
YIELD Yield Control
Miscellaneous Instructions
B2R Move Barrier To Register
BAR Barrier Synchronization
CS2R Move Special Register to Register
DEPBAR Dependency Barrier
GETLMEMBASE Get Local Memory Base Address
LEPC Load Effective PC
NOP No Operation
PMTRIG Performance Monitor Trigger
R2B Move Register to Barrier
S2R Move Special Register to Register
SETCTAID Set CTA ID
SETLMEMBASE Set Local Memory Base Address
VOTE Vote Across SIMD Thread Group

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