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VHDL Code To Simulate 4-Bit Binary Counter by Software

VHDL code to simulate 4-bit Binary Counter by Software This document describes a VHDL code to simulate a 4-bit binary up counter using a Spartan 3 Starter Kit. It includes a flow chart and code listing. The code uses a process sensitive to the clock and clear signals to increment an internal signal on each rising edge of the clock unless clear is asserted, and assigns the internal signal to the output. Experiments covered include up, down, and up/down counters.

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Ashok kumar
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204 views

VHDL Code To Simulate 4-Bit Binary Counter by Software

VHDL code to simulate 4-bit Binary Counter by Software This document describes a VHDL code to simulate a 4-bit binary up counter using a Spartan 3 Starter Kit. It includes a flow chart and code listing. The code uses a process sensitive to the clock and clear signals to increment an internal signal on each rising edge of the clock unless clear is asserted, and assigns the internal signal to the output. Experiments covered include up, down, and up/down counters.

Uploaded by

Ashok kumar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

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M E R I N T E R N/ VHDL S Hcode
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Starter View Details (/internship/) 

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07 VHDL code to simulate 4-Bit Binary Counter
by software using spartan 3 Starter Kit
(https://www.pantechsolutions.net/vhdl-
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)
code-to-simulate-4-bit-binary-counter-by-
(https://www.pantechsolutions.net/) software-using-spartan-3-starter-kit)
VHDL code to simulate 4-bit Binary Counter by Software
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VHDL code to simulate 4-bit Binary Counter by Software


Experiments Covered
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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

☞Up Counter
SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 
☞Down Counter
Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07
☞Up/Down Counter

Software - Xilinx ISE 9.2


GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)
VHDL code to simulate 4-Bit Binary Counter by software
(https://www.pantechsolutions.net/)
COUNTERS
A counter is a device which stores the number of times a particular event or process has occurred, often in
relationship to a clock signal. There are two types of counters: 0 My Bag
0 item(s) - 0.00
☞up counters (https://www.pantechsolutions.n

☞down counters

Up counters
Each of the higher-order flip-flops are made ready to toggle (both J and K inputs "high") if the Q outputs of all
previous flip-flops are "high." Otherwise, the J and K inputs for that flip-flop will both be "low," placing it into the
"latch" mode where it will maintain its present output state at the next clock pulse. Since the first (LSB) flip-flop
needs to toggle at every clock pulse, its J and K inputs are connected to Vcc or Vdd, where they will be "high" all the
time.

Up Counter (Program for 4-bit binary counter using behavior description)


Description
In this program an up counter has a 1- bit input and a 4- bit output. Additional control signals may be added such
as enable. The output of the multiplexers depends on the level of the select line.

Flow Chart
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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)

(https://www.pantechsolutions.net/)

0 My Bag
0 item(s) - 0.00
(https://www.pantechsolutions.n

Code Listing

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

library IEEE;
SUMM ER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 
use ieee.std_logic_1164.all;
Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07
use ieee.std_logic_unsigned.all;

entity counter is
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/) port(Clock, CLR : in std_logic;

Q : out std_logic_vector(3 downto 0));


(https://www.pantechsolutions.net/)

end counter;

architecture archi of counter is 0 My Bag


0 item(s) - 0.00
signal tmp: std_logic_vector(3 downto 0); (https://www.pantechsolutions.n

begin

process (Clock, CLR)

begin

if (CLR='1') then

tmp <= "0000";

elsif (Clock'event and Clock='1') then

tmp <= tmp + 1;

end if;

end process;

Q <= tmp;

end archi;

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

S UResult
MMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 

SW : PSTYRO-FPGASP3\Code\EXA-8a\..............
Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)

(https://www.pantechsolutions.net/)
Down Counter (Program for 4-bit binary counter using behavior description)
Description
0 My Bag
In this program a down counter has a 1- bit input and a 4- bit output. Additional control signals may be0 item(s)
added such
- 0.00

as enable. The output of the multiplexers depends on the level of the select line. (https://www.pantechsolutions.n

Flow Chart

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)

(https://www.pantechsolutions.net/)

0 My Bag
0 item(s) - 0.00
(https://www.pantechsolutions.n

Code Listing

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

library IEEE;
SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 
use ieee.std_logic_1164.all;
Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07
use ieee.std_logic_unsigned.all;

entity counter is
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/) port(Clock, CLR : in std_logic;

Q : out std_logic_vector(3 downto 0));


(https://www.pantechsolutions.net/)

end counter;

architecture archi of counter is 0 My Bag


0 item(s) - 0.00
signal tmp: std_logic_vector(3 downto 0); (https://www.pantechsolutions.n

begin

process (Clock, CLR)

begin

if (CLR='1') then

tmp <= "0000";

elsif (Clock'event and Clock='1') then

tmp <= tmp + 1;

end if;

end process;

Q <= tmp;

end archi;

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 


Result

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

SW : PSTYRO-FPGASP3\Code\EXA-8a\..............

GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)

up-counter
(https://www.pantechsolutions.net/)

Down Counter (Program for 4-bit binary counter using behavior description)

0 My Bag
Description 0 item(s) - 0.00
(https://www.pantechsolutions.n

In this program a down counter has a 1- bit input and a 4- bit output. Additional control signals may be added such as enable. T

Flow Chart

vhcl-down-counter-flow-chart-of-tyro

Code Listing

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;
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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

S U M M E R Ientity
NTE R N SisH I P - 1 5 t h A P R I L 1 9 - 3 1 t h J U L Y 1 9
counter View Details (/internship/) 

port(Clock, CLR : in std_logic;


Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

Q : out std_logic_vector(3 downto 0));

end counter;
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)
architecture archi of counter is

(https://www.pantechsolutions.net/)
signal tmp: std_logic_vector(3 downto 0);

begin
0 My Bag
process (Clock, CLR) 0 item(s) - 0.00
(https://www.pantechsolutions.n
begin

if (CLR='1') then

tmp <= "1111";

elsif (Clock'event and Clock='1') then

tmp <= tmp - 1;

end if;

end process;

Q <= tmp;

end archi;

end process;

Q <= tmp;

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

end archi;
SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07


Result
SW : PSTYRO-FPGASP3\Code\EXA-8b\..............
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)

(https://www.pantechsolutions.net/)

0 My Bag
Up/Down Counter (Program for 4-bit binary counter using behavior description) 0 item(s) - 0.00
(https://www.pantechsolutions.n
Description
The Up/Down control input line simply enables either the upper string or lower string of AND gates to pass the
Q/Q' outputs to the succeeding stages of flip-flops. If the Up/Down control line is "high," the top AND gates
become enabled. If the Up/Down control line is made "low," the bottom AND gates become enabled.

Flow Chart

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)

(https://www.pantechsolutions.net/)

0 My Bag
0 item(s) - 0.00
(https://www.pantechsolutions.n

Code Listing

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

S U M M E R Ilibrary
N T Eieee;
RNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 
use ieee.std_logic_1164.all;
Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07
use ieee.std_logic_unsigned.all;

entity counter is
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/) port(C, CLR, up_down : in std_logic;

Q : out std_logic_vector(3 downto 0));


(https://www.pantechsolutions.net/)

end counter;

architecture archi of counter is 0 My Bag


0 item(s) - 0.00
signal tmp: std_logic_vector(3 downto 0); (https://www.pantechsolutions.n

begin

process (C, CLR)

begin

if (CLR='1') then

tmp <= "0000";

elsif (C'event and C='1') then

if (up_down='1') then

tmp <= tmp + 1;

else

tmp <= tmp - 1;

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 


end if;

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07


end if;

end process;
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
Q <= tmp;
-us/)

end archi;
(https://www.pantechsolutions.net/)

end process;

Q <= tmp;
0 My Bag
end archi; 0 item(s) - 0.00
(https://www.pantechsolutions.n
end process;

Q <= tmp;

end archi;

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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
-us/)

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0 item(s) - 0.00
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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/) 

Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07

More Information
GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
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GVjaHNvbHV0aW9ucy5uZXQvdmhkbC1jb2RlLXRvLXNpbXVsYXRlLTQtYml0LWJpbmFyeS1jb3VudGVyLWJ5LXNvZnR3YXJlLXVzaW5nLXNwYXJ0YW4tMy1zdGFydGVyLWtpdA,,/)
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boards/psoc3-development-board)
FPGA BOARDS : FPGA Starter Kit (https://www.pantechsolutions.net/cpld-fpga-boards/spartan3an-fpga-project-kit)
(https://www.pantechsolutions.net/) | FPGA Development Board (https://www.pantechsolutions.net/cpld-fpga-
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DSP FLOATING POINT BOARDS : TMS320F2812 Development Board (https://www.pantechsolutions.net/dsp-dsc-boards/tms320f2812-dsp-development-board) | TMS320C6745 DSP Trainner Kit
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board) 0 My Bag
DSP FIXED POINT BOARDS : TMS320C5505 Development Board (https://www.pantechsolutions.net/dsp-dsc-boards/tms320c5505-dsp-development-board) 0 item(s) - 0.00
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RASPBERRY PI : Raspberry Pi 3| Rapserry Pi Accessories
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module-with-base-board)
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Brain Computer Interface (https://www.pantechsolutions.net/sensors/brainsense) | Brainsense (https://www.pantechsolutions.net/sensors/brainsense)
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5/8/2019 VHDL code to simulate 4-bit Binary Counter by Software

MOTOR DRIVES : PMSM Motor Drive (https://www.pantechsolutions.net/power-electronics-and-drives/pmsm-motor-control-using-dspic) | BLDC Motor Drive (https://www.pantechsolutions.net/power-
SUMMER INTERNSHIP - 15th APRIL 19 - 31th JULY 19 View Details (/internship/)
electronics-and-drives/bldc-motor-control-using-dspic) | Three Phase Induction Motor Drive (https://www.pantechsolutions.net/power-electronics-and-drives/three-phase-induction-motor-control-using-dspic)

| SRM Motor Drive (https://www.pantechsolutions.net/power-electronics-and-drives/switched-reluctance-motor-control-using-dspic) | Stepper Motor Drive (https://www.pantechsolutions.net/power-
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Online Sales: 9840974406 | 9003113840 Academic: 9840974408 / 07
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PROJECTS AND RESOURCES


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-us/)
ECE MINI PROJECTS : 8051 Projects (https://www.pantechsolutions.net/8051-projects) | ARM Projects (https://www.pantechsolutions.net/arm7-projects) | FPGA Projects
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(https://www.pantechsolutions.net/)
(https://www.pantechsolutions.net/robotics-projects)
EEE MINI PROJECTS: Electrical Projects | Simulink Projects
DIP PROJECTS : Image Processing Projects (https://www.pantechsolutions.net/image-processing-projects) | Video Processing Projects (https://www.pantechsolutions.net/video-processing-projects)
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PROJECTS AND RESOURCES
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MICROCONTROLLERS IC'S : P89V51RD2 (https://www.pantechsolutions.net/p89v51rd2) | AT89S51 (https://www.pantechsolutions.net/at89s51) | LPC2148
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