Pooja Vashisth

CSC 258
Pooja Vashisth
CSC 258
Pooja Vashisth
This Week’s Learning Goals
Describe a computer as a state machine that interprets instructions.
Explain the organization of a classical, von Neumann style processor
Describe the major functional units in a processor

Datapath
4
Introduction
We will examine two RISC-V implementations
A simplified version (this week)
A more realistic pipelined version (next week)
We are reducing the instruction set …

Simple subset, shows most aspects of the system
Memory reference: ld, sd
Arithmetic/logical: add, sub, and, or
Control transfer: beq
5
Instruction Execution
PC → instruction memory, fetch instruction
Register numbers → register file, read registers
Use ALU to calculate

Arithmetic result
Memory address for load/store
Branch comparison
Access data memory for load/store
PC ← target address or PC + 4
6
Datapath Overview
7
Composing the Elements
The single-cycle data path does an instruction in one clock cycle
Each datapath element can only do one function at a time
Hence, we need separate instruction and data memories
Use multiplexers where alternate data sources are used for different
instructions
8
Multiplexers
 Can’t just join
wires together
 Use multiplexers
9
Breaking Down Instructions
Next, we’ll look at individual steps
Instruction fetch and PC update

Register fetch
Computation
Writeback
10
Instruction Fetch
Increment by
4 for next
64-bit instruction
register
11
R-Format Instructions
Read two register operands
Perform arithmetic/logical operation
Write register result
12
Load/Store Instructions
Read register operands
Calculate address using 12-bit offset
Use ALU, but sign-extend offset
Load: Read memory and update register
Store: Write register value to memory
13
Branch Instructions
1. Read register operands
2. Compare operands
1. Use ALU, subtract and check Zero output
3. Calculate target address
1. Sign-extend displacement
2. Shift left 1 place (halfword displacement)
3. Add to PC value
14
Branch Instructions
Just
re-routes
wires
Sign-bit wire
replicated
15
R-Type/Load/Store Datapath
16
Full Datapath
17
Activity time!
We’re going to try to analyze the datapath to better

understand how it works.
5 minutes: Exercise 4.7 in the text
5 minutes
18
Latencies and clock period
19
Full Datapath to Annotate
20
Processor Control and
the Processor as State Machine
21
Control
22
ALU Control
ALU used for
Load/Store: F = add
Branch: F = subtract
R-type: F depends on opcode
ALU control Function

0000 AND
0001 OR
0010 add
0110 subtract
23
ALU Control
Assume 2-bit ALUOp derived from opcode
Combinational logic derives ALU control
ALU
opcode ALUOp Operation Opcode field ALU function control
ld 00 load register XXXXXXXXXXX add 0010
sd 00 store register XXXXXXXXXXX add 0010
beq 01 branch on equal XXXXXXXXXXX subtract 0110
R-type 10 add 100000 add 0010

subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
24
The Main Control Unit
Control signals derived from instruction
25
Datapath With Control
26
R-Type Instruction
27
Load Instruction
28
BEQ Instruction
29
Performance Issues
1. Longest delay determines clock period
1. Critical path: load instruction
2. Instruction memory → register file → ALU → data
memory → register file
2. Not feasible to vary period for different instructions
3. Violates design principle
1. Making the common case fast
4. We will improve performance by pipelining
30
Demonstration
 Let’s go to RIPES!
1. Demonstrate how an instruction is executed
on an implementation of a classical von
Neumann machine.
2. System Simulation: Instruction Execution on

a Single-Cycle Processor
31
Activity time!
We’re going to try to enumerate control signals to

better understand how the control path works.
5 minutes: Exercise 4.5 in the text
5 minutes
32
Tasks
33
Extra Exercises
34
Let’s do this together!
35
Coming Up
36
Don’t Forget!
• Submit READY? Quizzes before next classes

• Participate in Peer discussion and Q/A every week
• Submit Quiz 4 before deadline (Mar. 10)
• Check your labs schedule… (we are starting Verilog with
the Lab K this week)
37
Don’t Forget!
• Submit Homework2 next week (based on week 5,6,7,8)
• Practice problems and part of Homework2:

(also mentioned at eClass course webpage)
• #?: AppA.1, A.4, A.5, A.7, A.11*, A.15, A.18*
• #?: 4.1, 4.2, 4.3, 4.5*
38
In the next week …
Inside the Processor
• More on Processor Organization

• Introduction to Pipelining
39
See you next
week!
40

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CSC 258

Explain the organization of a classical, von Neumann style processor

Describe the major functional units in a processor

We are reducing the instruction set …

Register numbers → register file, read registers

Use ALU to calculate

Instruction fetch and PC update

We’re going to try to analyze the datapath to better

5 minutes: Exercise 4.7 in the text

ALU control Function

R-type 10 add 100000 add 0010

2. System Simulation: Instruction Execution on

We’re going to try to enumerate control signals to

5 minutes: Exercise 4.5 in the text

• Submit READY? Quizzes before next classes

• Submit Homework2 next week (based on week 5,6,7,8)

• Practice problems and part of Homework2:

Inside the Processor

• More on Processor Organization

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