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Tutorial 3 2022 Students

1. The document contains a microprocessor tutorial for an engineering course. It includes multiple choice questions about 8086 microprocessor concepts as well as longer questions about peripherals and memory decoding. 2. In section B, students are asked to define assembler directives, explain the operation of common string and arithmetic instructions, and discuss features of the 8086 architecture like the BIU and EU. 3. Two questions involve designing memory decoder circuits using gates or decoders to map different memory regions to EPROM or EEPROM chips for an 8086 system. The start and end addresses and control signals must be indicated.

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Indongo Eliaser
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84 views5 pages

Tutorial 3 2022 Students

1. The document contains a microprocessor tutorial for an engineering course. It includes multiple choice questions about 8086 microprocessor concepts as well as longer questions about peripherals and memory decoding. 2. In section B, students are asked to define assembler directives, explain the operation of common string and arithmetic instructions, and discuss features of the 8086 architecture like the BIU and EU. 3. Two questions involve designing memory decoder circuits using gates or decoders to map different memory regions to EPROM or EEPROM chips for an 8086 system. The start and end addresses and control signals must be indicated.

Uploaded by

Indongo Eliaser
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIVERSITY OF NAMIBIA

SCHOOL OF ENGINEERING AND THE BUIT ENVIRONMENT


MICROPROCESSOR SYSTEMS TUTORIAL 3 – 29/03/2022
SECTION A:

1. In 8086 microprocessor one of the following statements is not true.


A) Coprocessor is interfaced in MAX mode B) Coprocessor is interfaced in MIN mode
C) I/O can be interfaced in MAX / MIN mode D) supports pipelining.
2. Direction flag is used with
A) String instructions. B) Stack instructions. C) Arithmetic instructions. D) Branch instructions.

3. Which of the following is the fastest memory element?


A) Cache B) primary C) secondary D) processor

4. The IP is ________ bits in length


A) 8 bits B) 4 bits C) 16 bits D) 32 bits

5. Example of Immediate addressing mode…


A) MOV AX, 2000H. B) MOV AX, BX. C) MOV AX, [2000H]. D) none

6. BHE of 8086 microprocessor signal is used to interface the


A) Even bank memory. B) Odd bank memory. C) I/O. D) DMA

7. In 8086 the overflow flag is set when


A) The sum is more than 16 bits. B) Signed numbers go out of their range after an arithmetic
operation. C) Both. D) none

8. Example of register addressing mode…


A) MOV AX, 2000H B) MOV AX, BX. C) MOV AX, [2000H] D) none

9. What will be the contents of r AL after the following has been executed
MOV BL, 8C
MOV AL, 7E
UNIVERSITY OF NAMIBIA
SCHOOL OF ENGINEERING AND THE BUIT ENVIRONMENT
MICROPROCESSOR SYSTEMS TUTORIAL 3 – 29/03/2022
ADD AL, BL
(A) 0A and carry flag is set (B) 0A and carry flag is reset
(C) 6A and carry flag is set (D) 6A and carry flag is reset

10. The size of instruction queue in 8086 is…


A) 4-byte long B) 5-byte long. C) 6-byte long D) 2-byte long

11. The total number of registers in 8086 is…….


A) 13 B) 10 C) 12 D) 14

12. The sizes of all registers in 8086 are ….


A) 32-bit B) 4-bit C) 8-bit D) 16-bit

13. In 16-bit to 8-bit division operation, the quotient and remainder store at…
A) AH-AL B) AL-AH C) AX-DX D) DX-AX

14. In 32-bit to 16-bit division operation, the quotient and remainder store at…
A) AH-AL B) AL-AH C) AX-DX D) DX-AX
26. Instructions IN and OUT are related to ….
A) AX B) BX C) CX D) all

15. The basic operation done in the instruction TEST is…..


A) OR B) AND C) XOR D) SUB

16. The basic operation done in the instruction CMP is…..


A) OR B) AND C) XOR D) SUB

17. Decrement CX is happened automatically in …….


A) LOOP B) REP C) TEST D) both A and B
UNIVERSITY OF NAMIBIA
SCHOOL OF ENGINEERING AND THE BUIT ENVIRONMENT
MICROPROCESSOR SYSTEMS TUTORIAL 3 – 29/03/2022

18. The instruction PUSH BX indicates…


A) Decrement SP by 2 B) Decrement SP by 2
C) Decrement SP by 1 D) Decrement SP by 1

19. The instruction MOV [BX+SI], BP belongs to …..Addressing mode


A) Base B) base-index
C) base-index with displacement D) index

20. The instruction ADD AX,[1234H] belongs to …..Addressing mode


A) Base. B) base-index. C) Register. D) direct

21. The instruction ADD AX, [SI]; belongs to …..Addressing mode


A) Base B) base-index
C) Index D) register in-direct

22. The instruction MOV AX,[BP+1]belongs to …..Addressing mode


A) Base-relative B) base-index. C) Index D) direct

23. The index registers are used to hold _______


A) Memory register B) offset address C) segment memory D) offset memory

24. Status register is also called as ___________


A) Accumulator B) Stack C) Counter D) flags
UNIVERSITY OF NAMIBIA
SCHOOL OF ENGINEERING AND THE BUIT ENVIRONMENT
MICROPROCESSOR SYSTEMS TUTORIAL 3 – 29/03/2022
SECTION B:
Question 1.
(a) Define what an assembler directive is. [2 marks]
(b) Explain how the following instructions operate:
MOVSB, LODSB, STOSB, SCASW, CMPSW. [10 marks]

{Your answer should give the default segments of operation, pointers used, operation done to achieve
the function etc. PS: Don’t just write, for example, it moves data and you end there. }

(c) Explain the function of the following: ORG, EVEN, ENDS and EQU in relation to 8086
programming. [4 marks]

(d) Explain the use of BIU and EU in the 8086 architecture. [6 marks]

Q2 (a) Explain the control word of 8255PPI and differentiate between the two command words.
[6 marks]
(b) The circuit connection of an 8255 chip is shown below with dedicated address lines
connected to a six input NAND gate and A0 and A1 connected to the A0 and A1 input
pin of the 8255 PPI chip. Find the address of Port B in the 8255 PPI shown below.
[6 marks]

P.T.O ---------------------------------------
UNIVERSITY OF NAMIBIA
SCHOOL OF ENGINEERING AND THE BUIT ENVIRONMENT
MICROPROCESSOR SYSTEMS TUTORIAL 3 – 29/03/2022
QUESTION 3
Design a decoder circuit to map the lowest section of memory space to four 32K x 8 EPROM chips
for an 8086 microprocessor system.

(i) Use NAND gates and inverters only for the decoder circuit. Indicate the start and end addresses
for each EPROM chip. Use RD and IO/M control signals of the microprocessor to access
memory.
(ii) Use the 74LS138 decoder
(iii) Indicate the start and end addresses for each EPROM chip

QUESTION 4
Design a decoder circuit to map the upper quarter (1/4) of the memory space to 64K x 8 EEPROM
chips for an 8086 microprocessor system.
(i) Use NAND gates and inverters only for the decoder circuit.
(ii) Determine the required number of chips
(iii) Indicate the start and end addresses for each EEPROM chip.
(iv) Use 74LS138 decoder
Use RD, WR, and IO/M control signals of the microprocessor to access memory.

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