Analysis of Power Distribution Network

in TSV-based 3D-IC

Kiyeong Kim, Woojin Lee, Jaemin Kim, Taigon Hyungdong Lee, Yongkee Kwon, and Kunwoo Park
Song, Joohee Kim, Jun So Pak, and Joungho Kim Advanced Design Team
Department of Electrical Engineering Hynix Semiconductor Inc.
KAIST, Icheon-si, Kyoungki-do, Korea
Daejeon, South Korea [email protected]
[email protected]; [email protected]

Abstract ² To reduce simultaneous switching noise (SSN) in a properties, a segmentation method was used to combine models
PDN design of TSV-based GPU system, the impedance properties of the on-chip PDN [1], a power/ground (P/G) TSV [2], and a
of the hierarchical PDN in the TSV-based GPU system were coplanar P/G line in a BS-RDL [3]-[5] which together form the
estimated and analyzed. The system consisted of triple-stacked hierarchical PDN. A segmentation method is a matrix-
TSV-based DRAMs on top of the GPU connected by TSVs, a calculation method for the impedance estimation of a total
silicon interposer, and a backside re-distribution layer (BS-RDL). structure using the impedance data of the individual sub-
A segmentation-based impedance-estimation method was used structures [1]
for the estimation of the total PDN impedance combining models
of the on-chip PDN, the power/ground (P/G) TSV, and the
coplanar P/G line in the BS-RDL. The impedance properties of
the PDN were also analyzed with respect to variations in the
number of P/G TSVs and P/G lines in the BS-RDL and variation
of the capacitance of the on-chip decoupling capacitor embedded
in the on-chip PDN.

Keywords ± Hierarchical power distribution network (PDN);

P/G TSV; coplanar P/G line; segmentation method; on-chip
decoupling capacitor.

I. INTRODUCTION
In recent years, the realization of high-speed integrated-
circuit systems with higher-bandwidths, smaller form factors,
and better electrical performance has been a continual
challenge. To this end, Through Silicon Via (TSV)-based
three-dimensional integrated circuits (3D-IC) have become the
major solution because TSV technology greatly reduces the
interconnection lengths between vertically stacked ICs. In
addition, a silicon interposer and a backside re-distribution
layer (BS-RDL) have been presented as additional areas for
both vertical and horizontal interconnection between ICs. High-
Figure 1. Cross-sectional view of the TSV-based GPU system with the
speed digital 3D-IC applications have been designed and stacked DRAMs, a GPU, a silicon interposer, and a BS-RDL. The on-
implemented using these technologies. chip PDNs in the DRAM, GPU, and silicon interposer are connected by
P/G TSVs and coplanar P/G lines in the BS-RDL.
As these technologies have been developed and applied in
3D-IC, power distribution networks (PDN) in 3D-IC have been In this paper, we estimated and analyzed the impedance
more complicated and hierarchically distributed. To reduce properties of the hierarchical PDN of the TSV-based GPU
simultaneous switching noise (SSN) in a PDN design, the system shown in Fig. 1 a representative TSV-based 3D-IC in
impedance of the PDN is estimated and analyzed to determine the frequency domain of 0.1 GHz to 30 GHz, using a
which electrical components of the PDN affect the total PDN segmentation-based impedance-estimation method. We also
impedance. Conventional method to estimate PDN impedance analyzed the impedance properties of the PDN with respect to
is using the 3D EM solver. However, it is not suited for the 3D variations in the number of P/G TSVs and P/G lines in the BS-
EM solver to estimate the impedance properties of the RDL and variation of the capacitance of the on-chip decoupling
hierarchical PDN in 3D-IC due to the memory problem and capacitor embedded in the on-chip PDN.
long simulation time [1]. Therefore, to estimate the impedance

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 II. IMPEDANCE-ESTIMATION METHOD FOR A III. ESTIMATION AND ANALYSIS OF THE IMPEDANCE CURVE
HIERARCHICAL PDN IN A TSV-BASED GPU SYSTEM OF THE HIERARCHICAL PDN IN A TSV-BASED GPU SYSTEM
The structure of the TSV-based GPU system is shown in In the TSV-based GPU system, because the I/O driver
Fig. 1. Here, three DRAMs are vertically stacked on top of the circuits operate at a double data rate (DDR), more SSN can be
GPU employing TSVs and a silicon interposer and a BS-RDL generated within the PDN, as it supplies power to the I/O driver
are used for interconnection between the stacked DRAMs and circuits. Therefore, in this study, we concentrate on the
the GPU. In the TSV-based GPU system, the PDN is impedance estimation of the PDN supporting the I/O driver
hierarchically organized into the on-chip PDN, the P/G TSVs, circuits.
and the coplanar P/G lines in the BS-RDL. The sizes of the on-
chip PDNs supporting the I/O driver circuits in the DRAM, Using the impedance-estimation method described above,
GPU, and silicon interposer are 4mm × 1mm, 10mm × 1mm, we estimated the impedance properties of the hierarchical PDN
and 4mm × 2mm, respectively. Also, these on-chip PDNs are in the GPU system in the frequency domain from 0.1 GHz to
vertically connected by P/G TSVs and coplanar P/G lines in the 30 GHz.
BS-RDL

Figure 2. On-chip PDN and constitutive unit-cell model. The on-chip

PDN is modeled by connecting the internal ports of the unit-cell models
using the segmentation method.

To estimate the impedance of the hierarchical PDN, a

segmentation-based impedance-estimation method was used,
connecting the internal ports of the models of on-chip PDNs, (a)
P/G TSVs, and coplanar P/G lines in the BS-RDL. The models
of the decomposed PDN substructures used in the impedance-
estimation method are described in the following:
First, the on-chip PDN is modeled using periodic unit-cell
models. If the distance between metal power lines and metal
ground lines fixed, the entire on-chip PDN consists of certain
repeated PDN structures: here, the unit cell illustrated in Fig. 2.
The on-chip PDN is modeled by connecting every port of a
unit-cell with the face-to-face ports of adjacent unit-cell models
using the segmentation method [1]. In this step, the impedance
profiles of the unit-cell model with one port on each side are
extracted from the 3D EM solver. Second, a P/G TSV pair,
including a P/G bump pair, is modeled using a simplified RLC
model based on the RLGC TSV model [2]. Third, a coplanar
P/G line in the BS-RDL is modeled by a series of simple RLC
transmission-line models. Assuming a lossless transmission
line, the inductance of the coplanar P/G line is derived from the
air-filled capacitance of the line [3], [4]. Also, the capacitance (b)
of the line is calculated based on the Veyers-Fouad Hanna Figure 3. PDN impedance curves of the TSV-based GPU system; (a)
approximation [5]. Finally, the resistance of the line calculated observed at the each floor PDN in the stacked DRAMs; (b) observed at
from Eq. (1): the PDN in the GPU. In (a), The PDN impedance on an upper-floor
DRAM is higher than that on the lower-floor DRAM from 3 GHz to 30
GHz due to greater PDN loop inductance and TSV inductance.

The impedance curves observed at each floor PDN in the

(1) stacked DRAMs and the PDN in the GPU are shown in Figs. 3-
, where L is the length of the coplanar P/G line, Wpwr/gnd is the (a) and (b), respectively.
width of the P/G line, and T is the thickness of the P/G line.

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 The impedance in regions I, II, III, IV, and V are dominated caused by the parallel connection of the lines. We again
by the electrical components of the PDN marked in each region, observed that as their numbers were increased, the impedance
in Fig. 3. Also, in region V, mode-resonance peaks and their level in region IV was reduced because of the reduction in
mode numbers are shown in Table I. PDN loop inductance and the inductance of the P/G TSV in Fig.
TABLE I. Mode Number of Mode-Resonance Peaks

It was observed that the PDN impedance on an upper-floor

DRAM in the stacked DRAMs is higher than that on the lower-
floor DRAM in the frequency range of 3 GHz to 30 GHz, as
shown in Fig. 3-(a), because the PDN on the upper-floor
DRAM sees greater PDN loop inductance and TSV inductance
due to its position. As the evidence, the inductance values of (a)
the third stacked DRAM, second stacked DRAM, and first
stacked DRAM in region IV are 43.3pH, 29.7pH, and 24.6pH,
respectively. The inductance and resistance of the coplanar P/G
line in the BS-RDL were very high compared to that of the
other PDN substructures. As a result, except for region I, it was
found that the PDN in the stacked DRAMs and the PDN in
GPU did not affect each other in Fig. 3 due to the virtual-open
state caused by the high inductance of the P/G line.
Here, the target impedance levels of the DRAMs and GPU,
which are 0.21 , respectively, were determined with the
simultaneous current consumption in substructures, a 10%
power supply tolerance, and a 50% switching activity. This
target impedance has to be satisfied by the system over a broad
range of frequencies, from dc to at least first harmonic of the
operating frequency of DRAMs and GPU [6]. A greater
capacitance is required in the on-chip PDN to meet the target
impedance levels in region I. On-chip decoupling capacitors
can be embedded in the on-chip PDN to provide this additional (b)
capacitance. Also, in region II, the resistance and inductance of Case 1 : Power TSV (12ea.) and Ground (14ea.)
BS-RDL must be reduced to meet the target impedance; Power line (12ea.) and Ground line (14ea.) in BS-RDL
Case 2 : Power TSV (24ea.) and Ground TSV (26ea.)
increasing the number of the P/G lines in the BS-RDL is one Power line (24ea.) and Ground line (26ea.) in BS-RDL
solution. Case 3 : Power TSV (48ea.) and Ground TSV (50ea.)
Power line (48ea.) and Ground line (50ea.) in BS-RDL
* All cases apply the number variation to a region of the same size.
IV. ANALYSIS OF IMPEDANCE PROPERTIES WITH VARIAION
IN THE NUMBER OF P/G TSVS AND P/G LINES IN THE BS-RDL Figure 4. PDN impedance curves of the TSV-based GPU system; (a)
observed at the PDN in the third stacked DRAM; (b) observed at the PDN
AND WITH VARIATION IN THE CAPACITANCE OF THE ON-CHIP in the GPU, when the number of P/G TSVs and P/G lines in the BS-RDL
DECOUPLING CAPACTIOR were changed. As their numbers were increased, the impedance levels in
region II and IV were reduced due to the reduction in the inductance and
A. Analysis of Impedance Properties with Variation in the resistance of the P/G lines in the BS-RDL and the reduction in PDN loop
Number of P/G TSVs and Coplanar P/G Lines in the BS-RDL inductance and in the inductance of the P/G TSV, respectively.
The impedance curves observed at the PDN in the third
4-(a). As the evidence, the inductance values in case I, case II,
stacked DRAM and the PDN in GPU are shown in Figs. 4-(a)
and case III are 43.3pH, 37.3pH, and 30.5pH, respectively.
and (b), respectively, when the number of P/G TSVs and the
Therefore, increasing the number of P/G lines in the BS-RDL
P/G lines in the BS-RDL were changed. As their numbers were
helps to meet the target impedance of the third stacked DRAM
increased, it was found that the impedance level in region II
and GPU in region II. However, increasing the number of P/G
was reduced due to the reduction in the inductance and
TSVs does not help to meet the target impedance of the third
resistance of the P/G lines in the BS-RDL. This reduction is

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 stacked DRAM and GPU, because the frequency range affected increased, the impedance level representing the capacitance of
by the TSVs is higher than that of their target impedance. on-chip PDN and on-chip decoupling capacitor was lowered in
regions I and III due to the increase in capacitance in Fig. 5.
B. Analysis of Impedance Properties with Variation of the Also, as the fraction was increased, the PDN loop inductance
Capacitance of the On-Chip Decoupling Capacitor was lowered in region IV due to the increase in the number of
The impedance curves observed for the PDN in the third the PDN loop. In addition, it is observed that the PDN mode
stacked DRAM and the PDN in the GPU are shown in Figs. 5- resonance peaks and the anti-resonance peaks caused by the
(a) and (b), respectively, when the ratio of the PDN area in inductance of TSV in region IV almost disappear due to the
which the on-chip decoupling capacitors are embedded to the variation of the Q factor caused by the ESR of on-chip
area of the whole PDN was changed. The on-chip decoupling decoupling capacitor. Therefore, increasing the total
capacitor can be modeled by including the series connection of capacitance of on-chip decoupling capacitor helps to lower the
Cdecap and ESR [7] in the unit-cell model of the on-chip PDN. PDN impedance in regions I, III, and IV in Fig. 5.
In this study, for the variation of the fraction of the PDN area in It was observed that the impedance of the third stacked
which on-chip decoupling capacitors are embedded by the 5%, DRAM met the target impedance, when the on-chip decoupling
10%, and 15% of the whole PDN area, we changed the number capacitors in all cases are used. However, the impedance of the
of the on-chip decoupling capacitor connected to the unit-cell
GPU did not meet the target impedance in regions II and III
model. As a result, the total capacitances of on-chip decoupling with the same condition due to the high inductances of the P/G
capacitor used in the GPU system were 15.3nF, 30.6nF, and lines in the BS-RDL and the GPU PDN. To meet the target
45.9nF, respectively. It is evident that, as this fraction was impedance, the number of P/G lines in the BS-RDL must be
increased and the size of the GPU on-chip PDN should be
minimized to lower the inductance of the GPU PDN.

V. CONCLUSIONS
Using a segmentation-based impedance-estimation method,
we estimated and analyzed the impedance properties in the
hierarchical PDN in a TSV-based GPU system in the frequency
range of 0.1 GHz to 30 GHz. The effects on the PDN
impedance curves of variations in the number of P/G TSVs and
P/G lines in the BS-RDL and variation of the capacitance of the
decoupling capacitor were also analyzed. The results indicated
that increasing the on-chip decoupling capacitance can make to
meet the target impedance of the third stacked DRAM.
However, to meet the target impedance of the GPU, increasing
the number of P/G lines in the BS-RDL and minimizing the
size of the GPU PDN are also required.

(a)
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