Sequential Digital Systems: The Synthesis

Pinit Kumhom

vLSI Design for embedded Systems with intelligence (vDeSi) Lab

Department of Electronic and Telecommunication Engineering
Faculty of Engineering

King Mongkut’s University of Technology Thonburi

September 16, 2016

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 1 / 14
Outline

1 What are expected to be learnt?

2 FSM Synthesis Process

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 2 / 14
What are expected to be learnt after this learning session?
Be able to answer the following questions or describe the following terms from own
understanding.

Be able to describe the FSM synthesis process.

Be able to perform all technical steps of FSM synthesis process
given its specification.

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 3 / 14
FSM Specification: A FSM can be specified by describing its state transitions
and outputs at all of its states.
This can be in many forms such as state diagram, state/output table, ASM (Algorithmic
State Machine) Chart, HDL (Hardware Description Language)

State Diagram State/Output Table

AB
S 00 01 11 10 Z
INIT A0 A0 A1 A1 0
A0 OK0 OK0 A1 A1 0
A1 A0 A0 OK1 OK1 0
OK0 OK0 OK0 OK1 A1 1
OK1 A0 OK0 OK1 OK1 1

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 4 / 14
Steps for synthesizing a digital circuit of an FSM given its state diagram or
state/output table.

1. If the FSM is specified using the state diagram, construct the

corresponding state table of the FSM.
2. (Optional) Reduce the number of states if possible.
3. Choose how to represent the state by the the following steps.
3.1 Choose a state encoding technique,
3.2 Find the number of memory devices based on the chosen state
encoding technique. Let n be the number of memory. Then, denote
the state signal as q = qn−1 qn−2 · · · q0 , where n is the number of
memory devices (number of bits of q).
4. Construct state transition/output table from the state table (Step 1 and 2)
and state representation (Step 3).
5. Choose type of memory device (either it is D-FF or JK-FF or T-FF). This
implies the excitation table of a memory device.
6. Construct excitation tables for all memeory devices using state transition/
output table (Step 4) and the excitation table of a memory device (Step 5).
7. Synthesis the next-state logic using the excitation tables from Step 6 as
specifications, and synthesize the output logic using the output table
from Step 4 as specifications.

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 5 / 14
Illustration of FSM Synthesis Process
Step 1: Given a state diagram, construct the corresponding state/output table.

State Diagram State/Output Table

AB
S 00 01 11 10 Z
INIT A0 A0 A1 A1 0
A0 OK0 OK0 A1 A1 0
A1 A0 A0 OK1 OK1 0
OK0 OK0 OK0 OK1 A1 1
OK1 A0 OK0 OK1 OK1 1

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 6 / 14
Illustration of FSM Synthesis Process
Step 3: Choose how to represent the state (state encoding)
Assumming there are N states after the state reduction.
State Choose whether it is one-hot, almost one-hot or multiple-hots?
For one-hot state encoding,
▶ use 1 memory device to reprsent 1 state ⇒ N memory devices for N
states
▶ arrange the N memory devices in sequence
▶ the code 00 · · · 1 · · · 00, where 1 (the hot position) is at the i bit,
represents the state i.
For almost one-hot state encoding,
▶ Use the all zero code to represent the initial state.
▶ The remaining N − 1 states are encoded as one-hot encoding.
For multi-hot encoding, the choices are as follows:
▶ binary code
▶ minimal-change code (gray code)
▶ designer’s decomposed code
▶ random code(usually done by a synthesis tool)
and the number of memory devices n = ⌈log2 N⌉

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 7 / 14
Illustration of FSM Synthesis Process
Step 3: Choose how to represent the state (state encoding)

State Name State Code (Representation)

For multi-hot encoding, S Binary Decomposed One-hot Almost one-hot
▶ There are 5 states ⇒ q2 q1 q0 q2 q1 q0 q4 q3 q2 q1 q0 q3 q2 q1 q0
INIT 000 000 00001 0000
need 3 memory devices. A0 001 100 00010 0001
▶ Let q = q q q be the
2 1 0 A1 010 101 00100 0010
state variable (signal). OK0 011 110 01000 0100
OK1 100 111 10000 1000
For one-hot encoding,
▶ There are 5 states ⇒ For almost one-hot encoding,
need 5 memory devices. ▶ There are 5 states ⇒ need 4
▶ Let q = q q q q q be
4 3 2 1 0 memory devices.
the state variable ▶ Let q = q3 q2 q1 q0 be the state
(signal). variable (signal).
▶ The initial state is the state
INIT
Choose the decomposed code.

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 8 / 14
Illustration of FSM Synthesis Process
Step 4: Construct state transition from the state table by replacing all each state name
with its corresponding code.

Present State Next State Output

State Name State Variable Input(AB)
S q = q2 q1 q0 00 01 11 10 Z
INIT 000 100 100 101 101 0
A0 100 110 110 101 101 0
A1 101 100 100 111 111 0
OK0 110 110 110 111 101 1
OK1 111 100 110 111 111 1
q′ = q′2 q′1 q′0

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 9 / 14
Illustration of FSM Synthesis Process
Step 5: Choose type of memory device
Step 6: Construct excitation table
Choose JK Flip-Flop State Transition Table unused state specification
PS Input(AB)
PS Input(AB)
JK flip-flop’s Excitation q2 q1 q0 00 01 11 10
q2 q1 q0 00 01 11 10 001 −−− −−− −−− −−−
Change Excitation
q → q′ J K 000 100 100 101 101 010 −−− −−− −−− −−−
011 −−− −−− −−− −−−
0→0 0 − 100 110 110 101 101
q′2 q′1 q′0
0→1 1 − 101 100 100 111 111
1→0 − 1
110 110 110 111 101
1→1 − 0
111 100 110 111 111
q′2 q′1 q′0

Q0 Transition (q0 → q′0 ) J0,K0 Excitation

Input(AB) Input(AB)
q2 q1 q0 00 01 11 10
q2 q1 q0 00 01 11 10
000 0→0 0→0 0→1 0→1
000 0,− 0,− 1,− 1,−
100 0→0 0→0 0→1 0→1
100 0,− 0,− 1,− 1,−
101 1→0 1→0 1→1 1→1
110 0→0 0→0 0→1 0→1 101 −,1 −,1 −,0 −,0
111 1→0 1→0 1→1 1→1 110 0,− 0,− 1,− 1,−
111 −,1 −,1 −,0 −,0
J0,K0

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 10 / 14
Illustration of FSM Synthesis Process
Step 7: Synthesize the next-state logic using the excitation table from Step 6.

J0,K0 Excitation J0 in Karnaugh Map for q2 = ’0’ J0 in Karnaugh Map for q2 = ’1’
Input(AB)
PS Input(AB) PS Input(AB)
q2 q1 q0 00 01 11 10
q1 q0 00 01 11 10 q1 q0 00 01 11 10
000 0,− 0,− 1,− 1,−
100 0,− 0,− 1,− 1,− 00 0 0 1 1 00 0 0 1 1
101 −,1 −,1 −,0 −,0 01 − − − − 01 − − − −
110 0,− 0,− 1,− 1,− 11 − − − − 11 − − − −
111 −,1 −,1 −,0 −,0
10 − − − − 10 0 0 1 1
J0,K0

K0 in Karnaugh Map for q2 = ’0’ K0 in Karnaugh Map for q2 = ’1’

J0 = A PS Input(AB) PS Input(AB)
q1 q0 00 01 11 10 q1 q0 00 01 11 10
K0 = Ā
00 − − − − 00 − − − −
01 − − − − 01 1 1 0 0
11 − − − − 11 1 1 0 0
10 − − − − 10 − − − −

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 11 / 14
Illustration of FSM Synthesis Process
Step 5: Choose type of memory device
Step 6: Construct excitation table

Choose D Flip-Flop State Transition Table unused state specification

PS Input(AB)
PS Input(AB)
D flip-flop’s Excitation q2 q1 q0 00 01 11 10
q2 q1 q0 00 01 11 10 001 −−− −−− −−− −−−
Change Excitation
000 100 100 101 101 010 −−− −−− −−− −−−
q → q′ D
011 −−− −−− −−− −−−
0→0 0 100 110 110 101 101
q′2 q′1 q′0
0→1 0 101 100 100 111 111
1→0 1 110 110 110 111 101
1→1 1 111 100 110 111 111
D= q′
q′2 q′1 q′0

Q0 Transition (q0 → q′0 ) d0 Excitation

Input(AB)
Input(AB)
q2 q1 q0 00 01 11 10
000 0→0 0→0 0→1 0→1 q2 q1 q0 00 01 11 10
100 0→0 0→0 0→1 0→1 000 0 0 1 1
101 1→0 1→0 1→1 1→1 100 0 0 1 1
110 0→0 0→0 0→1 0→1
101 0 0 1 1
111 1→0 1→0 1→1 1→1
110 0 0 1 1
111 0 0 1 1
d0

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 12 / 14
Illustration of FSM Synthesis Process
Step 7: Synthesize the next-state logic using the excitation table from Step 6.

State Transition Table d0 in Karnaugh Map for q2 = ’0’ d0 in Karnaugh Map for q2 = ’1’
PS Input(AB)
PS Input(AB) PS Input(AB)
q2 q1 q0 00 01 11 10
000 100 100 101 101
q1 q0 00 01 11 10 q1 q0 00 01 11 10
100 110 110 101 101 00 0 0 1 1 00 0 0 1 1
101 100 100 111 111 01 − − − − 01 0 0 1 1
110 110 110 111 101
11 − − − − 11 0 0 1 1
111 100 110 111 111
10 − − − − 10 0 0 1 1
q′2 q′1 q′0

d1 in Karnaugh Map for q2 = ’0’ d1 in Karnaugh Map for q2 = ’1’

d0 = A PS Input(AB) PS Input(AB)
q1 q0 00 01 11 10 q1 q0 00 01 11 10
d1 =
00 0 0 0 0 00 1 1 0 0
01 − − − − 01 0 0 1 1
11 − − − − 11 0 1 1 1
10 − − − − 10 1 1 1 0

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 13 / 14
Illustration of FSM Synthesis Process
Step 7: Synthesize the next-state logic using the excitation table from Step 6.

State Transition Table d2 in Karnaugh Map for q2 = ’0’ d2 in Karnaugh Map for q2 = ’1’
PS Input(AB)
PS Input(AB) PS Input(AB)
q2 q1 q0 00 01 11 10
000 100 100 101 101
q1 q0 00 01 11 10 q1 q0 00 01 11 10
100 110 110 101 101 00 1 1 1 1 00 1 1 1 1
101 100 100 111 111 01 − − − − 01 1 1 1 1
110 110 110 111 101
11 − − − − 11 1 1 1 1
111 100 110 111 111
10 − − − − 10 1 1 1 1
q′2 q′1 q′0

Pinit Kumhom (vDeSi Lab, KMUTT) Sequential System Synthesis September 16, 2016 14 / 14