EC 1601 – Microprocessors and Microcontrollers Department of CSE 2022-2023

UNIT II 8086 SYSTEM BUS STRUCTURE

1. 8086 signals – Basic configuration:

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip. Let
us now discuss in detail the pin configuration of a 8086 Microprocessor.

Power supply and frequency signals: It uses 5V DC supply at VCC pin 40, and uses ground at
VSS pin 1 and 20 for its operation.
Clock signal: Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
Address/data bus: AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order
byte data and AD8AD15 carries higher order byte data. During the first clock cycle, it carries
16-bit address and after that it carries 16-bit data.
Address/status bus: A16-A19/S3-S6. These are the 4 address/status buses. During the first
clock cycle, it carries 4-bit address and later it carries status signals.
BHE: BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer
of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is
active.
Read{RD}: It is available at pin 32 and is used to read signal for Read operation.
Ready: It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready to
transfer data. When it is low, it indicates wait state.
RESET: It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles
to RESET the microprocessor.

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INTR: It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt or
not.
NMI: It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered
input, which causes an interrupt request to the microprocessor.
TEST: This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.
MN{MX}: It stands for Minimum/Maximum and is available at pin 33. It indicates what mode
the processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.
INTA: It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.
ALE: It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a valid
address on the address/data lines.
DEN: It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data from the address/data bus.
DT/R: It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out and
vice-a-versa.
M/IO: This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at pin
28.
WR: It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.
HLDA: It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
HOLD: This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
QS1 and QS0: These are queue status signals and are available at pin 24 and 25. These signals
provide the status of instruction queue. Their conditions are shown in the following table −

QS0 QS1 Status

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty the queue

1 1 Subsequent byte from the queue

S0, S1, S2: These are the status signals that provide the status of operation, which is used by the
Bus Controller 8288 to generate memory & I/O control signals. These are available at pin 26,
27, and 28. Following is the table showing their status:

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S2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

LOCK: When this signal is active, it indicates to the other processors not to ask the CPU to
leave the system bus. It is activated using the LOCK prefix on any instruction and is available at
pin 29.
RQ/GT1 and RQ/GT0: These are the Request/Grant signals used by the other processors
requesting the CPU to release the system bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

2. System bus timing –System design using 8086

(a) System Bus timings: Minimum mode 8086 system and timings
In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX* pin to logic1. In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single microprocessor in the minimum mode system. The
remaining components in the system are latches, transreceivers, clock generator, memory and I/O
devices.
The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in
two parts, the first is the timing diagram for read cycle and the second is the timing diagram for
write cycle.
Fig shows the read cycle timing diagram. The read cycle begins in T1 with the assertion of the
address latch enable (ALE) signal and also M/IO* signal. During the negative going edge of this
signal, the valid address is latched on the local bus. The BHE* and A0 signals address low, high
or both bytes. From Tl to T4, the M/IO* signal indicates a memory or I/O operation. At T2 the
address is removed from the local bus and is sent to the output. The bus is then tristated. The read
(RD*) control signal is also activated in T2 .The read (RD) signal causes the addressed device to
enable its data bus drivers. After RD* goes low, the valid data is available on the data bus. The
addressed device will drive the READY line high, when the processor returns the read signal to
high level, the addressed device will again tristate its bus drivers.

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Table: Read write cycle:

A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO*
signal is again asserted to indicate a memory or I/O operation. In T2 after sending the address in
Tl the processor sends the data to be written to the addressed location. The data remains on the
bus until middle of T4 state. The WR* becomes active at the beginning ofT2 (unlike RD* is
somewhat delayed in T2 to provide time for floating). The BHE* and A0 signals are used to
select the proper byte or bytes of memory or I/O word to be read or written. The M/IO*, RD*
and WR* signals indicate the types of data transfer as specified in above Table,

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(b) System Bus timings: Maximum mode 8086 system and timings
In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this
mode, the processor derives the status signals S2*, S1* and S0*. Another chip called bus
controller derives the control signals using this status information. In the maximum mode, there
may be more than one microprocessor in the system configuration.
Pin Definitions (24 to 31) in Maximum Mode:
 QS1, QS0 (output): These two output signals reflect the status of the instruction queue.
This status indicates the activity in the queue during the previous clock cycle.

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 S2,S1,S0 (output) : These three status signals indicate the type of transfer to be take
place during the current bus cycle.

 LOCK : This signal indicates that an instruction with a LOCK prefix is being executed
and the bus is not to be used by another processor:
 RQ/GT1 and RQ/GT0 : In the Maximum Mode Configuration of 8086, HOLD and
HLDA pins are replaced by RQ (Bus request)/GT0 (Bus Grant), and RQ/GT1 signals. By
using bus request signal another master, can request for the system bus and processor
communicate that the request is granted to the requesting master by using bus grantnal.
Both signals are similar except the RQ/GT0 has higher priority than RQ/GT1.
Figure shows the typical Maximum Mode Configuration of 8086. In the maximum mode
additional circuitry is required to translate the control signals. The additional circuitry converts
the status signals (S2-S0) into the I/O and memory transfer signals. It also generates the control
signals required to direct the data flow and for controlling 8282 latches and 8286 transceivers.
The Intel 8288 bus controller is used to implement this control circuitry.
The basic functions of the bus controller chip IC8288, is to derive control signals like RD* and
WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the information made
available by the processor on the status lines. The bus controller chip has input lines S2*, S1*
and S0* and CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE,
DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN*, IOB and CEN
pins are especially useful for multiprocessor systems. AEN* and IOB are generally grounded.
CEN pin is usually tied to +5V.

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Figure shows that the 8288 bus controller is able to originate the address latch enable signal to
the 8282’s, the enable and direction signals to the 8286 transceivers, and the interrupt
acknowledge signal to the interrupt controller. It also decodes the S2-S0 signals to generate
MRDC, MWTC, IORC, IOWC, MCE/PDEN, AEN, IOB, CEN, AIOWC, and AMWC signals.

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 MRDC (Memory Read Command) : It instructs the memory to put the contents of the
addressed location on the data bus.
 MWTC (Memory Write Command) : It instructs the memory to accept the data on the
data bus and load the data into the addressed memory location.
 IORC (I/O Read Command) : It instructs an I/O device to put the data contained in the
addressed port on the data bus.
 IOWC (I/0 Write Command) : It instructs an I/O device to accept the data on the data
bus and load the data into the addressed port.
 MCE/PDEN (Master Cascade Enable/Peripheral Data Enable) : It controls the mode
of operation of 8259. It selects cascade operation for 8259 (interrupt controller) if IOB
signal is grounded and enables the I/O bus transceivers if IOB is tied high.
 AEN, IOB and CEN : These pins are used in multiprocessor system. With a single
processor in the system, AEN and IOB are grounded and CEN is tied high. AEN causes
the 8288 to enable the memory control signals. IOB (I/O bus mode) signal selects either
the I/O bus mode or system bus mode operation. CEN (control enable) input enables the
command output pins on the 8288.
 AIOWC/AMWC (Advance I/O Write Command/Advance Memory Write
Command) : These signals are similar to IOWC and MWTC except that they are
activated one clock pulse earlier. This gives slow interfaces an extra clock cycle to
prepare to input the data.
Bus Timing Diagram of 8086:
The Bus Timing Diagram of 8086 of input and output transfers are shown in the Figure (a) and
(b) respectively.

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These are explained in steps.

 S0,S1,S2 are set at the beginning of bus cycle. On detecting the change on
passive state S0 = S1 = S2 = 1, the 8288 bus controller will output a pulse on its ALE and
apply a required signal to its DT/R pin during T 1.
 In T2, 8288 will set DEN = 1 thus enabling transceiver. For an input, 8288 it will activates
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T 3 to T4.
 The status bits S0 to S2 remain active until T3, and become passive during T3 and T4.
 If ready input is not activated before T3, wait state will be inserted between T3 and T4.

3. I/O programming :
The 8086 External Hardware Synchronization Instructions are namely

HLT Instruction : HLT instruction will cause the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The only ways to get the processor out of the halt
state are with an interrupt signal on the INTR pin, an interrupt signal on the NMI pin, or a reset
signal on the RESET input.

WAIT Instruction : When this instruction executes, the 8086 enters an idle condition where it is
doing no processing. The 8086 will stay in this idle state until a signal is asserted on the 8086
TEST input pin, or until a valid interrupt signal is received on the INTR or the NMI interrupt
input pins. If a valid interrupt occurs while the 8086 is in this idle state, the 8086 will return to
the idle state after the execution of interrupt service procedure. WAIT affects, no flags. The
WAIT, instruction is used to synchronize the 8086 with 8086 External Hardware
Synchronization Instructions such as the 8087 math coprocessor.

ESC Instruction : This instruction is used to pass instructions to a coprocessor such as the 8087
math coprocessor which shares the address and data bus with an 8086. Instructions for the
coprocessor are represented by a 6-bit code embedded in the escape instruction. When the 8086
fetches an ESC instruction, the coprocessor decodes the instruction and carries out the action
specified by the 6-bit code specified in the instruction. In most cases the 8086 treats the ESC

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instruction as a NOP. In some cases the 8086 will access a data item in memory for the
coprocessor.

LOCK Instruction : In a multiprocessor system each microprocessor has its own local’ buses
and memory. The individual microprocessors are connected together by a system bus so that each
can access system resources such as disk drives, or, memory. Each microprocessor only takes
control of the system bus when it needs to access some system resources. The LOCK prefix
allows a microprocessor to make sure that another processor does not take control of the
system bus while it is in the middle of a critical instruction which uses the system bus. The
LOCK prefix is put in front of the critical instruction. When an instruction with a LOCK prefix
executes, the 8086 will assert its bus lock signal output. This signal is connected to an 8086
External Hardware Synchronization Instructions bus controller device which then prevents any
other processor from taking over the system bus. LOCK affects no flags.

NOP Instruction :At the time of execution of NOP instruction, no operation is performed except
fetch and decode. It takes three clock cycles to execute the instruction. NOP instruction does not
affect any flag. This instruction is used to fill in time delays or to delete and insert instructions in
the program while trouble shooting.
Input Output Interface

In addition to memory, a computer system must also provide interfaces with other external
devices, such as display unit, keyboard etc. All these external devices are regarded as
Input/Output devices (usually we simply use the term I/O). In general, memory can also be
considered as some kinds of I/O from the CPU’s point of view.

The I/O (Input/Output) interface permits the microprocessor to communicate with the outside
world. How can you connect a keyboard, or a mouse, to an 8086 microprocessor?
In the 8086 microprocessor, I/O devices are connected via the address and data buses and the
mechanism is similar to the memory interface. Data transfer takes place over the multiplexed
address/data bus.

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The above figure shows how the I/O devices are connected to the system. As you can see the
major difference between connection to a memory and connecting to I/O devices is the signal
level of M/IO. When accessing memory devices M/IO is ‘1’. While M/IO is ‘0’ when accessing
I/O devices.
Similar to memory devices, as there are many I/O devices connected to the buses therefore,
decoding is also required for I/O system.

The 8086 minimum mode I/O interface

Interface circuitry, as depicted in Figure, is used to bridge the microprocessor and the I/O
(Input/Output) devices. Functions of the interface are to select the I/O port, latch output data,
adjust the signal levels etc. Only address/data lines from 0-15 are used (but for memory devices
address lines A0 to A19 are used.) In addition, the I/O interface circuit is also similar to the
memory decoder.

I/O address space: Unlike the 89C51, or the ADuC832, there are no I/O ports available in the
8086. All I/O devices are connected to the address bus and data bus. However, we still use the
term I/O port to describe the connection between the 8086 and an I/O device. Since only address
lines A0 to A15 are used by I/O devices so a total of 64K devices can be connected to the system.
Imagine there are virtual I/O ports then the ports are numbered from 0 to 64K-1. Similar to
memory devices, byte is the basic unit for data transfer so if an I/O device transfers 16-bit data
then it will occupy 2 ports. So I/O ports could be 8-bit or 16-bit.
I/O port number (16-bit) are generated by microprocessor via the ADn lines and after proper
decoding, correct I/O port can be selected. AD16 to AD19 are held at 0 for I/O operations.

Software for accessing I/O ports: When accessing memory, we use move (MOV) operations.
When accessing I/O port, we use IN and OUT. There are two forms of IN OUT instructions:
direct and indirect.
In Direct instruction, we can address 256 ports (8-bit) only. The format of IN OUT is:

IN - input from port into AL or AX

OUT - Output from AL or AX to port
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IN AL, a-8-bit-value representing the port number,

Ex. IN AL, #FFH (move a byte in from port FF)
OUT an-8-bit-value representing the port number, AL ,
Ex. OUT #FFH, AL (move a byte out from AL)
The 8-bit value is used to represent a port, since it is 8-bit so only Port 0 to Port 255 can be
manipulated.
For accessing Port greater than 255 then Indirect addressing is used. And the format is
IN AL, DX
Where DX is 16-bit and stores the port number.
Indirect addressing can access 64K ports (WHY?)
Example:
MOV DX, #1234H
MOV AL, #12h
OUT DX, AL ; SEND THE VALUE 12H TO PORT 1234H

Program example

Data are to be read in from two byte-wide input ports at port AA and A9, respectively, and
then output as a word to a word-wide output port at port B000. The data comes from Port AA
is the high byte. Write a sequence of instructions to perform these I/O operations.

IN AL, AA
MOV AH,AL
IN AL,A9 ; now the data becomes 16-bit and stored in AX
MOV DX, B000
OUT DX, AX ; can I do OUT B000, AX instead ??????

Since the port number B000 is larger then 8-bit so indirect is used.

I/O bus cycle

Accessing I/O devices are very similar to accessing memory therefore, to read/write data to or
from an I/O device, a proper cycle is performed. A read cycle for I/O also takes 4 cycles and the
signals are very similar to the memory read cycle except the M/IO signal.

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Input cycle

Timing for an output cycle (write)

Hardware configuration for Output devices

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Figure: Input/output decoding

The device 8282, as shown in the above diagram, is only a latch for storing data. The 8205
(similar to a 3x8 multiplexer) is used as a decoder. When the 8086 issues a Port Number via its
address bus, the number is decoded so that a proper I/O device can be selected. In the circuit, the
decoder output is used to control the STB (Strobe) of the 8282. Since the circuit only supports
output therefore, the signal /WR is also used as part of a control for the STB.
Are you able to determine the Port addresses represented by the 8282.

Example
Refer to the Figure 7.8, to which port are data written when the address put on the bus during an
output bus cycle is 8002(Hex)
Write a series of instructions that will output the byte contents of the memory location called
DATA to output Port 0 as shown in Figure 7.8.

Answer
The input select (ABC) for the 8205 is driven by A1 A2 and A3, refer to the diagram
For the address 8002H, the 3 bits are 001 (2Hex)

So Port 1 is selected

The control required to select the Port 0 is

8000H (refer to above, Port 1 is 8002)
The instruction is
Mov DX, 8000H
Mov AL, DATA
Out DX, AL ; using indirect

8255A Programmable Peripheral Interface (PPI)

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As you can see in Figure 7.8, in order to connect to an I/O device, a buffer, or latch is required. If
your system is connected to many I/O devices then a lot of latches are required. Usually, a
computer system makes use of some ICs instead of standard latches to interface with the I/O
devices and the 8255A is the most common interface used in a computer system.

The 8255A is an LSI peripheral designed to permit easy implementation of parallel I/O in the PC
systems. It provides a flexible parallel interface, such as input and output ports; level-sensitive
inputs; latched outputs; strobed inputs or outputs; and strobed bidirectional input/outputs. These
features are selected under software control. 8255 can interface any TTL-compatible I/O device
to the microprocessor. You can obtain a full description of the 8255 by downloading its data
sheet, or the document PIO_8255.doc in the ftp site.

Usually the 8255 is used to interface with a keyboard and parallel printer port in the past but now
most of the interfaces are based on USB. However, the 8255 is still applied in interfacing with
non-standard devices. For example, if you want to use a PC to control a motor etc.
The block diagram of the 8255 is shown below.

4. Introduction to Multiprogramming - System Bus Structure

Multiprogramming: A programming unit that performs an independent task is called a
process, job or a task. The system which executes the process one after the another is called
uni-programming system.
Multiprogramming is the technique of running several processes at a time using timesharing.
It allows a computer to do several things at the same time. Multiprogramming creates
parallelism. Multiprogramming significantly improves the system performance by
overlapping I/O operation and CPU operation.

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Multiprocessing is the concurrent processing of instructions by more than one processors.

Multiprocessing is a general term that can mean the dynamic assignment of a program to one
of two or more processors working in tandem.

Multiprocessor Configuration: The speed of any system depends upon the clock frequency
at which it is operating. A single processor system has an upper limit on its processing
capability. When several microprocessors are connected in a system, speed of operation can
be improved.
A system that includes 2 or more components can execute instructions simultaneously and is
called a multiprocessing system. The processor added can be special purpose processor or
General purpose processors.
Eg: (i) Numeric data processor that quickly operates on floating point numbers and numbers
having larger width.(8087-NDP)
I/O processor that performs string manipulations, code conversion, Character searching and
bit testing. (8089-IOP)
I/O Devices: Most of I/O operations are sluggish due to low operating speed of I/O devices.
Thus, in order to avoid main processor wasting its time carrying out I/O activities, the I/O
processor (IOP) takes care of the I/O activities.
Coprocessor: NDP & IOP work in tune with main processor to complete specific tasks.
(i) They are not able to work independently.
(ii) They are not able to fetch code
from memory. (iii)So, they work
under the control
of main processor.
Additional hardware elements like bus controllers, bus arbiters are used to
coordinate activities of the multiprocessors working at a time in the system.
Multiprocessing features are provided in Maximum mode to provide 3 basic
configurations
(i) Coprocessor configuration
(ii) Closely coupled configuration
(iii) Loosely coupled configuration
Processors used in multi microprocessor systems are either Coprocessor or
independent processors.

Coprocessor Independent Processor

It executes instructions fetched for it by the It asks for a bus access, itself fetches the
host processor instructions & executes them independently.

Difference between closely coupled and loosely coupled configurations:

Closely coupled or Tightly coupled Loosely coupled configuation

configuration

1. The microprocessors (either 1. Each CPU may have its own bus
coprocessor or independent processor) control logic.

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share a common clock and bus control 2. More numbers of CPU’s (8086) can be
logic
. added.
2. The two processors in this system 3. Bus arbitration is handled by an
communicates using
common system external circuit, common to all
bus or common memory processors.
3. A coprocessor is always interconnected 4. Eg: LAN, WAN
with host CPU (8086) in this
configuration
4. Eg: Small computing system.

8086 based Multiprocessing System: Coprocessor or closely coupled

configuration using 8087 NDP:
Although 8086 is a powerful single chip microprocessor, their instruction set is not
sufficient to perform complex applications. For example, 8086 has no instructions for
performing floating point arithmetic, but by using INTEL 8087 NDP as a coprocessor,
floating point calculations can be done.
Flowchart describing communication between CPU & NDP:

Detailed Block Diagram:

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Working Operation:
(i) Both CPU (8086) & Coprocessor executes their instructions from the same
program.
(ii) CPU fetches instructions from memory
(iii) 8087 uses QS0 & QS1 pins to identify and obtain the instructions fetched by host
CPU (8086)
(iv) Host CPU identifies coprocessor instructions using ESCAPE code bits in them.
(v) Once CPU recognizes the ESCAPE code, it triggers execution of NDP instruction
in 8087.
(vi) While executing, ESCAPE code finds out the coprocessor instruction which
requires memory operands and those which does not require memory operands.
(vii) If instructions requires memory operand to be fetched from memory, the 20 bit
physical address of the operand is calculated, the 8087(NDP) reads it & proceeds
for execution.
(viii) If instruction does not require any operand, then the instruction is directly executed.
(ix) When 8087 is ready with execution results, it gets control of the bus from 8086,
executes a write cycle to write the results in memory at the prespecified address.
(x) When 8087 (NDP) begins execution, it pulls up BUSY signal.
The BUSY signal of 8087 is connected to TEST pin of 8086. If BUSY signal is high,
CPU recognizes that the instruction is not yet complete. So 8086 wait till the BUSY pin
of 8087 (i.e) TEST input of 8086 goes low or till coprocessor executes the instruction
completely.

I/O Processor:
A practical microprocessor system has a number of peripheral devices connected
with it. All such peripherals can be interfaced with the CPU. However maintenance of
these peripheral devices consumes considerable CPU time, thereby reducing throughput
in terms of speed.
An IOP takes care of all the system I/O activities. Once initiated by host CPU,
 The IOP receives request from the systems peripherals,
 It issues commands to the system peripherals
 It keeps track of the operations of the peripherals.
 The IOP establishes communication with the host, using its interrupt service.
Flowchart describing communication between CPU & IOP:

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 8089 communicates with the host processors using a memory table.

 The memory table contains details of task to be executed.
 These tables are prepared by host CPU to allot a task to IOP.
 Host CPU interrupts IOP after allotting a task to it.
 Once it is interrupted, IOP reads memory tables prepared by host CPU to
get details of the allotted task.
 This memory table has an address of a program, written in 8089
instructions called as channel program.
 The 8089 executes channel program
 8089 can fetch and executes its instructions on its own, unlike 8087.
 When 8089 completes the task, it interrupts the CPU or maintains a busy
flag in memory table, and this flag is periodically checked by host
CPU(8086)
 8089 can be in tightly or loosely coupled configuration

5. Multiprocessor configurations – Coprocessor, Closely coupled and

loosely Coupled configurations
In order to adapt to as many situations as possible both the 8086 and 8088 have been given two
modes of operation, the minimum mode and the maximum mode. The minimum mode is used
for a small system with a single processor, a system in which the 8086/8088 generates all the
necessary bus control signals directly (thereby minimizing the required bus control logic). The
maximum mode is for medium-size to large systems, which often include two or more
processors.
Multiprocessor means a multiple set of processors that executes instructions simultaneously.
There are three basic multiprocessor configurations.

 Coprocessor configuration
 Closely coupled configuration
 Loosely coupled configuration

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Coprocessor Configuration:

A Coprocessor is a specially designed circuit on microprocessor chip which can perform the
same task very quickly, which the microprocessor performs. It reduces the work load of the
main processor. The coprocessor shares the same memory, IO system, bus, control logic and
clock generator. The coprocessor handles specialized tasks like mathematical calculations,
graphical display on screen, etc.
The 8086 and 8088 can perform most of the operations but their instruction set is not able to
perform complex mathematical operations, so in these cases the microprocessor requires the
math coprocessor like Intel 8087 math coprocessor, which can easily perform these operations
very quickly.

Block Diagram of Coprocessor Configuration:

Coprocessor and the processor connection:

 The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 &
QS1 signals.
 The TEST signal is connected to BUSY pin of coprocessor and the remaining 3 pins are
connected to the coprocessor’s 3 pins of the same name.
 TEST signal takes care of the coprocessor’s activity, i.e. the coprocessor is busy or idle.
 The RT-/GT-is used for bus arbitration.
 The coprocessor uses QS0 & QS1 to track the status of the queue of the host processor.

Closely Coupled Configuration:

Closely coupled configuration is similar to the coprocessor configuration, i.e. both share the
same memory, I/O system bus, control logic, and control generator with the host processor.
However, the coprocessor and the host processor fetches and executes their own instructions.
The system bus is controlled by the coprocessor and the host processor independently.

Block Diagram of Closely Coupled Configuration:

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Processor and the independent processor connection:

 Communication between the host and the independent processor is done through memory
space.
 None of the instructions are used for communication, like WAIT, ESC, etc.
 The host processor manages the memory and wakes up the independent processor by
sending commands to one of its ports.
 Then the independent processor accesses the memory to execute the task.
 After completion of the task, it sends an acknowledgement to the host processor by using
the status signal or an interrupt request.

Loosely Coupled Configuration:

Loosely coupled configuration consists of the number of modules of the microprocessor based
systems, which are connected through a common system bus. Each module consists of their own
clock generator, memory, I/O devices and are connected through a local bus.

Block Diagram of Loosely Coupled Configuration

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Advantages:

 Having more than one processor results in increased efficiency.

 Each of the processors have their own local bus to access the local memory/I/O devices.
This makes it easy to achieve parallel processing.
 The system structure is flexible, i.e. the failure of one module doesn’t affect the whole
system failure; faulty module can be replaced later.

6. Introduction to advanced processors.

In loosely coupled configuration, 8089 has its own local bus & communicates with host CPU
using bus arbiter & bus controller. It has shared system bus, system memory, and system I/O.
Each processor has its own clock as well as its own memory.

Used for medium to large multiprocessor systems

Each module is capable of being the bus master

Any module could be a processor capable of being a bus master, a coprocessor
configuration or a closely coupled configuration.
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
No direct connections between the modules. Each share the system bus and
communicate through shared resources.

Processor in their separate modules can simultaneously access their private subsystems
through their local busses, and perform their local data references and instruction
fetches independently. This results in improved degree of concurrent processing.
Excellent for real time applications, as separate modules can be assigned specialized
tasks.

Advantages:

 High system throughput can be achieved by having more than one CPU.
 The system can be expanded in modular form. Each bus master module is an
independant unit and normally resides on a separate PC board. One can be added or
removed without affecting the others in the system.
 A failure in one module normally does not affect the breakdown of the entire system
and the faulty module can be easily detected and replaced
 each bus master has its own local bus to access dedicated memory or IO devices so a
greater degree of parallel processing can be achieved.

Disadvantages:

 Bus Arbitration (contention): Process of accessing system bus by more than one
processor is called bus contention. Make sure that only 1 processor can access the bus at
any given time.
 Must synchronize local and system clocks for synchronous data transfer
 Requires control chips to tie into the system bus

Bus arbitration and Control:

 In order to enhance processing speed of a single processor system, shared bus

multiprocessor configuration was introduced.
 In order to further enhance processing speed or power, the number of microprocessors
sharing bus may be increased.
 But, this gives rise to bus contention and interprocessor communication problems.
 To resolve these problems, (i) bus allotment and control, (ii) bus arbitration and (iii)
priority resolving methods are introduced.

Bus arbiter IC (8289):

 It is used for arbitration of the shared system bus

 CPU is given capability to request for bus access, it recognizes the bus allotted to it and
also to other processors in the system
 This arbiter takes care of all bus access control functions & bus handshake activities.
 It operates with bus controller (8288)
 This arbiter controls access of the bus for its host CPU & maintains status about current
access of the bus.
 Bus access is given to its master or host CPU using the following bus
arbitration(allocation) schemes for resolving the contention problem.
Daisy chaining method
Polling method
Independent request method
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BUS ALLOCATION SCHEMES:

 Need a bus controller to monitor bus busy and bus request signals
 Sends a bus grant to a Master >> each Master either keeps the service or passes it on
 Controller synchronizes the clocks
 Master releases the Bus Busy signal when finished

Polling method:

 Controller sends address of device to grant bus access

 Can use priority resolution. Memory is given highest priority
 Highest priority is granted first, if it does not respond, then a lower priority is granted,
and so on until someone accepts


Independent Request method:

 Each master has a request and grant line

 Could have fixed priority, rotating priority, etc. usually fixed because memory is desired
to be the highest priority
 Synchronization of the clocks must be performed once a Master is recognized
 Master will receive a common clock from one side and pass it to the controller which
will derive a clock for transfer
 Can accurately predict calculations (since memory is always the highest priority).

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Introduction to advanced processors:

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