PD Assignments

SSTA

Week - 1

1. Define Timing Paths and What are the Different Timing paths?

2. Explain in detail abt the need of each inputs of synthesis

3. Cant we Constrain our design without the help of .lib? Explain

4. What do you mean by constraining a design ?

5. Explain about Setup and Hold Requirements with respect to transmission gates.

6. What do you mean by the wire load model? why do we consider ZWLM while

Synthesis?

Week – 2

1. How is net-delay Calculate?

2. What is Wire Load Model?

3. Why in Synthesis we consider Zero Wire Load Model.

4. write down pros and cons of STA and DTA

5. Write Down the all the Commands related to defining clock.

6. How do you define maximum frequency of a clock

Week – 3

1. What are the steps you take to fix Setup slack?

2. What is Logic Synthesis

3. What is Physical Synthesis

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 4. what are the tools for logic synthesis?

5. If two clocks are defined in a design what should be the relation between those two

clocks

Week – 4

1. List down all SDC Commands

2. List Report_timing Command Switches and their output

3. List down all the Commands Related to the Clock

4. What is the output of report transitive fanin

5. What are Input delay and output delay, Explain the reason behind deciding the values

for them.

Week – 5

1. What are Sanity checks?

2. What is the check “check_design” does?

3. What are the Default and non-default checks that “check_design” does?

4. What are all the Cell Informations that “.lib” provides?

5. For The given circuit shown below is having the following delays. Wherever the bus
has been defined it’s a register bank. Calculate the following only for reg2reg paths :
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Assume the jitter of the clock for Flops is 1ns and calculate the following:
Worst setup slack for Flops
Worst hold slack for Flops
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Max operating clock Freq
Assume the max/min insertion delays of the clock for Flops is 7/9ns.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Assume the derating factors of the clock has 21 % for setup and 18 % for hold.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Assume the derating factors of the clock has 16 % for setup and 10 % for hold. CPPR
for these designs is 2ns consider all the above factors of jitter, insertion delays and
derating factors.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Consider the above cell delays as pre-extraction cells and after route at the post
extraction we are seeing a difference of 3ns. Including the factors of jitter, insertion
delays and derating factors.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Frequency

If the clock period has been changed to 30ns what would be the effect?
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
If the MCP have been defined has two clock cycles what would be the effect?
Worst setup slack for Flops

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 Worst hold slack for Flops
Max operating clock Freq
All the clocks Clk1, Clk2, Clk3 and Clk4 are generating from the same PLL. Clock to O
delay is 2.5ns, clock to O* is 3.5ns, And gate 1.5ns Or gate 2ns Mux inputs 3.5ns and
selection line delays is at 5ns. Setup and hold time of Flops F1 , F2 and F3 are 4ns, F4
is 6ns.

6. The circuit shown below has two clk 1 (4 ns clock period) and clk2 (4ns clock period)
which are generated from two PLL. Jitter effect of PLL is having 1ns and 0.8ns for two
clocks. Can you tell us the effects of setup, hold?

Week – 6

1. what is clock Uncertainty?

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2. What are the Effects of Jitter in Timing

3. Different Types of Clock Jitter

4. For The given circuit shown below is having the following delays. Wherever the bus

has been defined it’s a register bank.

Calculate the following only for reg2reg paths :

Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Assume the jitter of the clock for Flops is 1ns and calculate the following:
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Assume the max/min insertion delays of the clock for Flops is 7/9ns.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Assume the derating factors of the clock has 21 % for setup and 18 % for hold.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Assume the derating factors of the clock has 16 % for setup and 10 % for hold. CPPR
for these designs is 2ns consider all the above factors of jitter, insertion delays and
derating factors.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
Consider the above cell delays as pre extraction cells and after route at the post
extraction we are seeing a difference of 3ns. Including the factors of jitter, insertion
delays and derating factors.
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Frequency

If the clock period has been changed to 30ns what would be the effect?
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 Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
If the MCP have been defined has two clock cycles what would be the effect?
Worst setup slack for Flops
Worst hold slack for Flops
Max operating clock Freq
The circuit shown in Figure below And Gate has arc timings as follows input high to
output rise has 2ns, input low to output high has 2.5ns. The inverter arc timing as
follows input high to output low has 1.5ns and input low to output high has 2ns.
Clock to Q delays 3ns.

Week – 7

1. what is Skew and types of skew?

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2. How do you decide the min pulse width of a clock?

3. Difference Between OCV, POCV and AOCV

4. For The given circuit shown below is having folthe lowing delays. Wherever the bus

has been defined it’s a register bank.

Calculate the following only for reg2reg paths:

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Assume the jitter of the clock for Flops is 1ns and calculate the following:

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Assume the max/min insertion delays of the clock for Flops is 7/9ns.

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Assume the derating factors of the clock has 21 % for setup and 18 % for hold.

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Assume the derating factors of the clock has 16 % for setup and 10 % for hold. CPPR for

these designs is 2ns consider all the above factors of jitter, insertion delays and derating
factors.

Worst setup slack for Flops

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Worst hold slack for Flops

Max operating clock Freq

Consider the above cell delays as pre-extraction cells and after route at the post
extraction we are seeing a difference of 3ns. Including the factors of jitter, insertion
delays and derating factors.

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Frequency

If the clock period has been changed to 30ns what would be the effect?

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

If the MCP have been defined has two clock cycles what would be the effect?

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

The circuit shown below in Figure 2 has following the nand gate delays has min / max
delay of 5/7ns. Input port and output port delays has 6 and 8ns.clk to Q delays are 9ns.

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Week -8

1. Advantages and disadvantages of Clock Gating

2. For The given circuit shown below is having the following delays. Wherever the bus
has been defined it’s a register bank.

Calculate the following only for reg2reg paths:

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Assume the jitter of the clock for Flops is 1ns and calculate the following:

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Assume the max/min insertion delays of the clock for Flops is 7/9ns.

Worst setup slack for Flops

Worst hold slack for Flops

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Max operating clock Freq

Assume the derating factors of the clock has 21 % for setup and 18 % for hold.

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Assume the derating factors of the clock has 16 % for setup and 10 % for hold. CPPR for

these designs is 2ns consider all the above factors of jitter, insertion delays and derating
factors.

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

Consider the above cell delays as pre extraction cells and after route at the post
extraction, we are seeing a difference of 3ns. Including the factors of jitter, insertion
delays and derating factors.

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Frequency

If the clock period has been changed to 30ns what would be the effect?

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

If the MCP have been defined has two clock cycles what would be the effect?

Worst setup slack for Flops

Worst hold slack for Flops

Max operating clock Freq

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The circuit shown below in Figure 3.a and Figure 3.b has following the nand gate delays
has min/max delay of 9/13ns, Inverter delays has 4/6ns. Input port and output port
delays has 6 and 8ns.clk to Q delays are 9ns.Clock to Q delays 9ns. Net delays of each
net is 2ns. Xtalk on nets is.2ns

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 PNR
Week - 1

1. Define Timing Paths and What are the Different Timing paths?
2. Draw the PD flow and explain each stage
3. Explain the input details of PD
4. Write the sanity check before PNR
5. What are the constraints inside the SDC files?
6. Explain about IO placement

Week – 2

1. How to decide chip core area

2. How to arrive at the value of utilization factor and aspect ratio during initial floorplan

3. How to decide pin or pad location

4. How is Floor planning done in hierarchical flow?

5. What are pad limit design and core limit design?

Week – 3

1. Explain in detail about pin guides

2. Explain about port DEF file

3. Explain the pin constraint file

4. Write ICC2 command for port placement, macro placement & power plan

5. Write the different types of modes in detail

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Week – 4

1. What is a Halo? How is it different from the blockages?

2. What is the minimum clearance around macro?

3. Explain well proximity effect. How to fix this problem?

4. Explain boundary cells and why boundary cells place before placement.

5. Explain floor planning from scratch to end.

Week – 5

1. Draw the internal circuit diagram and explain static and dynamic power

2. Write the power estimation guidelines

3. Explain how to create a power ring and mesh

4. Write an icc2 command for PG ring and mesh

5. Write the Goal of power routing

Week – 6

1. What are the things to be checked before going to the placement stage? explain.

2. What are the reasons for congestion in the design?

3. Explain 5 stages in place_opt. command

4. How to solve cell density issue.

5. Explain the global routing scenario

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Week – 7

1. Explain the causes for congestion issue in placement stage

2. How tool do congestion analysis in placement stage

3. How do you fix unoptimized nets and paths

4. Explain about timing analysis after placement

5. Explain about bounds

Week – 8

1. What are the SDC constraints associated with the clock tree? How tool do congestion

analysis in the placement stage

2. What are the goals of CTS?

3. How do congestion optimization and balance slew?

4. Explain in-place optimization and Timing Delay.

5. Explain about clock_opt stages

Week – 9

1. Explain the antenna effects and fixing technique

2. Explain different types of routing and its purpose

3. What are the reports we observed after routing QoR checks?

4. Explain the technique to fix violation after routing

5. Explain post route optimization and quality checks

Week – 10

1. What are the SDC constraints associated with clock tree

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 2. Which is better when compared to buffer and inverter.If so why

3. What type of buffers and Inverters are used at CTS Stage

4. How will you build a clock tree for gated clocks

5. How will you synthesize the clock tree

6. Explain the role of the skew group in building better clock tree

7. Why to reduce Clock skew

8. Why buffers are used in the clock tree

9. Which is more complicated when you have a 48 Mhz and 500 MHz Frequency

10.What kind of optimization is done in the CTO stage

11.How does jitter effects the setup and hold paths

12.How does set inter clock uncertainty

Week – 11

1. what is base tapeout?

2. what is LEC? what do you observe in LEC

3. what is ECO Flow? explain with a flow chart

4. Explain the objectives of physical verification.

5. Explain the different stages of LEC

Week – 12

1. Which metal layers are used for Routing and why?

2. What is an antenna rule check?

3. Why do we use reverse bias diode for antenna effect?

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 4. What are antenna violations in physical design?

5. What is pre-routing?

6. What is a routing track?

7. What is routing blockages?

8. What are the different types of routing?

9. What are routing resources?

10. What are Gcells?

Week -13

1. What are the principles in low power design?

2. Why is low power important?
3. How to fix a static IR drop?
4. How to fix EM?
5. What is a level shifter cell?
6. What is isolation in UPF?
7. What is a retention cell?
8. What are the low-power techniques?
9. Why is secondary pg necessary?
10.What is the difference between higher and lower node technologies?

Week – 14

1. How is spef generated?

2. At which stage physical only, cells will be placed

3. Which cells will be placed to overcome the latch-up problem?

4. Why do we need tie cells?

5. What is the difference between LEF and DEF?

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 6. What is the purpose of filler cells?

7. What are LEF files used for?

8. What is a GDS file?

9. What is a netlist file?

10.Where does end cap cells will be placed?

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PD Assignments

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 1. a) Why current density is more important than current in IC design.
b) What is technology node?
2. What is the condition for symmetric transfer characteristics and equal current-driving
capability in both directions (pull-up and pull-down).
3. write about multi cycle path.
4. write about false path
5. write about generated clock
6. Write about set_load.
7. Write about set_deriving_cell

1. Write set up and hold equations with diagrams for below topics.

1. positive edge trigger flip flop and negative edge triggered flip flop
2.positive edge trigger flip flop and positive edge triggered flip flop
3.negative edge trigger flip flop and negative edge triggered flip flop
4.negative edge trigger flip flop and positive edge triggered flip flop
5.in2reg path
6.reg2out path

1. What are look up tables.

2. Why there is difference in cell delay rise and fall transition.
3. What are DRV's and types.
4. What is the meaning of operating condition.
5. How cross talk, ocv, crpr, latency,skew,glitch effects the setup te and hold time
explain with a diagram
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 .

1. What are some common types of timing checks performed by Static Timing Analysis
tools?
2. How to define asynchronous clock in your tool (don't use set_false_path).
3. What are some of the best practices that should be followed when doing Static Timing
Analysis (synthesis)
4. How does STA help in reducing power consumption on digital chips?
5. What do you understand about path tracing in STA?
6. Write a TCL script to print

Lib_cell_name. Instance count

Ex:BUFFD1. 20

And cells which are not used in design should not be printed

7. Write a script to print below information

1.Start point 2.endpoint 3.Slack 4.No of logic levels in data path
Using get_timing_path
8. In ICC2 SHELL
Report attributes of metal layers
1.Layer name 2.Min width 3.pitch 4.min spacing 5. Min area 5. Routing direction

Using get_layers

1. If Std cell area = 800 µm2 & utilization = 0.7

Aspect ratio = 1, then what is the height and width
AR = 0.8
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 AR = 0.6
AR = 0.5
2. What is the difference between hard macro and soft macro
3. Review the synthesis flow

PNR
1. Explain PNR flow.
2. How to calculate the maximum clock frequency fmax or minimum time period Tmin
required for the given sequential circuit.
3. Explain is ocv
4. Why clock skew constraint-specific value?
5. What are the contents of .tf file?
6. what are the guidelines to place a macro
7. What is keep out margin and channel space? How much gave in your design?
8. What is the size of your block and macro size? How many macros and standard cells
are present in your design?
9. How many power stripes are placed in horizontal and vertical by using highest metal
layer? How many site rows are present in your design?
10. What is the area and power of your design? What are the different switches available
for set_pg_strategy?
11.Write about different stages in place_opt.
12.What are the sanity checks in placement stage.
13.What are the issues faced in power plan stage.
14.What are the issues faced in floor plan stage and how did you resolve that issues?
15.How many scenarios used in your design?
16.How much TNS and WNS in your design.

17.What is the utilization in each stage...if utilization increased more than 5% ,What is the

reasons behind that?

18.Why congestion occurs in your design, write all reasons and fixes.

19.write mmmc file script.

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20.write inputs and checks in each stage

21.How to fix setup and hold violations at a time

22.What is scan chain reordering?

23.What is the concept of rows in the floor plan

24.What are the advantages of NDR's?

25.In reg to reg path if you have setup problem where will you insert buffer.

26.What is usage of DEF file.

27.What is usage of spef file.

28.What type of nets present I spef file.

29.Explain report_congestion command

30.What is special net and its significance in DEF file.

31.which metal layers ports are present.

32.what are the steps for doing PT ECO stage.
33.Different between the flat and hierarchal design.
34.what is latch up explain timing concepts.
35.explain about upf file
36.what is the inputs for pt shell.

37.What is Setup? How you fix setup in pt shell.

38.write a script for fix Hold.

39.What are the commands using entire pd flow?

40.What is OCV , AOCV and POCV

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 LAB Questions
#check_pin_placement

#set_boundary_cell_rules

#create_boundary_cells

#compile_boundary_cells

#check_boundary_cells

#create_tap_cells

1.man create pin guide

2.man set_individual_ pin_constraints

3.man remove_pin_constraints

4.man set_block_pin_constraints

report_app option plan*macro

5. man plan.macro. macro_place_only

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 1. What are the inputs required for Pnr?
2. Explain Pnr Flow
3. What type of information is consist in the following libraries
a. .lib
b. .db
c. .tf
d. LEF
e. TLU+
f. .V
g. Def
4. Advantages of polysilicon?

1. Explain macro guidelines? Types of macro

2. Explain endcapcells (and decapcell)
3. Difference between keepout Margin and blockage ? Types of blockages
4. What are inputs required for PNR? PNR flow?
5. What is core, Die, Macro utilization? Write formula for macro channel spacing

1. What are the information contain in .lib file?

2. How to find top module from RTL file?
3. Explain following commands with example

a) Linl_library
b) Tanget_library
c) Analyze
d) Compile
e) Elaborate
f) Write file
4. Explain setup and hold using transmission gates
5. Difference between compile and compile ultra

1. What is synthesis? Types of synthesis explain in detail

2. Explain synthesis flow in detail
3. Explain clock gating
4. Explain DFT
5. Synthesis i/p and o/ps

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