This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2807384, IEEE
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A Novel Single-Input Dual-Output Three-

Level DC-DC Converter
Amir Ganjavi, Hoda Ghoreishy, and Ahmad Ale Ahmad

 high forward voltage drop and ON-state resistance. Moreover,

Abstract— This paper proposes a novel non-isolated the typical semiconductors used in high voltage applications are
single-input dual-output three-level dc-dc converter IGCT and high voltage IGBT [6], [7], which are not good
(SIDO-TLC) appropriate for medium and high voltage solutions for multiport dc-dc converters. Due to the very high
applications. The SIDO-TLC is an integration of the three-
level buck and boost converters, whose output voltages are
switching losses of those switches, their switching frequency is
regulated simultaneously. Reducing voltage stress across practically limited to about 1 KHz [6], [7]; therefore, the size of
semiconductor devices, improving efficiency, and reducing the passive components will increase dramatically. This study
inductors size are among the main merits of the new aimed at designing a high-efficiency multiport dc-dc converter
topology. Moreover, due to the considerably reduced with reduced voltage stress across semiconductor devices and
volume of the step-down filter capacitor, a small film shrunken passive components size.
capacitor can be used instead, whose advantages are lower
ESR and a longer lifespan. A closed-loop control system
Reference [8] proposes a bidirectional multiple-input
has been designed based on a small-signal model multiple-output dc-dc converter based on the triangular
derivation in order to regulate the output voltages along modular multilevel dc-dc converter. In this converter, the
with the capacitors’ voltage balancing. In order to verify the voltage stress on switches is shared amongst the levels. In
theoretical and simulation results, a 300 W prototype was addition to its complex control system, the converter is not
built and experimented. The results prove the afore- capable of generating buck and boost output voltages at the
mentioned advantages of the SIDO-TLC, and the high
effectiveness of the balancing control strategy.
same time. As a result, it requires two separate circuits with
Furthermore, the converter shows very good stability, even different topologies to generate each voltage separately. In [9],
under simultaneous step changes of the loads and input a non-isolated single-input dual-output dc-dc converter
voltage. (SIDOC) is proposed, which one of its outputs is boost and the
other one is buck at the same time. The converter’s topology is
Index Terms— Multiport converter, non-isolated dc-dc achieved through the substitution of two series-connected
converter, single-input dual-output dc-dc converter
switches with the control switch of the conventional boost
(SIDOC), single-input dual-output three-level dc-dc
converter (SIDO-TLC), three-level converter. converter. The voltage stress on each switch and the diode is
equal to the boost output voltage, making the converter
I. INTRODUCTION appropriate for low-voltage applications. Meanwhile, because
of high voltage stress on the diode and the series added
M ULTIPORT dc-dc converters have attracted a great deal
of research interest recently, which could be attributed to
the growing demand of renewable energy, the development of
switches, and also due to the lack of proper high input current
distribution (which is typically the case in the single-input
multiple-output converters) among the switches, the
power electronic systems, and the increasing use of microgrids.
converter’s both conduction and switching losses are high,
Compared to several separate dc-dc converters, multiport dc-dc
which can lead to a fairly low system efficiency. Reference [10]
converters suggest a compact structure with a lower cost and
proposes an isolated SIDOC, which comprises four diodes and
less component counts [1]–[5]. At higher voltages, switches
only one power switch. However, in order to increase the
voltage stress is a major challenge for multiport dc-dc
efficiency and cope with the high current stress, two paralleled
converters. The reason for that are the issues such as the cost
high-current switches with soft-switching method have been
and the inaccessibility of high voltage switches, which could
used in the experimental prototype. A number of studies have
also have a negative effect on overall efficiency due to their
been found proposing multiport multi-level converters
[11]–[13]. In [12], a non-isolated SIDOC is proposed, which is
Manuscript received September 14, 2017; revised December 12,
a combination of the sepic and five-level boost converters. The
2017 and January 11, 2018; accepted January 31, 2018. converter is composed of one switch and 10 diodes. The voltage
A. Ganjavi, H. Ghoreishy, and A. A. Ahmad are with the Department stress on the switch is reduced to one-fifth of the high voltage
of Electrical Engineering Faculty, Babol Noshirvani University of side. Yet, high number of diodes may affect the reliability of
Technology, Babol, Mazandaran, Iran (e-mail: [email protected],
[email protected], [email protected]). the system. Moreover, reducing the passive components size,

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which is one of the advantages of the multi-level structures, has L1 D11

not been achieved through the proposed converter.
This paper presents a newly designed, non-isolated single- iL1 iC11 io1
input dual-output three-level dc-dc converter (SIDO-TLC). S1
io2 L2 +
With an appropriate control strategy, the converter benefits
a C11 vC11
from both the three-level and multiport structures. Owing to its + iL2 S2 − +
three-level structure, the proposed converter has the advantages
of reduced voltage stress on switches and diodes, reduced vin vo2 C2 vo1
passive components size, and improved efficiency. This paper iC2 iC12
− S3
has been arranged as follows: the following section offers the + −
proposed converter and describes its operation principles and b C12 vC12
the related switching states. This section also analyzes the S4 −
steady-state operation. In section III, the closed-loop and
balancing control strategies are proposed, and the dynamic
characteristics of the SIDO-TLC are analyzed through the D12
obtained small-signal model. In section IV, the experimental Fig. 1. The proposed SIDO-TLC.
results are demonstrated to verify the converter’s behavior.
Finally, a summary is provided in section V. Case A, vo1
Case A, vo2
II. PRINCIPLE OF OPERATION 7 Case B, vo1 XXXX
Case B, vo2 XXXX

Step-Up & Step-Down

6
A. Switching States, Main Waveforms, and Operating Case C, vo1 ………….
………….

Cases
5 Case C, vo2 ………….
………….
4
Gains
Fig. 1 shows the circuit diagram of the proposed SIDO-TLC. 3
In this figure, vin is the input voltage, vo1 is the step-up output 2
voltage, and vo2 is the step-down output voltage. The series 1
capacitors C11 and C12 are the filter capacitors of the step-up 0
1
output, while C2 is the filter capacitor of the step-down output. 0.8 1
The converter is composed of four power switches: S1, S2, S3,
0.6 0.9
0.8
d2=(Y) 0.4
and S4, with anti-parallel diodes, and two power diodes: D11 and 0.2 0.6
0.7
d1=(X)
0 0.5
D12. Table I shows the switching states, the unfiltered step- Fig. 2. Operating range of the output voltage gains with variation of
down output voltage vab, the instantaneous voltages of inductors duty-cycles d1, and d2.
vL1 and vL2, the series capacitors’ currents iC11 and iC12, and also
limits in each case, the operating range of the SIDO-TLC is
the capacitors’ voltage change (magnitude and direction).
defined in Table II based on the steady-state evaluation.
As can be seen from Table I, several switching states can not
Accordingly, Fig. 2 illustrates the operating range of the
only generate the same output voltages, but also have the same
SIDO-TLC by showing the voltage gain surfaces with variation
charging states. In other words, they have identical equivalent
of duty-cycles d1 and d2. As it is seen in Fig. 2, although the
circuits. Furthermore, some other switching states generate the
proposed converter regulates two output voltages
same output voltages and just their charging states are different
independently and at the same time fulfill the task of a three-
((5, 6) & (7, 8); (9, 10) & (11, 12); 13 & 14). It appears that this
level control strategy, the converter spans a wide range of duty-
wide variety of redundancies can guarantee the precise
cycles. That is because all three possible cases in which the
balancing of the series capacitors, which will be discussed in
converter can regulate the output voltages along with its three-
next sections.
level control strategy are defined for the proposed converter.
Regarding the duty-cycles of the switches, there are three
Also, Fig. 3 shows the main waveforms of the SIDO-TLC as
possible operating cases named A, B, and C for the SIDO-TLC.
well as its switching states in each case. As depicted in Fig. 3,
In the ideal situation, the control signals of S1 and S4 have the
vab varies between 0 and Vo1/2 in the operating cases A and B,
same duty-cycles (dS1=dS4=d1) and are 180 degree phase-
while it varies between Vo1/2 and Vo1 in case C. Meanwhile,
shifted. In the same way, the control signals of S2 and S3 have
due to the utilized switching sequence in each case, the effective
the same duty-cycles (dS2=dS3=d2) and are 180 degree phase-
ripple frequencies of the inductors currents and vab are twice as
shifted. In order to achieve the afore-mentioned phase-shifts,
much as the switching frequency. This will help the designer to
two saw-tooth carriers with the same frequency and 180 phase-
reduce the passive components size without increasing the
shift are used in each operating case. Depending on d1 and d2
switching frequency.
values, the operating cases can be expressed as follows:
Case A: (1/2 < d1 & d2 < 1) & (d1 > d2). B. Static Gain
Case B: (1/2 < d1 & d2 < 1) & (d1 < d2). By applying inductors’ volt-second balance in one-second of
Case C: (d2+1/2 < d1 < 1) & (0 < d2 < 1/2). the switching period, both step-up and step-down gains can be
According to all possible duty-cycles and output voltage

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TABLE I
SWITCHING STATES FOR THE SIDO-TLC (ARROWS INDICATE MAGNITUDE AND DIRECTION- RO1 IS THE RESISTIVE LOAD AT THE STEP-UP TERMINAL)

Switching
S1 S2 S3 S4 vab vL1 vL2 iC11 iC12 C11 C12
state
1 0 0 0 0
2 0 0 1 0
0 vin−vo1 −vo2 iL1−vo1/Ro1 iL1−vo1/Ro1
3 0 1 0 0
4 0 1 1 0
5 0 0 1 1
0 vin−vo1/2 −vo2 iL1−vo1/Ro1 −vo1/Ro1
6 0 1 1 1
7 1 1 0 0
0 vin−vo1/2 −vo2 −vo1/Ro1 iL1−vo1/Ro1
8 1 1 1 0
9 0 0 0 1
vo1/2 vin−vo1 vo1/2−vo2 iL1−vo1/Ro1 iL1−iL2−vo1/Ro1
10 0 1 0 1
11 1 0 0 0
vo1/2 vin−vo1 vo1/2−vo2 iL1−iL2−vo1/Ro1 iL1−vo1/Ro1
12 1 0 1 0
13 1 0 1 1 vo1/2 vin−vo1/2 vo1/2−vo2 iL1−iL2−vo1/Ro1 −vo1/Ro1

14 1 1 0 1 vo1/2 vin−vo1/2 vo1/2−vo2 −vo1/Ro1 iL1−iL2−vo1/Ro1

15 1 0 0 1 vo1 vin−vo1 vo1−vo2 iL1−iL2−vo1/Ro1 iL1−iL2−vo1/Ro1

16 1 1 1 1 0 vin −vo2 −vo1/Ro1 −vo1/Ro1

d1 d2 0° 180°

TSW∕2 TSW 3TSW∕2 2TSW TSW∕2 TSW 3TSW∕2 2TSW TSW∕2 TSW 3TSW∕2 2TSW
1 1 1

0.5 0.5 0.5

0 0 0
S1 S1 S1

S2 S2 S2

S3 S3 S3

S4 S4 S4
(1−d1)TSW
iL1 iL1 iL1
(d2−1/2)TSW (d1−1/2)TSW (1− d2)TSW (d1− d2− 1/2)TSW

iL2 iL2 iL2

(d1− d2)TSW (d2−d1)TSW
(1− d1)TSW Vo1 Vo1∕2
Vo1/2 Vo1/2
vab 0 vab 0 vab
d1TSW d2TSW d2TSW d1TSW d1TSW d2TSW
State 16 13 12 16 14 10 16 13 12 16 14 10 16 6 10 16 8 12 16 6 10 16 8 12 15 9 14 15 11 13 15 9 14 15 11 13

(a) (b) (c)

Fig. 3. Typical waveforms of the proposed converter, including the control signals of the switches, inductors currents, unfiltered step-down output
voltage vab, and the switching states for all operating cases: (a) case A, (b) case B, (c) case C.
 1  v 
obtained in each case independently. According to Table I and vin  d2     vin  o1   d1  d2 
 2   2 
the switching sequences in Fig. 3(a), the output voltages’
State 16 State 13
conversion ratio can be obtained for case A as follows:
For the inductor L1,   vin  vo1 1  d1   0
State 12

vo1 1
Hence,  . (1)
vin 2  d1  d2

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TABLE II
+
OPERATING RANGE OF THE SIDO-TLC
180° −
S2
Case Duty-cycle limits Voltage limits − dpI1_A d2
vo1 ∑ PI1_A +
S3
1/2 < d1 & d2 < 1 0° −
A vin/2 < vo2 < vo1/2 +
d1 > d2
1/2 < d1 & d2 < 1 0 < vo2 < vin/2 Vo1,ref
B
d1 < d2 vo1 > 2(vin−vo2) +
d2+1/2 < d1 < 1 vo1/2 < vo2 < vo1 S4
C 180° −
0 < d2 < 1/2 vin < vo1 < 2vin − dpI2_A ++ d1
vo2 ∑ PI2_A ∑ +
S1
+ 0° −
And for the inductor L2,
Vo2,ref
1 v 
 vo2   d2     o1  vo2   d1  d2 
 2   2  Fig. 4. Block diagram of the closed-loop control system for case A
(excluding the balancing control system).
State16 State13

v 
  o1  vo2  1  d1   0 has exclusive PI controllers (e.g. PI1_A & PI2_A for case A in
 2  Fig. 4). In this study, the control strategy will be described for
State12 case A, and other cases will be designed with the same
approach. According to Fig. 4, both output voltages are
vo2
Hence,  1  d2 . (2) compared with their reference values (Vo1,ref and Vo2,ref for boost
vo1 and buck outputs, respectively). The generated error signals
vo2 vo2 vo1 1  d2 will then pass through PI1_A and PI2_A, producing dPI1_A and
Thus,    . (3) dPI2_A, respectively. According to Table II, d1 is greater than d2.
vin vo1 vin 2  d1  d2
To meet this condition, d1 and d2 are obtained as follows:
The voltage gains in cases B and C can also be achieved in the d2  dPI 1_ A
same way as the above procedure. (6)
d1  dPI 1_ A  dPI 2_ A .
Voltage gains for all three cases become
Thus, the step-up output is regulated by d2, and the step-down
 1 output is regulated by d1, while d2 is constant.
 2  d  d , Case A & Case B
vo1  1 2 B. Voltage Balancing Control Strategy
 (4)
vin  1 In practice, the voltages of the series capacitors C11 and C12
, Case C
 1  d2 will deviate from each other due to the asymmetry of the series
switches and their drive signals [14], [15], as well as the leakage
 1  d2
 , Case A & Case B currents of the capacitors [16]. Another reason could be the
vo2  2  d1  d2 (5) electronic elements which are not essentially identical despite
 .
vin  d1  d2 the fact that their factory specifications are the same. This
, Case C

 1  d2 unbalancing will cause problems such as damaging the switches
and diodes, reducing the quality of the output waveforms, and
From (4) and (5), it can be seen that d1 and d2 are the control
reducing the total lifetime of the circuit. The objective of the
parameters for both output voltages. In cases A and B, the step-
balancing control strategy for the proposed converter is meeting
up output voltage is related to both d1 and d2, while in the case (7):
C, it is only related to d2. On the other hand, the step-down v
output voltage in all three cases is related to both d1 and d2. vC 11  vC 12  o1 . (7)
2
More detailed study of the control strategy will be conducted in
For pursuing that, one of the voltages of the capacitors should
the following section.
be sensed and compared with vo1/2. Again the balancing
control procedure will be explained for case A.
III. CONTROL AND DYNAMICS
On the assumption that the SIDO-TLC operates in case A, if
A. Closed-Loop Control Strategy vC11 > vo1/2, vC11 should be decreased in comparison with vC12.
In this paper, the method utilized for control strategy is Thus, according to Table I, the time lengths of the switching
taken from the conventional three-level buck and boost states 12 and 14 should be increased, and the time lengths of 10
converters. Nonetheless, due to the novelty of the SIDO-TLC, and 13 should be decreased. To fulfill the aim, as shown in
a new control design is required. As previously mentioned, the Fig. 5, the pulse width of S1 and S2 should be increased, and the
proposed converter consists of three separate cases. In order to pulse width of S3 and S4 should be decreased, which means:
regulate both step-up and step-down output voltages, two
proportional-integral (PI) compensators have been employed
for each case. Having its own switching sequence, each case

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1 d1+Δd 1
d1− Δd  iˆL1   iˆL1   
d2+Δd 
ˆ
 
ˆ
  dˆ1   L1 
0.5 d2− Δd  i  i
 L2    0
d  L2 
ˆ o1   A.  vˆo1    B .  dˆ2     .vˆ in
v
0 dt      ˆ  0 
 vˆ o2   vˆo2   d   0 
S1      
16 13 12 16 14 10  vˆC   vˆC   0 
S2
 iˆL1 
 
 vˆo1  0 0 1 0 0  iˆL2 
S3
 vˆ   0 0 0 1 0 .  
 o2     vˆo1  (12)
S4  vˆC  0 0 0 0 1  vˆ 
o2
TSW∕2 TSW  
Fig. 5. Effect of balancing duty-cycle on the control signals of the  vˆC 
switches and time length of the switching sates in case A. where [A] and [B] are the system and control matrices,
respectively. Also, v̂ o1, v̂ o2, and Δv̂ C compose the outputs of the
dS 1  d1  d control system.
dS 2  d2  d In the ideal situation, the steady-state voltage balancing error
(8) (ΔVC) and also ΔD are equal to zero. However, due to the non-
dS 3  d2  d
idealities such as the leakage currents (i.e. when using
dS 4  d1  d electrolytic capacitors), ΔVC has a non-zero value. If so, the
where Δd is the balancing duty-cycle. designed balancing control system should produce an
appropriate Δd to tend ΔvC to zero. The leakage currents of the
C. Small-Signal Modeling
series capacitors are modeled with two constant dc current
Obtaining the small-signal model of a converter is a high sources (ILeak1 and ILeak2) paralleled with C11 and C12,
priority in designing the control system. In this paper, the respectively [16]. The relation between the leakage currents and
balancing control strategy has been taken into account in the the steady-state balancing duty-cycle, in case A, can be
small-signal modeling of the SIDO-TLC. In the proposed expressed as:
approach, averaging of inductors currents and capacitors
voltages in one switching period has been done for each case ILeak 2  ILeak1 ILeak
separately. The state space averaging in one switching period, D   . (13)
4IL1  2IL2 4IL1  2IL2
for each case, can be expressed as

t TSW In order to obtain the linearized state-space equations, the

1
 x  d  X  xˆ inductors’ volt-second balance and capacitors’ charge balance
 x  (9)
TSW are analyzed in one switching period then the second-order ac
t terms are neglected. By assuming C11= C12= C1, and considering
where TSW is the switching period, X is a dc steady-state value, the resistive loads Ro1 and Ro2 at the step-up and step-down
and x̂ is a small perturbation around X. The dynamic variables terminals, respectively, the matrices [A] and [B] can be
of the proposed converter are expressed as:

iL1   IL1  iˆL1 iL2   IL2  iˆL2  A

vo1   Vo1  vˆo1 vo2   Vo2  vˆo2  D1  D2  2 2D 
 0 0 0
L1 
(10)
vC  VC  vˆC d  D  dˆ 
L1

 1  D2 1 D 
d  D  dˆ a d  D  dˆ .  0 0   
1 1 1 2 2 2
 L2 L2 L2 
 2  D  D  2 21  D2  2 
The voltage balancing error ΔvC=vC11−vC12 caused by the voltage   1 2
  0 0 
unbalancing across the series capacitors is controlled by Δd.  C1 C1 Ro1C1 
 
 1 1
The relation between the step-up output voltage and its 0 0  0 
capacitors voltages is  C2 C2Ro2 
 
v v v v  4D 2D
vc11    o1  c  vc12    o1  c  . (11)  0 0 0 
2 2 2 2  C1 C1 
 
The state-space model in each case can finally be expressed as: (14)

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 Vo1 Vo1 2VC  Uncompensated

 L L1 L1  150 Compensated
 1  ΔD=4e-3

Magnitude (dB)
100

 V VC  50

 0  o1  
L2 L2
0
  −50
(15)
    2IL1
B  2 I L2  I L1 
0
.

−100
450
 C1 C1 
 

Phase (deg)
360

 0 0 0  270

 2 I L2  2I L1   180
 0 0  90
 C1  10−3 10−2 10−1 100 101 102 103 104 105 106
Frequency (Hz)
(a)
D. Compensator Design Uncompensated
150
Compensated
The operation of the SIDO-TLC has been validated using a 100

Magnitude (dB)
ΔD=4e-3
lab prototype. The converter’s specifications for a design 50
0
example are shown in Table III. Regarding these specifications, −50
the SIDO-TLC operates in case A, as in compliance with the −100
−150
relations in Table II. Also, Table IV shows the selected 360
components of the converter. From (12), (14), and (15), the 270

Phase (deg)
control transfer functions of the converter is obtained through 180
90
MATLAB software. The corresponding Bode diagrams have 0
also been plotted in order to design the optimal control system. −90
10−3 10−2 10−1 100 101 102 103 104 105
As previously mentioned, the step-up output voltage is Frequency (Hz)
regulated by d2, and the step-down output voltage is regulated (b)
by d1. The control transfer functions with constant coefficients 200
ΔD=0
Magnitude (dB)

are expressed in (16)–(18) at the ideal situation (ΔD= 0) as well 150

ΔD=4e-3
as at the condition when the leakage currents of the series 100

capacitors are included (ΔD= 0.004). The constant coefficients 50

of (16)–(18) are provided in APPENDIX. 0

180

TABLE III
Phase (deg)

135
DESIGN EXAMPLE SPECIFICATIONS FOR THE SIDO-TLC
90

Parameter Value 45
10-3 10-2 10-1 100 101 102 103 104
Total Output Power (Po) 300 W Frequency (Hz)
Input Voltage (Vin) 60 V (c)
Step-Up Output Voltage (Vo1) 125 V
Fig. 6. Bode diagrams of the designed SIDO-TLC. (a) Loop gain of the
Step-Down Output Voltage (Vo2) 36 V step-up output before the compensation, after the compensation with
Step-Up Resistive Load (Ro1) 65 Ω ΔD=0, and after the compensation with ΔD=0.004 [see (16)]. (b) Loop
Step-Down Resistive Load (Ro2) 20 Ω gain of the step-down output ——, [see (17)]. (c) Balancing control
Switching Frequency (fSW) 20 KHz transfer function (Δv̂ C/Δd̂ ) with ΔD=0, and ΔD=0.004 [see (18)].

vˆo1 3 s3  2 s2  1 s  0
TABLE IV D 0 
COMPONENT LIST OF THE SIDO-TLC dˆ2 s 4  3 s3  2 s2  1 s  0
(16)
vˆo1 4 s 4  3 s3  2 s2  1 s  0
D  4103

dˆ s5  4 s 4  3 s3  2 s2  1 s  0
Component Attribute Specification
2

Inductor (L1) 401 μH Iron powder core: vˆo2 1 s   0

D 0 
dˆ s 4  3 s3  2 s2  1 s  0
T184-26
Wire: AWG #20 1
Inductor (L2) 740 μH (17)
vˆo2 2 s2  1 s   0
D  4103

Capacitor (C11) 31 μF
dˆ1 s5  4 s 4  3 s3  2 s 2  1 s  0
Capacitor (C12) 30 μF Film capacitor
vˆc 0
4.5 μF D 0 
dˆ
Capacitor (C2)
s
MOSFETs IRF540NPbF (18)
(S1-S4)
100 V/ 33 A vˆc 4 s 4  3 s3  2 s2  1 s  0
(International Rectifier)
D  4103

Diodes
600 V/ 15 A
MUR1560G dˆ s5  4 s 4  3 s3  2 s2  1 s  0
(D11-D12) (On Semiconductor)

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A. Steady State Test

From (16)–(18), the Bode diagrams of the loop gains for both 1) Main Waveforms
outputs are illustrated in Fig. 6. Fig. 8 shows the steady-state behavior of the proposed
As can be seen in Figs. 6(a) and 6(b), before the converter. In Fig. 8(a), it is seen that the ripple frequency of the
compensation, the phase for both the step-up and step-down inductors currents is twice as much as the switching frequency.
loops are 360 degree at the gains more than unity, which can Also, a 180 degree phase shift between the control signals of S2
lead to system instability. In order to make the gain plots pass and S3 can be seen from the figure. In Figs. 8(b) and 8(c), it is
0 dB line at the slope of −20 dB/dec, and at the same time have shown that the voltage stress on the switches and diodes is
sufficient phase and gain margins, a simple PI controller has 62.5 V i.e. half of the step-up output voltage. It is also seen in
been used for each loop. In this case, the selected PI controller’s Fig. 8(c) that vab is between 0 and 62.5 V (Vo1/2), which is in
proportional and integral gains for the step-up loop are 0.15 and compliance with Fig. 3(a) in case A.
74, and for the step-down loop are 0.09 and 228, respectively.
After the compensation, the step-up loop’s phase margin is
63 degree and its gain margin is 28.1 dB. Also, the step-down
loop’s phase margin is 91 degree and its gain margin is iL1= [2 A/ div]
15.75 dB.
iL2= [1 A/ div]
IV. EXPERIMENTAL RESULTS
As shown in Fig. 7, a 300 W SIDO-TLC lab prototype has
been built with the parameters of Tables III and IV.
vGS2= [50 V/ div]

vGS3= [50 V/ div]

(a)

vo1= [100 V/ div]

vo2= [20 V/ div]

vS1= [50 V/ div]

vD11= [50 V/ div]

(b)
Fig. 7. Photo of the designed experimental prototype.

It should be noted that the power diodes used in the

vo1= [100 V/ div] vab= [50 V/ div]
experimental prototype are overdesigned ones available in our
laboratory (which 100 V diodes could be used instead). The
control algorithm was executed by the DSP TMS320F28335
from Texas Instruments with the sampling period (TS) equal to
the switching period. The control specifications are first
designed in the continuous-time S domain then they are iL2= [1 A/ div]
transferred to the discrete-time Z domain to be feasible in the
digital controller. In order to implement the PI compensators in
the control algorithm, a Forward Euler method has been used.
This approximation is vS2= [50 V/ div]
1 T 5
 S , TS  TSW  5  10 (s).
(c)
(19)
S Z 1 Fig. 8. Steady-state experimental waveforms of the SIDO-TLC
(Vin=60 V, Vo1=125 V, Vo2=36 V, Ro1=65 Ω, Ro2=20 Ω). (a) Inductors currents
and the control signals of S1 and S2. (b) Output voltages, voltage across
S1 and D11. (c) Step-up output voltage, current of L2, unfiltered step-down
output voltage vab, voltage across S2.

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2) Effect of Non-Idealities 105

Step-Up Output Voltage (Vo1)

Like the conventional dc-dc converters, the SIDO-TLC is 100
affected by non-idealities such as inductors’ series resistance 95
and switches ON-state resistance. To illustrate the effect of 90
these non-idealities on the operation of the proposed converter, 85
the steady-state output voltages are compared in calculation
80 Vo1 (Calculation)
(through (4), and (5)), ideal simulation, and experimentation for
various ranges of duty-cycles. Figs. 9 and 10 Show the 75 Vo1 (Simulation)
comparison at different duty-cycles. The comparisons are 70 Vo1 (Experimentation)
conducted at the constant input voltage of Vin=60 V, and of the 65
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
two duty-cycles, one is kept constant and the other one is D1
D2=0.55
varying to see the change in the output voltages. Fig. 9 shows (a)
Vo1 (Calculation)

Step-Up Output Voltage (Vo1)

the variation in the step-up output voltage with the variation of 125
D1 and D2, respectively, while keeping one of them constant and 120 Vo1 (Simulation)
the other one varying; with the same approach, Fig. 10 shows 115 Vo1 (Experimentation)
the variation in the step-down output voltage. As a result, the 110
experimental values of Vo1 and Vo2 deviate from those of 105
100
calculation or simulation typically about 2.5% and 2%,
95
respectively. The calculation and ideal simulation match 90
accurately with each other, proving that the calculated 85
equations for gains are precisely obtained. Also, all in all, there 80
is a good match of the experimental values with those of 75
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
calculation or simulation. D2
D1=0.6
B. Transient State Test (b)
Fig. 9. Comparative analysis of calculated, simulated, and experimental
1) Step Change of Loads results of the output voltages with variations in D1 and D2 for Vo1.
In order to test the stability of the system under dynamic
changes, two different situations are considered. In the first
Step-Down Output Voltage (Vo2)

46
situation, step changes are applied to the input voltage and the
44
step-up output load, and in the second situation, step changes
42
are applied to the input voltage and the step-down output load.
40
In fact, the simultaneous step changes of load and input voltage
can be regarded as a bigger challenge for the control system 38

rather than the individual change of the load or the input 36 Vo2 (Calculation)
voltage. In Fig. 11(a), the resistive load at the boost terminal 34 Vo2 (Simulation)
changes from Ro1= 65 Ω to Ro1=303 Ω, and at the same time, 32 Vo2 (Experimentation)
the input voltage steps up from Vin=56 V to Vin=60 V. Under 30
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
this condition, vo1 settles to its reference value in about 60 ms D2=0.55 D1
with a 20% overshoot (25 V), and vo2 in about 80 ms with a 12% (a)
Step-Down Output Voltage (Vo2)

undershoot (4.2 V). It is clear that the output voltages are stably 30
Vo2 (Calculation)
regulated at their predetermined values of Vo1=125 V and 28
Vo2 (Simulation)
Vo2=36 V under dynamic changes, owing to the satisfactory 26
Vo2 (Experimentation)
24
performance of the closed-loop control system. 22
In Fig. 11(b), the resistive load at the buck terminal changes 20
from Ro2=135 Ω to Ro2=20 Ω, and at the same time, the input 18
voltage steps down from Vin= 60 V to Vin=59 V. As it can be 16
14
seen, the output voltages are insensitive to the simultaneous
12
changes of the input voltage and step-down terminal load. 10
2) Autonomous Transition Through Cases 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
D1=0.6 D2
As seen in Fig. 12, with the sudden change of the input
(b)
voltage from 60 V to 92 V, the control system autonomously Fig. 10. Comparative analysis of calculated, simulated, and
switches from case A to B, and the output voltages are well experimental results of the output voltages with variations in D1 and D2
regulated at their predetermined values. for Vo2.

C. Balancing Strategy Test in Fig. 13(a), without the balancing control technique, the
In order to test the proposed balancing strategy of the voltage difference between the series capacitors reaches 20 V,
SIDO-TLC practically, an unbalanced condition at the step-up yet if the unbalancing increases, the switches and diodes will be
terminal has been provided. Fig. 13 shows iL1, vC11, vC12, and vo1 damaged. By applying the balancing control strategy, as seen in
with and without the balancing control strategy. As can be seen Fig. 13(b), the voltages are precisely balanced, and the output

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60 V
56 V
vC11 [10 V/ div] 72.5 V
vin [10 V/ div]
52.5 V
io1 [1 A/ div]
vC12 [10 V/ div]
8.32 V/div 20 ms/div

iL1 [2 A/ div]

vo1 [100 V/ div]

125 V
vo2 [50 V/ div] vo1 [100 V/ div]
4.16 V/ div 20 ms/ div

(a)
(a)

60 V 59 V vC12 [10 V/ div]

vin [10 V/ div]
62.5 V
vC11 [10 V/ div]

iL1 [2 A/ div]
io2 [1 A/ div]
vo1 [100 V/ div]

vo2 [50 V/ div] 125 V

vo1 [100 V/ div]

(b) (b)
Fig. 11. Transient state experimental waveforms of the SIDO-TLC due Fig. 13. Experimental waveforms of series capacitors voltages, step-up
to the varied load and input voltage. (a) Load at the step-up terminal output voltage, and iL1 in an unbalanced condition. (a) Without the
changes from Ro1=65 Ω to Ro1=303 Ω, and input voltage changes from balancing control system, (b) with the proposed balancing control
56 V to 60 V. (b) Load at the step-down terminal changes from technique.
Ro2=135 Ω to Ro2=20 Ω, and input voltage changes from 60 V to 59 V.

D. Efficiency and Comparison

The efficiency of the SIDO-TLC has been measured in two
different conditions: Firstly, when the powers of the two
92 V
outputs are equal to each other, namely Po1=Po2. Secondly,
60 V
vin [50 V/ div] when the power of the step-up output is twice as much as that
of the step-down, namely Po1=2Po2. In both conditions, the
Case A Case B
terminal voltages are fixed at Vin=60 V, Vo1= 125 V, and
Vo2= 36 V. Fig. 14 illustrates the measured efficiencies. The
12.5 V/ div 20 ms/div vo1 [100 V/ div] average of the measured efficiencies is 95.03%, and the
efficiency peaks at 95.9%. Despite using the overdesigned
diodes, the obtained efficiencies are high. This could be
attributed to the fact that both conduction and switching losses
vo2 [50 V/ div]
are reduced in comparison with the conventional two-level
6.25 V/ div 20 ms/div
structures. The conduction losses are reduced because
MOSFETs with less ON-state resistance could be used due to
the considerable reduction of the voltage stress across the
Fig. 12. Autonomous transition from case A to case B with the sudden switches [17]. Also, the diode reverse recovery losses are
change of the input voltage from 60 V to 92 V.
reduced because the voltage stress on the diodes is only half of
the step-up output voltage, so the total switching losses are
voltages stay regulated at the same time. This highly accurate
significantly reduced [17]. In Table V, some SIDOCs have been
balance of the series capacitors voltages is due to the wide
found to be compared with the proposed SIDO-TLC in terms of
variety of the switching state redundancies. This makes the
voltage stress and efficiency. As can be seen in Table V, most
converter appropriate for the applications such as the three-
of the SIDOCs in previous works are buck-type converters,
level diode clamped inverters in which the dc link capacitors
such as [19]–[21]. In fact, very few references propose
voltage balancing is very important.
converters generating both step-up and step-down outputs

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97 clamped inverters in which the dc link capacitors voltage

balancing is of great importance.
96
Efficiency (%) APPENDIX
95
CONTROL TRANSFER FUNCTION COEFFICIENTS [(16) – (18)]
94
v̂ o1/d̂ 2:
93 3  2.184E5, 2  1.084E10, 1  7.84E13, 0  2.996E18,
Po1= Po2
92 3  1.191E4, 2  3.572E8, 1  8.048E11, 0  1.15E16,
Po1= 2Po2
4  2.249E5, 3  1.077E10, 2  7.644E13, 1  2.995E18,
91
50 100 150 200 250 300 0  6.874E17, 4  1.191E04, 3  3.572E08, 2 =8.049E11,
Total output power (W) 1 =1.151E16, 0 =3.281E15.
Fig. 14. Efficiency curve of the prototype as a function of the total output
power in the conditions where Po1=Po2, and Po1=2Po2. v̂ o2/d̂ 1:
1  2.906E13, 0  8.627E17, 3  1.191E4, 2  3.572E8,
TABLE V
PERFORMANCE COMPARISON OF THE PROPOSED SIDO-TLC WITH OTHER
1  8.048E11, 0  1.15E16, 2  2.963E13, 1  8.629E17,
ANNOUNCED SIDOCS 0  1.51E17, 4  1.191E4, 3  3.572E8, 2  8.049E11,
Maximum 1  1.151E16, 0  3.281E15.
voltage stress
Reference
Terminal
Efficiency on Δv̂ C/Δd̂ :
voltages
semiconductor 0  5.545E5, 4  5.675E5, 3  6.761E9, 2  2.027E14,
devices
Vin=12 V 1  4.567E17, 0  6.528E21, 4  1.191E4,
Vo1=18 V vo1
[9]
Vo2=6 V
Around 90%
3  3.572E8, 2  8.049E11, 1  1.151E16, 0  3.281E15.
Vin=15 V
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0278-0046 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2807384, IEEE
Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

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Amir Ganjavi was born in Babol, Iran, in 1990.

He received the B.Sc. and M.Sc. degrees in
electrical engineering from Babol Noshirvani
University of Technology, Babol, Iran, in 2014
and 2017, respectively.
His research interests include dynamic
control and stability of power electronic systems,
power converters and their applications in
renewable energy, high-voltage high-power
multilevel converters, multiport circuits, and dc
microgrids.

Hoda Ghoreishy received her B.Sc. in electrical

engineering from Amir Kabir University of
Technology, Tehran, Iran, in 2004, her M.Sc. in
electrical engineering from Mazandaran
University, Babol, Iran, in 2006 and her Ph.D. in
electrical engineering, specializing in power
electronics and motor drives, from Tarbiat
Modares University, Tehran, Iran in 2012.
Since 2012, she has been with Babol
Noshirvani University of Technology, Babol,
Iran, as an Assistant Professor in the Department of Electrical and
Computer Engineering. Dr. Ghoreishy’s main research interests include
the modeling, analysis, design, and control of power electronic
converters/systems and motor drives. Her area of interest also includes
embedded software development for power electronics and electric
drives using microcontrollers and DSPs.

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