Arora Ⅴ Series of FPGA Products

GW5AT-138 Pinout Preliminary

Version History

Date Version Description

01/05/2023 1.0E Initial version published. Package FPG676A supported.

© 2023 GOWINSEMI UG982-1.0E 1(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin Definitions
Pin Name I/O Description
User I/O
[End] indicates the pin location, including L(left), R(right), B(bottom), and T(top).
[Row/Column Number] indicates the pin row/column number. If [End] is T(top) or B(bottom), the pin indicates the
IO[End][Row/Column column number of the corresponding CFU. If [End] is L(left) or R(right), the pin indicates the row number of the
I/O/LVDS
Number][A/B] corresponding CFU.
[A/B] indicates differential signal pair information.
LVDS indicates that the pin only supports LVDS output.
Multi-Function Pins
/MMM represents one or more of the other functions in addition to being general purpose user I/O. When these
IO[End][Row/Column Number][A/B]/MMM
functions are not in use, these pins can be used as user I/O.
D00 I/O CPU Mode: Data input/output (bidirectional) pin D00
CPU Mode: Data input/output (bidirectional) pin D01
D01 I/O MSPI Mode: Serial data input in X1 mode; In X2 and X4 modes, the input pin of parallel data bit 1 that connects
to pin DQ1/Q/SO/IO1 of external Flash device
CPU Mode: Data input/output (bidirectional) pin D02
D02 I/O MSPI Mode: In X4 mode, the input pin of parallel data bit 2 that connects to pin DQ2/W#/WP#/IO2 of external
Flash device respectively
CPU Mode: Data input/output (bidirectional) pin D03
D03 I/O MSPI Mode: In X4 mode, the input pin of parallel data bit 3 that connects to pin DQ3/HOLD#/IO3 of external
Flash device respectively
D04~D07 I/O CPU Mode: Data input/output port D04~D07
D08~D31 I CPU Mode: Data input port D08~D31
ADCINCK0 I/O ADC0 dedicated clock input pin
ADCINCK1 I/O ADC1 dedicated clock input pin
Configuration Clock
CCLK I/O Slave Mode: CCLK is input and need connect to external clock source
Master Mode: CCLK is output
Configuration Bank Voltage Selection Signal (1 for 3.3/2.5V)
CFGBVS I/O Configuration Bank is bank3, bank4, and bank10
The function of pin CFGBVS is 1; The default bank voltage is 3.3/2.5V
CFGPU I/O Weak pull-up selection signal pin during configuration
External Input Clock Signal
EMCCLK I Master Mode: EMCCLK is used as the clock source of FPGA configuration logic and output CCLK
Slave Mode: EMCCLK is not associated with slave mode

© 2023 GOWINSEMI UG982-1.0E 2(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin Definitions
Pin Name I/O Description
MCKTEST I/O MCLK CIB output test pin
FBTEST_L0 I/O Internal test pin
FBTEST_R0 I/O Internal test pin
CLKTEST_L0 I/O Internal test pin
CLKTEST_R0 I/O Internal test pin
MSPI Mode: Serial instruction and address output, in X2 and X4 modes, the input pin of parallel data bit 0 that
MOSI I/O
connects to pin DQ0/D/SI/IO0 of external Flash device
CPU Mode: Chip select signal, active-low
Master CPU Mode: The chip select signal can connect to external configuration controller and can be grounded
directly or grounded in series with a 1KΩ resistor
CSI_B I
Slave CPU Mode: External configuration controller can select FPGA through controlling CSI_B signal
In Master and Slave modes, CSI_B signal is sent from external controller; In other modes, CSI_B signal is not
associated with external controller
Connect to next-level device in FPGA cascade configuration mode (Daisy Chain)
Serial Mode: Output the configuration data of next-level device
DOUT_CSO_B O
Master SPI Mode: Output the configuration data of next-level device
CPU Mode: Output the chip select signal of next-level device
Active-low, weak pull-up selection signal pin during configuration：
Enable internal weak pull-up resistor during configuration after FPGA power up
PUDC_B I PUDC_B low: all GPIOs except PUDC_B weak pull-up
PUDC_B high: all GPIOs are in high impedance
PUDC_B are not allowed to be left floating during configuration
CPU Mode: Data write/read controlling signal
When RDWR is high, FPGA outputs data, while RDWR is low, external controller writes data into FPGA
Master CPU Mode: Connect external controller RDWR signal; Connect directly or in series with resistor ≤ 1KΩ
RDWR I to GND
Slave CPU Mode: External controller RDWR signal
In CPU mode, low 8-bit dedicated IO will be affected by RDWR status after wakeup; low 8-bit dedicated IO will
not be affected by RDWR status if it is set as multiplexed IO
SSPI_CLK I/O SSPI/QSSPI Configuration Mode: Clock input pin
SSPI_WPN I/O QSSPI Configuration Mode: Data input pin
SGCLKC_[x] I Differential input pin of SGCLKT_[x], C(Comp), [x]: clock No.
SGCLKT_[x] I Dedicated clock input pin driving the same clock domain ,T(True), [x]: clock No.

© 2023 GOWINSEMI UG982-1.0E 3(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin Definitions
Pin Name I/O Description
MGCLKC_[x] I Differential input pin of MGCLKT_[x], C(Comp), [x]: clock No.
MGCLKT_[x] I Dedicated clock input pin driving multiple clock domains, T(True), [x]: clock No.
VREF Reference Voltage
DOUT O SERIAL Mode: Data output
I, internal weak
DIN SERIAL Mode: Data input
pull-down
I, internal weak
TMS JTAG Mode: Serial mode input
pull-up
TCK I JTAG Mode: Serial clock input
TDO O JTAG Mode: Serial data output
I, internal weak
TDI JTAG mode: Serial data input
pull-up
I, internal weak
RECONFIG_N Global reset GowinCONFIG logic signal, active low
pull-up
High, the programming configuration has been completed successfully;
[1] O
DONE Low, the programming configuration has not been completed or failed.
I When the DONE signal is low, delay the chip to activate. Activate the chip until the DONE signal is high.
High, the device can be programmed and configured currently;
READY[1] O
Low, the device cannot be programmed and configured currently.
MCS_N O MSPI Mode: Enable signal MCS_N, active-low
SSPI_CS_N I/O SSPI Mode: Enable signal SSPI_CS_N, active-low, and internal weak pull-up
LPLL_C_fb/RPLL_C_fb I Left/Right PLL feedback input pin, C(Comp)
LPLL_T_fb/RPLL_T_fb I Left/Right PLL feedback input pin, T(True)
LPLL_C_in/RPLL_C_in I Left/Right PLL clock input pin, C(Comp)
LPLL_T_in/RPLL_T_in I Left/Right PLL clock input pin, T(True)
I, internal weak GowinCONFIG mode selection pin
MODE2
pull-down If this pin is not bonded, it's internally grounded.
I, internal weak GowinCONFIG mode selection pin
MODE1
pull-down If this pin is not bonded, it's internally grounded.
I, internal weak GowinCONFIG mode selection pin
MODE0
pull-down If this pin is not bonded, it's internally grounded.

© 2023 GOWINSEMI UG982-1.0E 4(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin Definitions
Pin Name I/O Description
Other Pins
VSS NA Ground
VCC NA Power supply pin of core voltage
VCCO# NA Power supply pin of I/O voltage for I/O BANK#
VCCC NA Power supply pin of clock tree voltage
VCCX NA Power supply pin of auxiliary voltage
VCC_REG NA Power supply pin of Regulator voltage
Q*_VDD* NA Power supply pin of SerDes voltage
M*_VDD* NA Power supply pin of MIPI voltage
Note!
[1] The default state of READY/DONE is open-drain output, internal weak pull-up. DONE outputs 0 during configuration.

© 2023 GOWINSEMI UG982-1.0E 5(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Bank

MIPI SerDes Bank Q0 SerDes Bank Q1

I/O Bank7

I/O Bank2
GW5AT-138
I/O Bank6

I/O Bank3
I/O Bank5 I/O Bank4 I/O Bank10

Note!
[1] Each Bank has independent reference voltage (VREF).
[2] You can choose to use the embedded VREF source of IOB (0.6V, 0.675V, 0.75V, 0.9V, and VCCO-based scaled voltages (33%,42%,50%,58%)).
[3] You can also select to use external VREF input (use any IO pins as external VREF input).

© 2023 GOWINSEMI UG982-1.0E 6(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB102A I/O 4 DQ12 True_of_IOB102B True x16 M16
IOB102B/VREF I/O 4 DQ12 VREF Comp_of_IOB102A True none M17
IOB104A I/O 4 DQS12 True_of_IOB104B True x16 K16
IOB104B I/O 4 DQS12 Comp_of_IOB104A True none K17
IOB106A I/O 4 DQ13 True_of_IOB106B True x16 K22
IOB106B I/O 4 DQ13 Comp_of_IOB106A True none K23
IOB108A I/O 4 DQ13 True_of_IOB108B True x16 F23
IOB108B I/O 4 DQ13 Comp_of_IOB108A True none E23
IOB110A I/O 4 DQS13 True_of_IOB110B True x16 G22
IOB110B I/O 4 DQS13 Comp_of_IOB110A True none F22
IOB112A I/O 4 DQ13 True_of_IOB112B True x16 J24
IOB112B I/O 4 DQ13 Comp_of_IOB112A True none H24
IOB114A/SGCLKT_4/BPLL2 SGCLKT_4/BPLL2_T_fb1
I/O 4 DQ13 True_of_IOB114B True x16 J23
_T_fb1/BPLL3_T_fb1 /BPLL3_T_fb1
IOB114B/SGCLKC_4/BPLL2 SGCLKC_4/BPLL2_C_fb1
I/O 4 DQ13 Comp_of_IOB114A True none H23
_C_fb1/BPLL3_C_fb1 /BPLL3_C_fb1
IOB116A/MGCLKT_4/BPLL2 MGCLKT_4/BPLL2_T_fb0
I/O 4 DQ13 True_of_IOB116B True x16 H21
_T_fb0/BPLL3_T_fb0 /BPLL3_T_fb0
IOB116B/MGCLKC_4/BPLL2 MGCLKC_4/BPLL2_C_fb
I/O 4 DQ13 Comp_of_IOB116A True none H22
_C_fb0/BPLL3_C_fb0 0/BPLL3_C_fb0
IOB120A/SGCLKT_5/BPLL2 SGCLKT_5/BPLL2_T_in0/
I/O 4 DQ14 True_of_IOB120B True x16 G20
_T_in0/BPLL3_T_in0 BPLL3_T_in0
IOB120B/SGCLKC_5/BPLL2 SGCLKC_5/BPLL2_C_in0
I/O 4 DQ14 Comp_of_IOB120A True none G21
_C_in0/BPLL3_C_in0 /BPLL3_C_in0
IOB122A/MGCLKT_5/BPLL2 MGCLKT_5/BPLL2_T_in1
I/O 4 DQ14 True_of_IOB122B True x16 K21
_T_in1/BPLL3_T_in1 /BPLL3_T_in1
IOB122B/MGCLKC_5/BPLL2 MGCLKC_5/BPLL2_C_in
I/O 4 DQ14 Comp_of_IOB122A True none J21
_C_in1/BPLL3_C_in1 1/BPLL3_C_in1
IOB124A I/O 4 DQ14 True_of_IOB124B True x16 L17
IOB124B I/O 4 DQ14 Comp_of_IOB124A True none L18
IOB126A I/O 4 DQ14 True_of_IOB126B True x16 J19

© 2023 GOWINSEMI UG982-1.0E 7(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB126B I/O 4 DQ14 Comp_of_IOB126A True none H19
IOB129A I/O 4 DQ14 True_of_IOB129B True x16 J18
IOB129B I/O 4 DQ14 Comp_of_IOB129A True none H18
IOB131A I/O 4 DQS14 True_of_IOB131B True x16 K20
IOB131B I/O 4 DQS14 Comp_of_IOB131A True none J20
IOB133A I/O 4 DQ15 True_of_IOB133B True x16 E25
IOB133B/VREF I/O 4 DQ15 VREF Comp_of_IOB133A True none D25
IOB135A I/O 4 DQS15 True_of_IOB135B True x16 E26
IOB135B I/O 4 DQS15 Comp_of_IOB135A True none D26
IOB138A I/O 4 DQ15 True_of_IOB138B True x16 H26
IOB138B I/O 4 DQ15 Comp_of_IOB138A True none G26
IOB140A I/O 4 DQ15 True_of_IOB140B True x16 G24
IOB140B I/O 4 DQ15 Comp_of_IOB140A True none F24
IOB142A I/O 4 DQ15 True_of_IOB142B True x16 J25
IOB142B I/O 4 DQ15 Comp_of_IOB142A True none J26
IOB144A I/O 4 DQ15 True_of_IOB144B True x16 G25
IOB144B I/O 4 DQ15 Comp_of_IOB144A True none F25
IOB146A I/O 4 none none none K18
IOB169A/TDO I/O 10 none TDO True_of_IOB169B True none J10
IOB169B/TMS I/O 10 none TMS Comp_of_IOB169A True none H11
IOB171A/READY I/O 10 none READY True_of_IOB171B True none V11
IOB171B/DONE I/O 10 none DONE Comp_of_IOB171A True none W10
IOB173A/TCK I/O 10 none TCK True_of_IOB173B True none H12
IOB173B/TDI I/O 10 none TDI Comp_of_IOB173A True none H10
IOB175A/MODE0 I/O 10 none MODE0 True_of_IOB175B True none AB7
IOB175B/CCLK I/O 10 none CCLK Comp_of_IOB175A True none H13
IOB177A/MODE1 I/O 10 none MODE1 True_of_IOB177B True none Y9
IOB177B/MODE2 I/O 10 none MODE2 Comp_of_IOB177A True none W9
IOB179A/CFGBVS I/O 10 none CFGBVS True_of_IOB179B True none AB15
IOB179B/RECONFIG_N I/O 10 none RECONFIG_N Comp_of_IOB179A True none AE16
IOB37A I/O 5 none none none E22
IOB38A I/O 5 DQ8 True_of_IOB38B True x16 D23

© 2023 GOWINSEMI UG982-1.0E 8(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB38B I/O 5 DQ8 Comp_of_IOB38A True none D24
IOB40A I/O 5 DQ8 True_of_IOB40B True x16 C24
IOB40B I/O 5 DQ8 Comp_of_IOB40A True none B24
IOB42A I/O 5 DQS8 True_of_IOB42B True x16 A23
IOB42B I/O 5 DQS8 Comp_of_IOB42A True none A24
IOB44A I/O 5 DQ8 True_of_IOB44B True x16 B25
IOB44B I/O 5 DQ8 Comp_of_IOB44A True none A25
IOB47A I/O 5 DQ8 True_of_IOB47B True x16 C26
IOB47B I/O 5 DQ8 Comp_of_IOB47A True none B26
IOB49A I/O 5 DQ8 True_of_IOB49B True x16 C22
IOB49B/VREF I/O 5 DQ8 VREF Comp_of_IOB49A True none C23
IOB51A I/O 5 DQ9 True_of_IOB51B True x16 C17
IOB51B I/O 5 DQ9 Comp_of_IOB51A True none B17
IOB53A I/O 5 DQ9 True_of_IOB53B True x16 E16
IOB53B I/O 5 DQ9 Comp_of_IOB53A True none D16
IOB56A I/O 5 DQS9 True_of_IOB56B True x16 A17
IOB56B I/O 5 DQS9 Comp_of_IOB56A True none A18
IOB58A I/O 5 DQ9 True_of_IOB58B True x16 B19
IOB58B I/O 5 DQ9 Comp_of_IOB58A True none A19
IOB60A/SGCLKT_6/BPLL0_ SGCLKT_6/BPLL0_T_in0/
I/O 5 DQ9 True_of_IOB60B True x16 E17
T_in0/BPLL1_T_in0 BPLL1_T_in0
IOB60BSGCLKC_6/BPLL0_ SGCLKC_6/BPLL0_C_in0
I/O 5 DQ9 Comp_of_IOB60A True none E18
C_in0/BPLL1_C_in0 /BPLL1_C_in0
IOB62A/MGCLKT_6/BPLL0_ MGCLKT_6/BPLL0_T_in1
I/O 5 DQ9 True_of_IOB62B True x16 D18
T_in1/BPLL1_T_in1 /BPLL1_T_in1
IOB62B/MGCLKC_6/BPLL0_ MGCLKC_6/BPLL0_C_in
I/O 5 DQ9 Comp_of_IOB62A True none C18
C_in1/BPLL1_C_in1 1/BPLL1_C_in1
IOB66A/MGCLKT_7/BPLL0_ MGCLKT_7/BPLL0_T_fb0
I/O 5 DQ10 True_of_IOB66B True x16 D19
T_fb0/BPLL1_T_fb0 /BPLL1_T_fb0
IOB66B/MGCLKC_7/BPLL0_ MGCLKC_7/BPLL0_C_fb
I/O 5 DQ10 Comp_of_IOB66A True none C19
C_fb0/BPLL1_C_fb0 0/BPLL1_C_fb0

© 2023 GOWINSEMI UG982-1.0E 9(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB68A/SGCLKT_7/BPLL0_ SGCLKT_7/BPLL0_T_fb1
I/O 5 DQ10 True_of_IOB68B True x16 E20
T_fb1/BPLL1_T_fb1 /BPLL1_T_fb1
IOB68B/SGCLKC_7/BPLL0_ SGCLKC_7/BPLL0_C_fb1
I/O 5 DQ10 Comp_of_IOB68A True none D20
C_fb1/BPLL1_C_fb1 /BPLL1_C_fb1
IOB70A I/O 5 DQS10 True_of_IOB70B True x16 B20
IOB70B I/O 5 DQS10 Comp_of_IOB70A True none A20
IOB72A I/O 5 DQ10 True_of_IOB72B True x16 C21
IOB72B I/O 5 DQ10 Comp_of_IOB72A True none B21
IOB74A I/O 5 DQ10 True_of_IOB74B True x16 B22
IOB74B I/O 5 DQ10 Comp_of_IOB74A True none A22
IOB76A I/O 5 DQ10 True_of_IOB76B True x16 E21
IOB76B I/O 5 DQ10 Comp_of_IOB76A True none D21
IOB78A I/O 5 DQ11 True_of_IOB78B True x16 G15
IOB78B I/O 5 DQ11 Comp_of_IOB78A True none F15
IOB80A I/O 5 DQ11 True_of_IOB80B True x16 G17
IOB80B I/O 5 DQ11 Comp_of_IOB80A True none F17
IOB83A I/O 5 DQ11 True_of_IOB83B True x16 H14
IOB83B I/O 5 DQ11 Comp_of_IOB83A True none H15
IOB85A I/O 5 DQ11 True_of_IOB85B True x16 H16
IOB85B/VREF I/O 5 DQ11 VREF Comp_of_IOB85A True none G16
IOB87A I/O 5 DQ11 True_of_IOB87B True x16 G19
IOB87B I/O 5 DQ11 Comp_of_IOB87A True none F20
IOB89A I/O 5 DQS11 True_of_IOB89B True x16 F18
IOB89B I/O 5 DQS11 Comp_of_IOB89A True none F19
IOB91A I/O 5 none none none H17
IOB92A I/O 4 none none none L19
IOB93A I/O 4 DQ12 True_of_IOB93B True x16 M14
IOB93B I/O 4 DQ12 Comp_of_IOB93A True none L14
IOB95A/ADCINCK1 I/O 4 DQ12 ADCINCK1 True_of_IOB95B True x16 M15
IOB95B I/O 4 DQ12 Comp_of_IOB95A True none L15
IOB97A I/O 4 DQ12 True_of_IOB97B True x16 J14
IOB97B I/O 4 DQ12 Comp_of_IOB97A True none J15

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Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB99A I/O 4 DQ12 True_of_IOB99B True x16 K15
IOB99B I/O 4 DQ12 Comp_of_IOB99A True none J16
IOL101A I/O 6 DQ7 True_of_IOL101B True x16 E6
IOL101B I/O 6 DQ7 Comp_of_IOL101A True none D6
IOL103A I/O 6 DQ7 True_of_IOL103B True x16 H8
IOL103B I/O 6 DQ7 Comp_of_IOL103A True none G8
IOL105A I/O 6 DQ7 True_of_IOL105B True x16 F8
IOL105B I/O 6 DQ7 Comp_of_IOL105A True none F7
IOL107A/MCKTEST I/O 6 DQ7 MCKTEST True_of_IOL107B True x16 H9
IOL107B/VREF I/O 6 DQ7 VREF Comp_of_IOL107A True none G9
IOL109A I/O 6 none none x16 J8
IOL11A I/O 7 DQ0 True_of_IOL11B True x16 P6
IOL11B/VREF I/O 7 DQ0 VREF Comp_of_IOL11A True none P5
IOL13A I/O 7 DQ0 True_of_IOL13B True x16 R8
IOL13B I/O 7 DQ0 Comp_of_IOL13A True none P8
IOL15A I/O 7 DQ1 True_of_IOL15B True x16 U2
IOL15B I/O 7 DQ1 Comp_of_IOL15A True none U1
IOL17A I/O 7 DQ1 True_of_IOL17B True x16 T2
IOL17B I/O 7 DQ1 Comp_of_IOL17A True none R2
IOL1A I/O 7 none none x16 U4
IOL20A I/O 7 DQ1 True_of_IOL20B True x16 T4
IOL20B I/O 7 DQ1 Comp_of_IOL20A True none T3
IOL22A I/O 7 DQS1 True_of_IOL22B True x16 R1
IOL22B I/O 7 DQS1 Comp_of_IOL22A True none P1
IOL24A/MGCLKT_11/LPLL0 MGCLKT_11/LPLL0_T_in
I/O 7 DQ1 True_of_IOL24B True x16 R3
_T_in1/LPLL1_T_in1 1/LPLL1_T_in1
IOL24B/MGCLKC_11/LPLL0 MGCLKC_11/LPLL0_C_in
I/O 7 DQ1 Comp_of_IOL24A True none P3
_C_in1/LPLL1_C_in1 1/LPLL1_C_in1
IOL26A/SGCLKT_11/LPLL0_ SGCLKT_11/LPLL0_T_in
I/O 7 DQ1 True_of_IOL26B True x16 P4
T_in0/LPLL1_T_in0 0/LPLL1_T_in0

© 2023 GOWINSEMI UG982-1.0E 11(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOL26B/SGCLKC_11/LPLL0_ SGCLKC_11/LPLL0_C_in
I/O 7 DQ1 Comp_of_IOL26A True none N4
C_in0/LPLL1_C_in0 0/LPLL1_C_in0
IOL29A/MGCLKT_10/LPLL0 MGCLKT_10/LPLL0_T_fb
I/O 7 DQ2 True_of_IOL29B True x16 N3
_T_fb1/LPLL1_T_fb1 1/LPLL1_T_fb1
IOL29B/MGCLKC_10/LPLL0 MGCLKC_10/LPLL0_C_f
I/O 7 DQ2 Comp_of_IOL29A True none N2
_C_fb1/LPLL1_C_fb1 b1/LPLL1_C_fb1
IOL2A/ADCINCK0 I/O 7 DQ0 ADCINCK0 True_of_IOL2B True x16 T8
IOL2B I/O 7 DQ0 Comp_of_IOL2A True none T7
IOL31A/SGCLKT_10/LPLL0_ SGCLKT_10/LPLL0_T_fb
I/O 7 DQ2 True_of_IOL31B True x16 M2
T_fb0/LPLL1_T_fb0 0/LPLL1_T_fb0
IOL31B/SGCLKC_10/LPLL0_ SGCLKC_10/LPLL0_C_fb
I/O 7 DQ2 Comp_of_IOL31A True none L2
C_fb0/LPLL1_C_fb0 0/LPLL1_C_fb0
IOL33A/FBTEST_L0 I/O 7 DQ2 FBTEST_L0 True_of_IOL33B True x16 K1
IOL33B/CLKTEST_L0 I/O 7 DQ2 CLKTEST_L0 Comp_of_IOL33A True none J1
IOL35A I/O 7 DQS2 True_of_IOL35B True x16 N1
IOL35B I/O 7 DQS2 Comp_of_IOL35A True none M1
IOL38A I/O 7 DQ2 True_of_IOL38B True x16 L3
IOL38B I/O 7 DQ2 Comp_of_IOL38A True none K2
IOL40A I/O 7 DQ2 True_of_IOL40B True x16 H2
IOL40B I/O 7 DQ2 Comp_of_IOL40A True none H1
IOL42A I/O 7 DQ3 True_of_IOL42B True x16 N7
IOL42B I/O 7 DQ3 Comp_of_IOL42A True none N6
IOL44A I/O 7 DQ3 True_of_IOL44B True x16 M6
IOL44B/VREF I/O 7 DQ3 VREF Comp_of_IOL44A True none M5
IOL47A I/O 7 DQ3 True_of_IOL47B True x16 L5
IOL47B I/O 7 DQ3 Comp_of_IOL47A True none K5
IOL49A I/O 7 DQS3 True_of_IOL49B True x16 M4
IOL49B I/O 7 DQS3 Comp_of_IOL49A True none L4
IOL4A I/O 7 DQS0 True_of_IOL4B True x16 U6
IOL4B I/O 7 DQS0 Comp_of_IOL4A True none U5
IOL51A I/O 7 DQ3 True_of_IOL51B True x16 K3

© 2023 GOWINSEMI UG982-1.0E 12(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOL51B I/O 7 DQ3 Comp_of_IOL51A True none J3
IOL53A I/O 7 DQ3 True_of_IOL53B True x16 M7
IOL53B I/O 7 DQ3 Comp_of_IOL53A True none L7
IOL55A I/O 7 none none x16 N8
IOL56A I/O 6 DQ4 True_of_IOL56B True x16 G2
IOL56B I/O 6 DQ4 Comp_of_IOL56A True none G1
IOL58A I/O 6 DQ4 True_of_IOL58B True x16 F2
IOL58B I/O 6 DQ4 Comp_of_IOL58A True none E2
IOL60A I/O 6 DQ4 True_of_IOL60B True x16 C2
IOL60B/VREF I/O 6 DQ4 VREF Comp_of_IOL60A True none B2
IOL62A I/O 6 DQ4 True_of_IOL62B True x16 E1
IOL62B I/O 6 DQ4 Comp_of_IOL62A True none D1
IOL65A I/O 6 DQS4 True_of_IOL65B True x16 C1
IOL65B I/O 6 DQS4 Comp_of_IOL65A True none B1
IOL67A I/O 6 DQ4 True_of_IOL67B True x16 A3
IOL67B I/O 6 DQ4 Comp_of_IOL67A True none A2
IOL69A I/O 6 DQS5 True_of_IOL69B True x16 J4
IOL69B I/O 6 DQS5 Comp_of_IOL69A True none H4
IOL6A I/O 7 DQ0 True_of_IOL6B True x16 T5
IOL6B I/O 7 DQ0 Comp_of_IOL6A True none R5
IOL71A I/O 6 DQ5 True_of_IOL71B True x16 K7
IOL71B I/O 6 DQ5 Comp_of_IOL71A True none K6
IOL73A I/O 6 none none x16 H3
IOL74A I/O 6 DQ5 True_of_IOL74B True x16 J6
IOL74B I/O 6 DQ5 Comp_of_IOL74A True none J5
IOL76A I/O 6 DQ5 True_of_IOL76B True x16 L8
IOL76B I/O 6 DQ5 Comp_of_IOL76A True none K8
IOL78A/SGCLKT_8/LPLL2_T SGCLKT_8/LPLL2_T_in0/
I/O 6 DQ5 True_of_IOL78B True x16 G4
_in0/LPLL3_T_in0 LPLL3_T_in0
IOL78B/SGCLKC_8/LPLL2_ SGCLKC_8/LPLL2_C_in0
I/O 6 DQ5 Comp_of_IOL78A True none F4
C_in0/LPLL3_C_in0 /LPLL3_C_in0

© 2023 GOWINSEMI UG982-1.0E 13(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOL80A/MGCLKT_8/LPLL2_ MGCLKT_8/LPLL2_T_in1
I/O 6 DQ5 True_of_IOL80B True x16 G5
T_in1/LPLL3_T_in1 /LPLL3_T_in1
IOL80B/MGCLKC_8/LPLL2_ MGCLKC_8/LPLL2_C_in1
I/O 6 DQ5 Comp_of_IOL80A True none F5
C_in1/LPLL3_C_in1 /LPLL3_C_in1
IOL83A/MGCLKT_9/LPLL2_ MGCLKT_9/LPLL2_T_fb1
I/O 6 DQ6 True_of_IOL83B True x16 E5
T_fb1/LPLL3_T_fb1 /LPLL3_T_fb1
IOL83B/MGCLKC_9/LPLL2_ MGCLKC_9/LPLL2_C_fb
I/O 6 DQ6 Comp_of_IOL83A True none D5
C_fb1/LPLL3_C_fb1 1/LPLL3_C_fb1
IOL85A/SGCLKT_9/LPLL2_T SGCLKT_9/LPLL2_T_fb0/
I/O 6 DQ6 True_of_IOL85B True x16 D4
_fb0/LPLL3_T_fb0 LPLL3_T_fb0
IOL85B/SGCLKC_9/LPLL2_ SGCLKC_9/LPLL2_C_fb0
I/O 6 DQ6 Comp_of_IOL85A True none C4
C_fb0/LPLL3_C_fb0 /LPLL3_C_fb0
IOL87A I/O 6 DQ6 True_of_IOL87B True x16 B4
IOL87B I/O 6 DQ6 Comp_of_IOL87A True none A4
IOL89A I/O 6 DQ6 True_of_IOL89B True x16 F3
IOL89B I/O 6 DQ6 Comp_of_IOL89A True none E3
IOL8A I/O 7 DQ0 True_of_IOL8B True x16 R7
IOL8B I/O 7 DQ0 Comp_of_IOL8A True none R6
IOL92A I/O 6 DQ6 True_of_IOL92B True x16 D3
IOL92B I/O 6 DQ6 Comp_of_IOL92A True none C3
IOL94A I/O 6 DQS6 True_of_IOL94B True x16 B5
IOL94B I/O 6 DQS6 Comp_of_IOL94A True none A5
IOL96A I/O 6 DQS7 True_of_IOL96B True x16 H7
IOL96B I/O 6 DQS7 Comp_of_IOL96A True none G7
IOL98A I/O 6 DQ7 True_of_IOL98B True x16 H6
IOL98B I/O 6 DQ7 Comp_of_IOL98A True none G6
IOR101A/D04 I/O 3 DQ16 D04 True_of_IOR101B True x16 N16
IOR101B/D05/SI I/O 3 DQ16 D05/SI Comp_of_IOR101A True none N17
IOR103A/PUDC_B I/O 3 DQS16 PUDC_B True_of_IOR103B True x16 P15
IOR103B/EMCCLK I/O 3 DQS16 EMCCLK Comp_of_IOR103A True none P16
IOR105A/D00/MOSI I/O 3 DQ16 D00/MOSI True_of_IOR105B True x16 R14

© 2023 GOWINSEMI UG982-1.0E 14(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR105B/D01/DIN I/O 3 DQ16 D01/DIN Comp_of_IOR105A True none R15
IOR107A/D02/ADCINCK1 I/O 3 DQ16 D02/ADCINCK1 True_of_IOR107B True x16 P14
IOR107B/D03 I/O 3 DQ16 D03 Comp_of_IOR107A True none N14
IOR109A I/O 3 none none x16 M19
IOR11A I/O 2 DQ23 True_of_IOR11B True x16 U14
IOR11B I/O 2 DQ23 Comp_of_IOR11A True none V14
IOR13A I/O 2 DQ23 True_of_IOR13B True x16 T14
IOR13B I/O 2 DQ23 Comp_of_IOR13A True none T15
IOR15A I/O 2 DQ22 True_of_IOR15B True x16 V19
IOR15B I/O 2 DQ22 Comp_of_IOR15A True none W19
IOR17A I/O 2 DQ22 True_of_IOR17B True x16 W20
IOR17B I/O 2 DQ22 Comp_of_IOR17A True none Y20
IOR1A I/O 2 none none x16 U17
IOR20A I/O 2 DQS22 True_of_IOR20B True x16 T20
IOR20B I/O 2 DQS22 Comp_of_IOR20A True none U20
IOR22A I/O 2 DQ22 True_of_IOR22B True x16 T19
IOR22B I/O 2 DQ22 Comp_of_IOR22A True none U19
IOR24A/SGCLKT_1/RPLL0_ SGCLKT_1/RPLL0_T_fb0
I/O 2 DQ22 True_of_IOR24B True x16 W21
T_fb0/RPLL1_T_fb0 /RPLL1_T_fb0
IOR24B/SGCLKC_1/RPLL0_ SGCLKC_1/RPLL0_C_fb
I/O 2 DQ22 Comp_of_IOR24A True none Y21
C_fb0/RPLL1_C_fb0 0/RPLL1_C_fb0
IOR26A/MGCLKT_1/RPLL0_ MGCLKT_1/RPLL0_T_fb1
I/O 2 DQ22 True_of_IOR26B True x16 U21
T_fb1/RPLL1_T_fb1 /RPLL1_T_fb1
IOR26B/MGCLKC_1/RPLL0_ MGCLKC_1/RPLL0_C_fb
I/O 2 DQ22 Comp_of_IOR26A True none V21
C_fb1/RPLL1_C_fb1 1/RPLL1_C_fb1
IOR29A/SGCLKT_0/RPLL0_ SGCLKT_0/RPLL0_T_in0
I/O 2 DQ21 True_of_IOR29B True x16 Y22
T_in0/RPLL1_T_in0 /RPLL1_T_in0
IOR29B/SGCLKC_0/RPLL0_ SGCLKC_0/RPLL0_C_in0
I/O 2 DQ21 Comp_of_IOR29A True none Y23
C_in0/RPLL1_C_in0 /RPLL1_C_in0
IOR2A I/O 2 DQ23 True_of_IOR2B True x16 V16
IOR2B I/O 2 DQ23 Comp_of_IOR2A True none V17

© 2023 GOWINSEMI UG982-1.0E 15(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR31A/MGCLKT_0/RPLL0_ MGCLKT_0/RPLL0_T_in1
I/O 2 DQ21 True_of_IOR31B True x16 U22
T_in1/RPLL1_T_in1 /RPLL1_T_in1
IOR31B/MGCLKC_0/RPLL0_ MGCLKC_0/RPLL0_C_in
I/O 2 DQ21 Comp_of_IOR31A True none V22
C_in1/RPLL1_C_in1 1/RPLL1_C_in1
IOR33A/FBTEST_R0 I/O 2 DQ21 FBTEST_R0 True_of_IOR33B True x16 AA22
IOR33B/CLKTEST_R0 I/O 2 DQ21 CLKTEST_R0 Comp_of_IOR33A True none AA23
IOR35A I/O 2 DQS21 True_of_IOR35B True x16 AB24
IOR35B I/O 2 DQS21 Comp_of_IOR35A True none AC24
IOR38A I/O 2 DQ21 True_of_IOR38B True x16 V23
IOR38B I/O 2 DQ21 Comp_of_IOR38A True none W23
IOR40A I/O 2 DQ21 True_of_IOR40B True x16 AA24
IOR40B I/O 2 DQ21 Comp_of_IOR40A True none AB25
IOR42A I/O 2 DQ20 True_of_IOR42B True x16 Y25
IOR42B I/O 2 DQ20 Comp_of_IOR42A True none AA25
IOR44A I/O 2 DQS20 True_of_IOR44B True x16 AB26
IOR44B I/O 2 DQS20 Comp_of_IOR44A True none AC26
IOR47A I/O 2 DQ20 True_of_IOR47B True x16 V24
IOR47B/VREF I/O 2 DQ20 VREF Comp_of_IOR47A True none W24
IOR49A I/O 2 DQ20 True_of_IOR49B True x16 W25
IOR49B I/O 2 DQ20 Comp_of_IOR49A True none Y26
IOR4A I/O 2 DQ23 True_of_IOR4B True x16 V18
IOR4B/VREF I/O 2 DQ23 VREF Comp_of_IOR4A True none W18
IOR51A I/O 2 DQ20 True_of_IOR51B True x16 V26
IOR51B I/O 2 DQ20 Comp_of_IOR51A True none W26
IOR53A I/O 2 DQ20 True_of_IOR53B True x16 U25
IOR53B I/O 2 DQ20 Comp_of_IOR53A True none U26
IOR55A I/O 2 none none x16 U24
IOR56A/D19 I/O 3 DQ19 D19 True_of_IOR56B True x16 T22
IOR56B/D18 I/O 3 DQ19 D18 Comp_of_IOR56A True none R22
IOR58A/CLKHOLD_N I/O 3 DQS19 CLKHOLD_N True_of_IOR58B True x16 T24
IOR58B/D22 I/O 3 DQS19 D22 Comp_of_IOR58A True none T25
IOR60A/D26 I/O 3 DQ19 D26 True_of_IOR60B True x16 R25

© 2023 GOWINSEMI UG982-1.0E 16(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR60B/D25/VREF I/O 3 DQ19 D25/VREF Comp_of_IOR60A True none P25
IOR62A/D17 I/O 3 DQ19 D17 True_of_IOR62B True x16 T23
IOR62B/D16 I/O 3 DQ19 D16 Comp_of_IOR62A True none R23
IOR65A/D21 I/O 3 DQ19 D21 True_of_IOR65B True x16 R26
IOR65B/D20 I/O 3 DQ19 D20 Comp_of_IOR65A True none P26
IOR67A/D24 I/O 3 DQ19 D24 True_of_IOR67B True x16 N26
IOR67B/D23 I/O 3 DQ19 D23 Comp_of_IOR67A True none M26
IOR69A/D28 I/O 3 DQ18 D28 True_of_IOR69B True x16 R20
IOR69B/D27 I/O 3 DQ18 D27 Comp_of_IOR69A True none R21
IOR6A I/O 2 DQ23 True_of_IOR6B True x16 U15
IOR6B I/O 2 DQ23 Comp_of_IOR6A True none U16
IOR71A/CSI_B I/O 3 DQ18 CSI_B True_of_IOR71B True x16 P19
IOR71B/D31 I/O 3 DQ18 D31 Comp_of_IOR71A True none N19
IOR73A I/O 3 none none x16 R18
IOR74A/D30 I/O 3 DQ18 D30 True_of_IOR74B True x16 P23
IOR74B/D29 I/O 3 DQ18 D29 Comp_of_IOR74A True none P24
IOR76A/RDWR I/O 3 DQS18 RDWR True_of_IOR76B True x16 N23
IOR76B/DOUT_CSO_B I/O 3 DQS18 DOUT_CSO_B Comp_of_IOR76A True none N24
IOR78A/SGCLKT_3/RPLL2_ SGCLKT_3/RPLL2_T_fb0
I/O 3 DQ18 True_of_IOR78B True x16 P20
T_fb0/RPLL3_T_fb0 /RPLL3_T_fb0
IOR78B/SGCLKC_3/RPLL2_ SGCLKC_3/RPLL2_C_fb
I/O 3 DQ18 Comp_of_IOR78A True none P21
C_fb0/RPLL3_C_fb0 0/RPLL3_C_fb0
IOR80A/MGCLKT_3/RPLL2_ MGCLKT_3/RPLL2_T_fb1
I/O 3 DQ18 True_of_IOR80B True x16 N21
T_fb1/RPLL3_T_fb1 /RPLL3_T_fb1
IOR80B/MGCLKC_3/RPLL2_ MGCLKC_3/RPLL2_C_fb
I/O 3 DQ18 Comp_of_IOR80A True none N22
C_fb1/RPLL3_C_fb1 1/RPLL3_C_fb1
IOR83A/MGCLKT_2/RPLL2_ MGCLKT_2/RPLL2_T_in1
I/O 3 DQ17 True_of_IOR83B True x16 M21
T_in1/RPLL3_T_in1 /RPLL3_T_in1
IOR83B/MGCLKC_2/RPLL2_ MGCLKC_2/RPLL2_C_in
I/O 3 DQ17 Comp_of_IOR83A True none M22
C_in1/RPLL3_C_in1 1/RPLL3_C_in1
IOR85A/MGCLKC_2/RPLL2_ SGCLKT_2/RPLL2_T_in0
I/O 3 DQ17 True_of_IOR85B True x16 L22
T_in0/RPLL3_T_in0 /RPLL3_T_in0

© 2023 GOWINSEMI UG982-1.0E 17(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR85B/SGCLKC_2/RPLL2_ SGCLKC_2/RPLL2_C_in0
I/O 3 DQ17 Comp_of_IOR85A True none L23
C_in0/RPLL3_C_in0 /RPLL3_C_in0
IOR87A/D14 I/O 3 DQ17 D14 True_of_IOR87B True x16 M24
IOR87B/D15 I/O 3 DQ17 D15 Comp_of_IOR87A True none M25
IOR89A/SSPI_CS_N I/O 3 DQS17 SSPI_CS_N True_of_IOR89B True x16 L24
IOR89B/D13 I/O 3 DQS17 D13 Comp_of_IOR89A True none L25
IOR8A I/O 2 DQS23 True_of_IOR8B True x16 T17
IOR8B I/O 2 DQS23 Comp_of_IOR8A True none T18
IOR92A/D11 I/O 3 DQ17 D11 True_of_IOR92B True x16 M20
IOR92B/D12 I/O 3 DQ17 D12 Comp_of_IOR92A True none L20
IOR94A/D09 I/O 3 DQ17 D09 True_of_IOR94B True x16 K25
IOR94B/D10 I/O 3 DQ17 D10 Comp_of_IOR94A True none K26
IOR96A/MCS_N I/O 3 DQ16 MCS_N True_of_IOR96B True x16 P18
IOR96B/D08/VREF/SO I/O 3 DQ16 D08/VREF/SO Comp_of_IOR96A True none N18
IOR98A/D06/SSPI_CLK I/O 3 DQ16 D06/SSPI_CLK True_of_IOR98B True x16 R16
IOR98B/D07/SSPI_WPN I/O 3 DQ16 D07/SSPI_WPN Comp_of_IOR98A True none R17
ADCTN/ADCTN DIO 10 none ADCTN none none R11
ADCTP/ADCTP DIO 10 none ADCTP none none R12
ADCVN/ADCVN DIO 10 none ADCVN none none P11
ADCVP/ADCVP DIO 10 none ADCVP none none N12
ATEST_O DIO Q0/Q1 none none none AF15
M0_CKN DIO MIPI none none none AA3
M0_CKP DIO MIPI none none none Y3
M0_D0N DIO MIPI none none none W1
M0_D0P DIO MIPI none none none V1
M0_D1N DIO MIPI none none none AA2
M0_D1P DIO MIPI none none none Y2
M0_D2N DIO MIPI none none none W3
M0_D2P DIO MIPI none none none V3
M0_D3N DIO MIPI none none none W4
M0_D3P DIO MIPI none none none V4
M1_CKN DIO MIPI none none none AF2
M1_CKP DIO MIPI none none none AE2

© 2023 GOWINSEMI UG982-1.0E 18(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
M1_D0N DIO MIPI none none none AC1
M1_D0P DIO MIPI none none none AB1
M1_D1N DIO MIPI none none none AE1
M1_D1P DIO MIPI none none none AD1
M1_D2N DIO MIPI none none none AF3
M1_D2P DIO MIPI none none none AE3
M1_D3N DIO MIPI none none none AF5
M1_D3P DIO MIPI none none none AE5
Q0_lN0_RXM_I DIO Q0 none none none C12
Q0_lN0_RXP_I DIO Q0 none none none D12
Q0_lN0_TXM_O DIO Q0 none none none C10
Q0_lN0_TXP_O DIO Q0 none none none D10
Q0_lN1_RXM_I DIO Q0 none none none C14
Q0_lN1_RXP_I DIO Q0 none none none D14
Q0_lN1_TXM_O DIO Q0 none none none C8
Q0_lN1_TXP_O DIO Q0 none none none D8
Q0_lN2_RXM_I DIO Q0 none none none A13
Q0_lN2_RXP_I DIO Q0 none none none B13
Q0_lN2_TXM_O DIO Q0 none none none A9
Q0_lN2_TXP_O DIO Q0 none none none B9
Q0_lN3_RXM_I DIO Q0 none none none A11
Q0_lN3_RXP_I DIO Q0 none none none B11
Q0_lN3_TXM_O DIO Q0 none none none A7
Q0_lN3_TXP_O DIO Q0 none none none B7
Q0_REFCLKM_0 DIO Q0 none none none E11
Q0_REFCLKM_1 DIO Q0 none none none E13
Q0_REFCLKP_0 DIO Q0 none none none F11
Q0_REFCLKP_1 DIO Q0 none none none F13
Q1_lN0_RXM_I DIO Q1 none none none AD14
Q1_lN0_RXP_I DIO Q1 none none none AC14
Q1_lN0_TXM_O DIO Q1 none none none AD8
Q1_lN0_TXP_O DIO Q1 none none none AC8
Q1_lN1_RXM_I DIO Q1 none none none AD12

© 2023 GOWINSEMI UG982-1.0E 19(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
Q1_lN1_RXP_I DIO Q1 none none none AC12
Q1_lN1_TXM_O DIO Q1 none none none AD10
Q1_lN1_TXP_O DIO Q1 none none none AC10
Q1_lN2_RXM_I DIO Q1 none none none AF13
Q1_lN2_RXP_I DIO Q1 none none none AE13
Q1_lN2_TXM_O DIO Q1 none none none AF9
Q1_lN2_TXP_O DIO Q1 none none none AE9
Q1_lN3_RXM_I DIO Q1 none none none AF11
Q1_lN3_RXP_I DIO Q1 none none none AE11
Q1_lN3_TXM_O DIO Q1 none none none AF7
Q1_lN3_TXP_O DIO Q1 none none none AE7
Q1_REFCLKM_0 DIO Q1 none none none AB11
Q1_REFCLKM_1 DIO Q1 none none none AB13
Q1_REFCLKP_0 DIO Q1 none none none AA11
Q1_REFCLKP_1 DIO Q1 none none none AA13
M0_VDDA/M0_VDDD/M1_V
Power N/A N13
DDA/M1_VDDD
M0_VDDA/M0_VDDD/M1_V
Power N/A W13
DDA/M1_VDDD
M0_VDDA/M0_VDDD/M1_V
Power N/A U13
DDA/M1_VDDD
M0_VDDA/M0_VDDD/M1_V
Power N/A R13
DDA/M1_VDDD
M0_VDDX/M1_VDDX Power N/A M12
Q0_VDDA/Q0_VDDD_IN0/Q
0_VDDD_IN1/Q0_VDDD_IN
2/Q0_VDDD_IN3/Q0_VDDT
Power N/A D11
C/Q0_VDDTC_In0/Q0_VDDT
C_IN1/Q0_VDDTC_IN2/Q0_
VDDTC_IN3

© 2023 GOWINSEMI UG982-1.0E 20(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
Q0_VDDA/Q0_VDDD_IN0/Q
0_VDDD_IN1/Q0_VDDD_IN
2/Q0_VDDD_IN3/Q0_VDDT
Power N/A D9
C/Q0_VDDTC_IN0/Q0_VDD
TC_IN1/Q0_VDDTC_IN2/Q0
_VDDTC_IN3
Q0_VDDA/Q0_VDDD_IN0/Q
0_VDDD_IN1/Q0_VDDD_IN
2/Q0_VDDD_IN3/Q0_VDDT
Power N/A D13
C/Q0_VDDTC_IN0/Q0_VDD
TC_IN1/Q0_VDDTC_IN2/Q0
_VDDTC_IN3
Q0_VDDHA Power N/A U9
Q0_VDDT_IN0/Q0_VDDT_IN
1/Q0_VDDT_IN2/Q0_VDDT_ Power N/A F12
IN3
Q0_VDDT_IN0/Q0_VDDT_IN
1/Q0_VDDT_IN2/Q0_VDDT_ Power N/A F10
IN3
Q1_VDDA/Q1_VDDD_IN0/Q
1_VDDD_IN1/Q1_VDDD_IN
2/Q1_VDDD_IN3/Q1_VDDT
Power N/A AC9
C/Q1_VDDTC_IN0/Q1_VDD
TC_IN1/Q1_VDDTC_IN2/Q1
_VDDTC_IN3
Q1_VDDA/Q1_VDDD_IN0/Q
1_VDDD_IN1/Q1_VDDD_IN
2/Q1_VDDD_IN3/Q1_VDDT
Power N/A AC13
C/Q1_VDDTC_IN0/Q1_VDD
TC_IN1/Q1_VDDTC_IN2/Q1
_VDDTC_IN3

© 2023 GOWINSEMI UG982-1.0E 21(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
Q1_VDDA/Q1_VDDD_IN0/Q
1_VDDD_IN1/Q1_VDDD_IN
2/Q1_VDDD_IN3/Q1_VDDT
Power N/A AC11
C/Q1_VDDTC_IN0/Q1_VDD
TC_IN1/Q1_VDDTC_IN2/Q1
_VDDTC_IN3
Q1_VDDHA Power N/A R9
Q1_VDDT_IN0/Q1_VDDT_IN
1/Q1_VDDT_IN2/Q1_VDDT_ Power N/A AA10
IN3
Q1_VDDT_IN0/Q1_VDDT_IN
1/Q1_VDDT_IN2/Q1_VDDT_ Power N/A AA12
IN3
VCC/VCCC Power N/A J13
VCC/VCCC Power N/A V12
VCC/VCCC Power N/A U11
VCC/VCCC Power N/A T12
VCC/VCCC Power N/A V10
VCC/VCCC Power N/A K10
VCC/VCCC Power N/A L13
VCC/VCCC Power N/A K12
VCC/VCCC Power N/A M10
VCC/VCCC Power N/A L11
VCC/VCCC Power N/A T10
VCC/VCCC Power N/A P10
VCC/VCCC Power N/A J11
VCC_REG Power N/A B14
VCC_REG Power N/A B8
VCC_REG Power N/A B12
VCC_REG Power N/A C7
VCC_REG Power N/A C15
VCC_REG Power N/A B10
VCCO10 Power N/A W11

© 2023 GOWINSEMI UG982-1.0E 22(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
VCCO10 Power N/A Y14
VCCX Power N/A J9
VCCX Power N/A N9
VCCX Power N/A L9
VCCO2 Power N/A Y24
VCCO2 Power N/A U23
VCCO2 Power N/A AC25
VCCO2 Power N/A T16
VCCO2 Power N/A T26
VCCO2 Power N/A V20
VCCO3 Power N/A L21
VCCO3 Power N/A K24
VCCO3 Power N/A R19
VCCO3 Power N/A N15
VCCO3 Power N/A N25
VCCO3 Power N/A P22
VCCO4 Power N/A M18
VCCO4 Power N/A H20
VCCO4 Power N/A G23
VCCO4 Power N/A J17
VCCO4 Power N/A F26
VCCO4 Power N/A K14
VCCO5 Power N/A C25
VCCO5 Power N/A B18
VCCO5 Power N/A D22
VCCO5 Power N/A E19
VCCO5 Power N/A F16
VCCO5 Power N/A A21
VCCO6 Power N/A J7
VCCO6 Power N/A D2
VCCO6 Power N/A C5
VCCO6 Power N/A A1
VCCO6 Power N/A F6

© 2023 GOWINSEMI UG982-1.0E 23(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
VCCO6 Power N/A G3
VCCO7 Power N/A L1
VCCO7 Power N/A N5
VCCO7 Power N/A M8
VCCO7 Power N/A K4
VCCO7 Power N/A T6
VCCO7 Power N/A P2
VSS Ground N/A M11
VSS Ground N/A AE15
VSS Ground N/A B15
VSS Ground N/A A10
VSS Ground N/A A12
VSS Ground N/A A14
VSS Ground N/A A16
VSS Ground N/A A26
VSS Ground N/A A6
VSS Ground N/A A8
VSS Ground N/A AA14
VSS Ground N/A AA16
VSS Ground N/A AA26
VSS Ground N/A AA6
VSS Ground N/A AB10
VSS Ground N/A AB12
VSS Ground N/A AB14
VSS Ground N/A AB23
VSS Ground N/A AB3
VSS Ground N/A AA9
VSS Ground N/A AB8
VSS Ground N/A AC15
VSS Ground N/A AC20
VSS Ground N/A AC7
VSS Ground N/A AD11
VSS Ground N/A AD13

© 2023 GOWINSEMI UG982-1.0E 24(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
VSS Ground N/A AD6
VSS Ground N/A AD9
VSS Ground N/A AD16
VSS Ground N/A AE24
VSS Ground N/A AE4
VSS Ground N/A AE6
VSS Ground N/A AF1
VSS Ground N/A AF10
VSS Ground N/A AF12
VSS Ground N/A AF14
VSS Ground N/A AF16
VSS Ground N/A AF21
VSS Ground N/A AF6
VSS Ground N/A AF8
VSS Ground N/A B16
VSS Ground N/A B23
VSS Ground N/A B3
VSS Ground N/A B6
VSS Ground N/A C11
VSS Ground N/A C13
VSS Ground N/A C16
VSS Ground N/A C20
VSS Ground N/A C6
VSS Ground N/A C9
VSS Ground N/A D15
VSS Ground N/A D17
VSS Ground N/A D7
VSS Ground N/A E10
VSS Ground N/A E12
VSS Ground N/A E14
VSS Ground N/A E24
VSS Ground N/A E4
VSS Ground N/A E7

© 2023 GOWINSEMI UG982-1.0E 25(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
VSS Ground N/A E8
VSS Ground N/A E9
VSS Ground N/A F1
VSS Ground N/A F14
VSS Ground N/A F21
VSS Ground N/A F9
VSS Ground N/A G10
VSS Ground N/A G11
VSS Ground N/A AB9
VSS Ground N/A G13
VSS Ground N/A Y12
VSS Ground N/A G18
VSS Ground N/A G12
VSS Ground N/A H25
VSS Ground N/A H5
VSS Ground N/A J12
VSS Ground N/A J2
VSS Ground N/A J22
VSS Ground N/A K11
VSS Ground N/A K13
VSS Ground N/A K19
VSS Ground N/A K9
VSS Ground N/A L10
VSS Ground N/A L12
VSS Ground N/A L16
VSS Ground N/A L26
VSS Ground N/A L6
VSS Ground N/A M13
VSS Ground N/A M23
VSS Ground N/A M3
VSS Ground N/A M9
VSS Ground N/A N10
VSS Ground N/A N20

© 2023 GOWINSEMI UG982-1.0E 26(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
VSS Ground N/A P13
VSS Ground N/A P17
VSS Ground N/A P7
VSS Ground N/A P9
VSS Ground N/A R10
VSS Ground N/A R24
VSS Ground N/A R4
VSS Ground N/A T1
VSS Ground N/A T11
VSS Ground N/A T13
VSS Ground N/A T21
VSS Ground N/A T9
VSS Ground N/A U10
VSS Ground N/A U12
VSS Ground N/A U18
VSS Ground N/A U8
VSS Ground N/A V15
VSS Ground N/A V25
VSS Ground N/A V5
VSS Ground N/A E15
VSS Ground N/A W12
VSS Ground N/A W2
VSS Ground N/A W22
VSS Ground N/A Y11
VSS Ground N/A Y10
VSS Ground N/A Y13
VSS Ground N/A Y19
VSS Ground N/A V13
NC N/A N/A AD15
NC N/A N/A AD7
NC N/A N/A AE10
NC N/A N/A AE12
NC N/A N/A AE14

© 2023 GOWINSEMI UG982-1.0E 27(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
NC N/A N/A AE8
NC N/A N/A AA1
NC N/A N/A AC5
NC N/A N/A AD2
NC N/A N/A U3
NC N/A N/A W7
NC N/A N/A Y4
NC N/A N/A G14
NC N/A N/A P12
NC N/A N/A N11
NC N/A N/A AA21
NC N/A N/A AB18
NC N/A N/A AD22
NC N/A N/A AE19
NC N/A N/A AF26
NC N/A N/A W17
NC N/A N/A AA17
NC N/A N/A AA18
NC N/A N/A AA19
NC N/A N/A AA20
NC N/A N/A AA4
NC N/A N/A AA7
NC N/A N/A AB16
NC N/A N/A AB17
NC N/A N/A AB19
NC N/A N/A AB2
NC N/A N/A AB20
NC N/A N/A AB21
NC N/A N/A AB22
NC N/A N/A AB5
NC N/A N/A AB6
NC N/A N/A AC16
NC N/A N/A AC17

© 2023 GOWINSEMI UG982-1.0E 28(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
NC N/A N/A AC18
NC N/A N/A AC19
NC N/A N/A AC2
NC N/A N/A AC21
NC N/A N/A AC22
NC N/A N/A AC23
NC N/A N/A AC3
NC N/A N/A AC6
NC N/A N/A AD17
NC N/A N/A AD18
NC N/A N/A AD19
NC N/A N/A AD20
NC N/A N/A AD21
NC N/A N/A AD23
NC N/A N/A AD24
NC N/A N/A AD25
NC N/A N/A AD26
NC N/A N/A AD3
NC N/A N/A AD4
NC N/A N/A AD5
NC N/A N/A AE17
NC N/A N/A AE18
NC N/A N/A AE20
NC N/A N/A AE21
NC N/A N/A AE22
NC N/A N/A AE23
NC N/A N/A AE25
NC N/A N/A AE26
NC N/A N/A AA5
NC N/A N/A AF17
NC N/A N/A AF18
NC N/A N/A AF19
NC N/A N/A AF20

© 2023 GOWINSEMI UG982-1.0E 29(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Pin List

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
NC N/A N/A AF22
NC N/A N/A AF23
NC N/A N/A AF24
NC N/A N/A AF25
NC N/A N/A AF4
NC N/A N/A V2
NC N/A N/A AB4
NC N/A N/A A15
NC N/A N/A W15
NC N/A N/A W16
NC N/A N/A AC4
NC N/A N/A Y1
NC N/A N/A Y15
NC N/A N/A Y16
NC N/A N/A Y17
NC N/A N/A Y18
NC N/A N/A AA15
NC N/A N/A V9
NC N/A N/A W14
NC N/A N/A V6
NC N/A N/A Y5
NC N/A N/A W5
NC N/A N/A Y8
NC N/A N/A U7
NC N/A N/A Y6
NC N/A N/A W6
NC N/A N/A Y7
NC N/A N/A AA8
NC N/A N/A V7
NC N/A N/A W8
NC N/A N/A V8

© 2023 GOWINSEMI UG982-1.0E 30(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
BANK10 True LVDS Pair
IOB169A/TDO I/O 10 none TDO True_of_IOB169B True none J10
IOB169B/TMS I/O 10 none TMS Comp_of_IOB169A True none H11
IOB171A/READY I/O 10 none READY True_of_IOB171B True none V11
IOB171B/DONE I/O 10 none DONE Comp_of_IOB171A True none W10
IOB173A/TCK I/O 10 none TCK True_of_IOB173B True none H12
IOB173B/TDI I/O 10 none TDI Comp_of_IOB173A True none H10
IOB175A/MODE0 I/O 10 none MODE0 True_of_IOB175B True none AB7
IOB175B/CCLK I/O 10 none CCLK Comp_of_IOB175A True none H13
IOB177A/MODE1 I/O 10 none MODE1 True_of_IOB177B True none Y9
IOB177B/MODE2 I/O 10 none MODE2 Comp_of_IOB177A True none W9
IOB179A/CFGBVS I/O 10 none CFGBVS True_of_IOB179B True none AB15
IOB179B/RECONFIG_N I/O 10 none RECONFIG_N Comp_of_IOB179A True none AE16
BANK7 True LVDS Pair
IOL11A I/O 7 DQ0 True_of_IOL11B True x16 P6
IOL11B/VREF I/O 7 DQ0 VREF Comp_of_IOL11A True none P5
IOL13A I/O 7 DQ0 True_of_IOL13B True x16 R8
IOL13B I/O 7 DQ0 Comp_of_IOL13A True none P8
IOL15A I/O 7 DQ1 True_of_IOL15B True x16 U2
IOL15B I/O 7 DQ1 Comp_of_IOL15A True none U1
IOL17A I/O 7 DQ1 True_of_IOL17B True x16 T2
IOL17B I/O 7 DQ1 Comp_of_IOL17A True none R2
IOL20A I/O 7 DQ1 True_of_IOL20B True x16 T4
IOL20B I/O 7 DQ1 Comp_of_IOL20A True none T3
IOL22A I/O 7 DQS1 True_of_IOL22B True x16 R1
IOL22B I/O 7 DQS1 Comp_of_IOL22A True none P1

© 2023 GOWINSEMI UG982-1.0E 31(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOL24A/MGCLKT_11/LPLL MGCLKT_11/LPLL0_T_in1/
I/O 7 DQ1 True_of_IOL24B True x16 R3
0_T_in1/LPLL1_T_in1 LPLL1_T_in1
IOL24B/MGCLKC_11/LPL MGCLKC_11/LPLL0_C_in1/
I/O 7 DQ1 Comp_of_IOL24A True none P3
L0_C_in1/LPLL1_C_in1 LPLL1_C_in1
IOL26A/SGCLKT_11/LPLL SGCLKT_11/LPLL0_T_in0/
I/O 7 DQ1 True_of_IOL26B True x16 P4
0_T_in0/LPLL1_T_in0 LPLL1_T_in0
IOL26B/SGCLKC_11/LPLL SGCLKC_11/LPLL0_C_in0/
I/O 7 DQ1 Comp_of_IOL26A True none N4
0_C_in0/LPLL1_C_in0 LPLL1_C_in0
IOL29A/MGCLKT_10/LPLL MGCLKT_10/LPLL0_T_fb1/
I/O 7 DQ2 True_of_IOL29B True x16 N3
0_T_fb1/LPLL1_T_fb1 LPLL1_T_fb1
IOL29B/MGCLKC_10/LPL MGCLKC_10/LPLL0_C_fb1/
I/O 7 DQ2 Comp_of_IOL29A True none N2
L0_C_fb1/LPLL1_C_fb1 LPLL1_C_fb1
IOL2A/ADCINCK0 I/O 7 DQ0 ADCINCK0 True_of_IOL2B True x16 T8
IOL2B I/O 7 DQ0 Comp_of_IOL2A True none T7
IOL31A/SGCLKT_10/LPLL SGCLKT_10/LPLL0_T_fb0/
I/O 7 DQ2 True_of_IOL31B True x16 M2
0_T_fb0/LPLL1_T_fb0 LPLL1_T_fb0
IOL31B/SGCLKC_10/LPLL SGCLKC_10/LPLL0_C_fb0/
I/O 7 DQ2 Comp_of_IOL31A True none L2
0_C_fb0/LPLL1_C_fb0 LPLL1_C_fb0
IOL33A/FBTEST_L0 I/O 7 DQ2 FBTEST_L0 True_of_IOL33B True x16 K1
IOL33B/CLKTEST_L0 I/O 7 DQ2 CLKTEST_L0 Comp_of_IOL33A True none J1
IOL35A I/O 7 DQS2 True_of_IOL35B True x16 N1
IOL35B I/O 7 DQS2 Comp_of_IOL35A True none M1
IOL38A I/O 7 DQ2 True_of_IOL38B True x16 L3
IOL38B I/O 7 DQ2 Comp_of_IOL38A True none K2
IOL40A I/O 7 DQ2 True_of_IOL40B True x16 H2
IOL40B I/O 7 DQ2 Comp_of_IOL40A True none H1
IOL42A I/O 7 DQ3 True_of_IOL42B True x16 N7
IOL42B I/O 7 DQ3 Comp_of_IOL42A True none N6
IOL44A I/O 7 DQ3 True_of_IOL44B True x16 M6

© 2023 GOWINSEMI UG982-1.0E 32(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOL44B/VREF I/O 7 DQ3 VREF Comp_of_IOL44A True none M5
IOL47A I/O 7 DQ3 True_of_IOL47B True x16 L5
IOL47B I/O 7 DQ3 Comp_of_IOL47A True none K5
IOL49A I/O 7 DQS3 True_of_IOL49B True x16 M4
IOL49B I/O 7 DQS3 Comp_of_IOL49A True none L4
IOL4A I/O 7 DQS0 True_of_IOL4B True x16 U6
IOL4B I/O 7 DQS0 Comp_of_IOL4A True none U5
IOL51A I/O 7 DQ3 True_of_IOL51B True x16 K3
IOL51B I/O 7 DQ3 Comp_of_IOL51A True none J3
IOL53A I/O 7 DQ3 True_of_IOL53B True x16 M7
IOL53B I/O 7 DQ3 Comp_of_IOL53A True none L7
IOL6A I/O 7 DQ0 True_of_IOL6B True x16 T5
IOL6B I/O 7 DQ0 Comp_of_IOL6A True none R5
IOL8A I/O 7 DQ0 True_of_IOL8B True x16 R7
IOL8B I/O 7 DQ0 Comp_of_IOL8A True none R6
BANK6 True LVDS Pair
IOL101A I/O 6 DQ7 True_of_IOL101B True x16 E6
IOL101B I/O 6 DQ7 Comp_of_IOL101A True none D6
IOL103A I/O 6 DQ7 True_of_IOL103B True x16 H8
IOL103B I/O 6 DQ7 Comp_of_IOL103A True none G8
IOL105A I/O 6 DQ7 True_of_IOL105B True x16 F8
IOL105B I/O 6 DQ7 Comp_of_IOL105A True none F7
IOL107A/MCKTEST I/O 6 DQ7 MCKTEST True_of_IOL107B True x16 H9
IOL107B/VREF I/O 6 DQ7 VREF Comp_of_IOL107A True none G9
IOL56A I/O 6 DQ4 True_of_IOL56B True x16 G2
IOL56B I/O 6 DQ4 Comp_of_IOL56A True none G1
IOL58A I/O 6 DQ4 True_of_IOL58B True x16 F2

© 2023 GOWINSEMI UG982-1.0E 33(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOL58B I/O 6 DQ4 Comp_of_IOL58A True none E2
IOL60A I/O 6 DQ4 True_of_IOL60B True x16 C2
IOL60B/VREF I/O 6 DQ4 VREF Comp_of_IOL60A True none B2
IOL62A I/O 6 DQ4 True_of_IOL62B True x16 E1
IOL62B I/O 6 DQ4 Comp_of_IOL62A True none D1
IOL65A I/O 6 DQS4 True_of_IOL65B True x16 C1
IOL65B I/O 6 DQS4 Comp_of_IOL65A True none B1
IOL67A I/O 6 DQ4 True_of_IOL67B True x16 A3
IOL67B I/O 6 DQ4 Comp_of_IOL67A True none A2
IOL69A I/O 6 DQS5 True_of_IOL69B True x16 J4
IOL69B I/O 6 DQS5 Comp_of_IOL69A True none H4
IOL71A I/O 6 DQ5 True_of_IOL71B True x16 K7
IOL71B I/O 6 DQ5 Comp_of_IOL71A True none K6
IOL74A I/O 6 DQ5 True_of_IOL74B True x16 J6
IOL74B I/O 6 DQ5 Comp_of_IOL74A True none J5
IOL76A I/O 6 DQ5 True_of_IOL76B True x16 L8
IOL76B I/O 6 DQ5 Comp_of_IOL76A True none K8
IOL78A/SGCLKT_8/LPLL2 SGCLKT_8/LPLL2_T_in0/L
I/O 6 DQ5 True_of_IOL78B True x16 G4
_T_in0/LPLL3_T_in0 PLL3_T_in0
IOL78B/SGCLKC_8/LPLL2 SGCLKC_8/LPLL2_C_in0/L
I/O 6 DQ5 Comp_of_IOL78A True none F4
_C_in0/LPLL3_C_in0 PLL3_C_in0
IOL80A/MGCLKT_8/LPLL2 MGCLKT_8/LPLL2_T_in1/L
I/O 6 DQ5 True_of_IOL80B True x16 G5
_T_in1/LPLL3_T_in1 PLL3_T_in1
IOL80B/MGCLKC_8/LPLL MGCLKC_8/LPLL2_C_in1/L
I/O 6 DQ5 Comp_of_IOL80A True none F5
2_C_in1/LPLL3_C_in1 PLL3_C_in1
IOL83A/MGCLKT_9/LPLL2 MGCLKT_9/LPLL2_T_fb1/L
I/O 6 DQ6 True_of_IOL83B True x16 E5
_T_fb1/LPLL3_T_fb1 PLL3_T_fb1
IOL83B/MGCLKC_9/LPLL MGCLKC_9/LPLL2_C_fb1/L
I/O 6 DQ6 Comp_of_IOL83A True none D5
2_C_fb1/LPLL3_C_fb1 PLL3_C_fb1

© 2023 GOWINSEMI UG982-1.0E 34(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOL85A/SGCLKT_9/LPLL2 SGCLKT_9/LPLL2_T_fb0/L
I/O 6 DQ6 True_of_IOL85B True x16 D4
_T_fb0/LPLL3_T_fb0 PLL3_T_fb0
IOL85B/SGCLKC_9/LPLL2 SGCLKC_9/LPLL2_C_fb0/L
I/O 6 DQ6 Comp_of_IOL85A True none C4
_C_fb0/LPLL3_C_fb0 PLL3_C_fb0
IOL87A I/O 6 DQ6 True_of_IOL87B True x16 B4
IOL87B I/O 6 DQ6 Comp_of_IOL87A True none A4
IOL89A I/O 6 DQ6 True_of_IOL89B True x16 F3
IOL89B I/O 6 DQ6 Comp_of_IOL89A True none E3
IOL92A I/O 6 DQ6 True_of_IOL92B True x16 D3
IOL92B I/O 6 DQ6 Comp_of_IOL92A True none C3
IOL94A I/O 6 DQS6 True_of_IOL94B True x16 B5
IOL94B I/O 6 DQS6 Comp_of_IOL94A True none A5
IOL96A I/O 6 DQS7 True_of_IOL96B True x16 H7
IOL96B I/O 6 DQS7 Comp_of_IOL96A True none G7
IOL98A I/O 6 DQ7 True_of_IOL98B True x16 H6
IOL98B I/O 6 DQ7 Comp_of_IOL98A True none G6
BANK5 True LVDS Pair
IOB38A I/O 5 DQ8 True_of_IOB38B True x16 D23
IOB38B I/O 5 DQ8 Comp_of_IOB38A True none D24
IOB40A I/O 5 DQ8 True_of_IOB40B True x16 C24
IOB40B I/O 5 DQ8 Comp_of_IOB40A True none B24
IOB42A I/O 5 DQS8 True_of_IOB42B True x16 A23
IOB42B I/O 5 DQS8 Comp_of_IOB42A True none A24
IOB44A I/O 5 DQ8 True_of_IOB44B True x16 B25
IOB44B I/O 5 DQ8 Comp_of_IOB44A True none A25
IOB47A I/O 5 DQ8 True_of_IOB47B True x16 C26
IOB47B I/O 5 DQ8 Comp_of_IOB47A True none B26
IOB49A I/O 5 DQ8 True_of_IOB49B True x16 C22

© 2023 GOWINSEMI UG982-1.0E 35(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB49B/VREF I/O 5 DQ8 VREF Comp_of_IOB49A True none C23
IOB51A I/O 5 DQ9 True_of_IOB51B True x16 C17
IOB51B I/O 5 DQ9 Comp_of_IOB51A True none B17
IOB53A I/O 5 DQ9 True_of_IOB53B True x16 E16
IOB53B I/O 5 DQ9 Comp_of_IOB53A True none D16
IOB56A I/O 5 DQS9 True_of_IOB56B True x16 A17
IOB56B I/O 5 DQS9 Comp_of_IOB56A True none A18
IOB58A I/O 5 DQ9 True_of_IOB58B True x16 B19
IOB58B I/O 5 DQ9 Comp_of_IOB58A True none A19
IOB60A/SGCLKT_6/BPLL0 SGCLKT_6/BPLL0_T_in0/B
I/O 5 DQ9 True_of_IOB60B True x16 E17
_T_in0/BPLL1_T_in0 PLL1_T_in0
IOB60BSGCLKC_6/BPLL0 SGCLKC_6/BPLL0_C_in0/B
I/O 5 DQ9 Comp_of_IOB60A True none E18
_C_in0/BPLL1_C_in0 PLL1_C_in0
IOB62A/MGCLKT_6/BPLL MGCLKT_6/BPLL0_T_in1/B
I/O 5 DQ9 True_of_IOB62B True x16 D18
0_T_in1/BPLL1_T_in1 PLL1_T_in1
IOB62B/MGCLKC_6/BPLL MGCLKC_6/BPLL0_C_in1/
I/O 5 DQ9 Comp_of_IOB62A True none C18
0_C_in1/BPLL1_C_in1 BPLL1_C_in1
IOB66A/MGCLKT_7/BPLL MGCLKT_7/BPLL0_T_fb0/B
I/O 5 DQ10 True_of_IOB66B True x16 D19
0_T_fb0/BPLL1_T_fb0 PLL1_T_fb0
IOB66B/MGCLKC_7/BPLL MGCLKC_7/BPLL0_C_fb0/
I/O 5 DQ10 Comp_of_IOB66A True none C19
0_C_fb0/BPLL1_C_fb0 BPLL1_C_fb0
IOB68A/SGCLKT_7/BPLL0 SGCLKT_7/BPLL0_T_fb1/B
I/O 5 DQ10 True_of_IOB68B True x16 E20
_T_fb1/BPLL1_T_fb1 PLL1_T_fb1
IOB68B/SGCLKC_7/BPLL SGCLKC_7/BPLL0_C_fb1/B
I/O 5 DQ10 Comp_of_IOB68A True none D20
0_C_fb1/BPLL1_C_fb1 PLL1_C_fb1
IOB70A I/O 5 DQS10 True_of_IOB70B True x16 B20
IOB70B I/O 5 DQS10 Comp_of_IOB70A True none A20
IOB72A I/O 5 DQ10 True_of_IOB72B True x16 C21
IOB72B I/O 5 DQ10 Comp_of_IOB72A True none B21

© 2023 GOWINSEMI UG982-1.0E 36(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB74A I/O 5 DQ10 True_of_IOB74B True x16 B22
IOB74B I/O 5 DQ10 Comp_of_IOB74A True none A22
IOB76A I/O 5 DQ10 True_of_IOB76B True x16 E21
IOB76B I/O 5 DQ10 Comp_of_IOB76A True none D21
IOB78A I/O 5 DQ11 True_of_IOB78B True x16 G15
IOB78B I/O 5 DQ11 Comp_of_IOB78A True none F15
IOB80A I/O 5 DQ11 True_of_IOB80B True x16 G17
IOB80B I/O 5 DQ11 Comp_of_IOB80A True none F17
IOB83A I/O 5 DQ11 True_of_IOB83B True x16 H14
IOB83B I/O 5 DQ11 Comp_of_IOB83A True none H15
IOB85A I/O 5 DQ11 True_of_IOB85B True x16 H16
IOB85B/VREF I/O 5 DQ11 VREF Comp_of_IOB85A True none G16
IOB87A I/O 5 DQ11 True_of_IOB87B True x16 G19
IOB87B I/O 5 DQ11 Comp_of_IOB87A True none F20
IOB89A I/O 5 DQS11 True_of_IOB89B True x16 F18
IOB89B I/O 5 DQS11 Comp_of_IOB89A True none F19
BANK4 True LVDS Pair
IOB102A I/O 4 DQ12 True_of_IOB102B True x16 M16
IOB102B/VREF I/O 4 DQ12 VREF Comp_of_IOB102A True none M17
IOB104A I/O 4 DQS12 True_of_IOB104B True x16 K16
IOB104B I/O 4 DQS12 Comp_of_IOB104A True none K17
IOB106A I/O 4 DQ13 True_of_IOB106B True x16 K22
IOB106B I/O 4 DQ13 Comp_of_IOB106A True none K23
IOB108A I/O 4 DQ13 True_of_IOB108B True x16 F23
IOB108B I/O 4 DQ13 Comp_of_IOB108A True none E23
IOB110A I/O 4 DQS13 True_of_IOB110B True x16 G22
IOB110B I/O 4 DQS13 Comp_of_IOB110A True none F22

© 2023 GOWINSEMI UG982-1.0E 37(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB112A I/O 4 DQ13 True_of_IOB112B True x16 J24
IOB112B I/O 4 DQ13 Comp_of_IOB112A True none H24
IOB114A/SGCLKT_4/BPLL SGCLKT_4/BPLL2_T_fb1/B
I/O 4 DQ13 True_of_IOB114B True x16 J23
2_T_fb1/BPLL3_T_fb1 PLL3_T_fb1
IOB114B/SGCLKC_4/BPL SGCLKC_4/BPLL2_C_fb1/B
I/O 4 DQ13 Comp_of_IOB114A True none H23
L2_C_fb1/BPLL3_C_fb1 PLL3_C_fb1
IOB116A/MGCLKT_4/BPL MGCLKT_4/BPLL2_T_fb0/B
I/O 4 DQ13 True_of_IOB116B True x16 H21
L2_T_fb0/BPLL3_T_fb0 PLL3_T_fb0
IOB116B/MGCLKC_4/BPL MGCLKC_4/BPLL2_C_fb0/
I/O 4 DQ13 Comp_of_IOB116A True none H22
L2_C_fb0/BPLL3_C_fb0 BPLL3_C_fb0
IOB120A/SGCLKT_5/BPLL SGCLKT_5/BPLL2_T_in0/B
I/O 4 DQ14 True_of_IOB120B True x16 G20
2_T_in0/BPLL3_T_in0 PLL3_T_in0
IOB120B/SGCLKC_5/BPL SGCLKC_5/BPLL2_C_in0/B
I/O 4 DQ14 Comp_of_IOB120A True none G21
L2_C_in0/BPLL3_C_in0 PLL3_C_in0
IOB122A/MGCLKT_5/BPL MGCLKT_5/BPLL2_T_in1/B
I/O 4 DQ14 True_of_IOB122B True x16 K21
L2_T_in1/BPLL3_T_in1 PLL3_T_in1
IOB122B/MGCLKC_5/BPL MGCLKC_5/BPLL2_C_in1/
I/O 4 DQ14 Comp_of_IOB122A True none J21
L2_C_in1/BPLL3_C_in1 BPLL3_C_in1
IOB124A I/O 4 DQ14 True_of_IOB124B True x16 L17
IOB124B I/O 4 DQ14 Comp_of_IOB124A True none L18
IOB126A I/O 4 DQ14 True_of_IOB126B True x16 J19
IOB126B I/O 4 DQ14 Comp_of_IOB126A True none H19
IOB129A I/O 4 DQ14 True_of_IOB129B True x16 J18
IOB129B I/O 4 DQ14 Comp_of_IOB129A True none H18
IOB131A I/O 4 DQS14 True_of_IOB131B True x16 K20
IOB131B I/O 4 DQS14 Comp_of_IOB131A True none J20
IOB133A I/O 4 DQ15 True_of_IOB133B True x16 E25
IOB133B/VREF I/O 4 DQ15 VREF Comp_of_IOB133A True none D25
IOB135A I/O 4 DQS15 True_of_IOB135B True x16 E26

© 2023 GOWINSEMI UG982-1.0E 38(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOB135B I/O 4 DQS15 Comp_of_IOB135A True none D26
IOB138A I/O 4 DQ15 True_of_IOB138B True x16 H26
IOB138B I/O 4 DQ15 Comp_of_IOB138A True none G26
IOB140A I/O 4 DQ15 True_of_IOB140B True x16 G24
IOB140B I/O 4 DQ15 Comp_of_IOB140A True none F24
IOB142A I/O 4 DQ15 True_of_IOB142B True x16 J25
IOB142B I/O 4 DQ15 Comp_of_IOB142A True none J26
IOB144A I/O 4 DQ15 True_of_IOB144B True x16 G25
IOB144B I/O 4 DQ15 Comp_of_IOB144A True none F25
IOB93A I/O 4 DQ12 True_of_IOB93B True x16 M14
IOB93B I/O 4 DQ12 Comp_of_IOB93A True none L14
IOB95A/ADCINCK1 I/O 4 DQ12 ADCINCK1 True_of_IOB95B True x16 M15
IOB95B I/O 4 DQ12 Comp_of_IOB95A True none L15
IOB97A I/O 4 DQ12 True_of_IOB97B True x16 J14
IOB97B I/O 4 DQ12 Comp_of_IOB97A True none J15
IOB99A I/O 4 DQ12 True_of_IOB99B True x16 K15
IOB99B I/O 4 DQ12 Comp_of_IOB99A True none J16
BANK3 True LVDS Pair
IOR101A/D04 I/O 3 DQ16 D04 True_of_IOR101B True x16 N16
IOR101B/D05/SI I/O 3 DQ16 D05/SI Comp_of_IOR101A True none N17
IOR103A/PUDC_B I/O 3 DQS16 PUDC_B True_of_IOR103B True x16 P15
IOR103B/EMCCLK I/O 3 DQS16 EMCCLK Comp_of_IOR103A True none P16
IOR105A/D00/MOSI I/O 3 DQ16 D00/MOSI True_of_IOR105B True x16 R14
IOR105B/D01/DIN I/O 3 DQ16 D01/DIN Comp_of_IOR105A True none R15
IOR107A/D02/ADCINCK1 I/O 3 DQ16 D02/ADCINCK1 True_of_IOR107B True x16 P14
IOR107B/D03 I/O 3 DQ16 D03 Comp_of_IOR107A True none N14
IOR56A/D19 I/O 3 DQ19 D19 True_of_IOR56B True x16 T22

© 2023 GOWINSEMI UG982-1.0E 39(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR56B/D18 I/O 3 DQ19 D18 Comp_of_IOR56A True none R22
IOR58A/CLKHOLD_N I/O 3 DQS19 CLKHOLD_N True_of_IOR58B True x16 T24
IOR58B/D22 I/O 3 DQS19 D22 Comp_of_IOR58A True none T25
IOR60A/D26 I/O 3 DQ19 D26 True_of_IOR60B True x16 R25
IOR60B/D25/VREF I/O 3 DQ19 D25/VREF Comp_of_IOR60A True none P25
IOR62A/D17 I/O 3 DQ19 D17 True_of_IOR62B True x16 T23
IOR62B/D16 I/O 3 DQ19 D16 Comp_of_IOR62A True none R23
IOR65A/D21 I/O 3 DQ19 D21 True_of_IOR65B True x16 R26
IOR65B/D20 I/O 3 DQ19 D20 Comp_of_IOR65A True none P26
IOR67A/D24 I/O 3 DQ19 D24 True_of_IOR67B True x16 N26
IOR67B/D23 I/O 3 DQ19 D23 Comp_of_IOR67A True none M26
IOR69A/D28 I/O 3 DQ18 D28 True_of_IOR69B True x16 R20
IOR69B/D27 I/O 3 DQ18 D27 Comp_of_IOR69A True none R21
IOR71A/CSI_B I/O 3 DQ18 CSI_B True_of_IOR71B True x16 P19
IOR71B/D31 I/O 3 DQ18 D31 Comp_of_IOR71A True none N19
IOR74A/D30 I/O 3 DQ18 D30 True_of_IOR74B True x16 P23
IOR74B/D29 I/O 3 DQ18 D29 Comp_of_IOR74A True none P24
IOR76A/RDWR I/O 3 DQS18 RDWR True_of_IOR76B True x16 N23
IOR76B/DOUT_CSO_B I/O 3 DQS18 DOUT_CSO_B Comp_of_IOR76A True none N24
IOR78A/SGCLKT_3/RPLL SGCLKT_3/RPLL2_T_fb0/R
I/O 3 DQ18 True_of_IOR78B True x16 P20
2_T_fb0/RPLL3_T_fb0 PLL3_T_fb0
IOR78B/SGCLKC_3/RPLL SGCLKC_3/RPLL2_C_fb0/
I/O 3 DQ18 Comp_of_IOR78A True none P21
2_C_fb0/RPLL3_C_fb0 RPLL3_C_fb0
IOR80A/MGCLKT_3/RPLL MGCLKT_3/RPLL2_T_fb1/
I/O 3 DQ18 True_of_IOR80B True x16 N21
2_T_fb1/RPLL3_T_fb1 RPLL3_T_fb1
IOR80B/MGCLKC_3/RPLL MGCLKC_3/RPLL2_C_fb1/
I/O 3 DQ18 Comp_of_IOR80A True none N22
2_C_fb1/RPLL3_C_fb1 RPLL3_C_fb1

© 2023 GOWINSEMI UG982-1.0E 40(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR83A/MGCLKT_2/RPLL MGCLKT_2/RPLL2_T_in1/R
I/O 3 DQ17 True_of_IOR83B True x16 M21
2_T_in1/RPLL3_T_in1 PLL3_T_in1
IOR83B/MGCLKC_2/RPLL MGCLKC_2/RPLL2_C_in1/
I/O 3 DQ17 Comp_of_IOR83A True none M22
2_C_in1/RPLL3_C_in1 RPLL3_C_in1
IOR85A/MGCLKC_2/RPLL SGCLKT_2/RPLL2_T_in0/R
I/O 3 DQ17 True_of_IOR85B True x16 L22
2_T_in0/RPLL3_T_in0 PLL3_T_in0
IOR85B/SGCLKC_2/RPLL SGCLKC_2/RPLL2_C_in0/
I/O 3 DQ17 Comp_of_IOR85A True none L23
2_C_in0/RPLL3_C_in0 RPLL3_C_in0
IOR87A/D14 I/O 3 DQ17 D14 True_of_IOR87B True x16 M24
IOR87B/D15 I/O 3 DQ17 D15 Comp_of_IOR87A True none M25
IOR89A/SSPI_CS_N I/O 3 DQS17 SSPI_CS_N True_of_IOR89B True x16 L24
IOR89B/D13 I/O 3 DQS17 D13 Comp_of_IOR89A True none L25
IOR92A/D11 I/O 3 DQ17 D11 True_of_IOR92B True x16 M20
IOR92B/D12 I/O 3 DQ17 D12 Comp_of_IOR92A True none L20
IOR94A/D09 I/O 3 DQ17 D09 True_of_IOR94B True x16 K25
IOR94B/D10 I/O 3 DQ17 D10 Comp_of_IOR94A True none K26
IOR96A/MCS_N I/O 3 DQ16 MCS_N True_of_IOR96B True x16 P18
IOR96B/D08/VREF/SO I/O 3 DQ16 D08/VREF/SO Comp_of_IOR96A True none N18
IOR98A/D06/SSPI_CLK I/O 3 DQ16 D06/SSPI_CLK True_of_IOR98B True x16 R16
IOR98B/D07/SSPI_WPN I/O 3 DQ16 D07/SSPI_WPN Comp_of_IOR98A True none R17
BANK2 True LVDS Pair
IOR11A I/O 2 DQ23 True_of_IOR11B True x16 U14
IOR11B I/O 2 DQ23 Comp_of_IOR11A True none V14
IOR13A I/O 2 DQ23 True_of_IOR13B True x16 T14
IOR13B I/O 2 DQ23 Comp_of_IOR13A True none T15
IOR15A I/O 2 DQ22 True_of_IOR15B True x16 V19
IOR15B I/O 2 DQ22 Comp_of_IOR15A True none W19
IOR17A I/O 2 DQ22 True_of_IOR17B True x16 W20

© 2023 GOWINSEMI UG982-1.0E 41(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR17B I/O 2 DQ22 Comp_of_IOR17A True none Y20
IOR20A I/O 2 DQS22 True_of_IOR20B True x16 T20
IOR20B I/O 2 DQS22 Comp_of_IOR20A True none U20
IOR22A I/O 2 DQ22 True_of_IOR22B True x16 T19
IOR22B I/O 2 DQ22 Comp_of_IOR22A True none U19
IOR24A/SGCLKT_1/RPLL SGCLKT_1/RPLL0_T_fb0/R
I/O 2 DQ22 True_of_IOR24B True x16 W21
0_T_fb0/RPLL1_T_fb0 PLL1_T_fb0
IOR24B/SGCLKC_1/RPLL SGCLKC_1/RPLL0_C_fb0/
I/O 2 DQ22 Comp_of_IOR24A True none Y21
0_C_fb0/RPLL1_C_fb0 RPLL1_C_fb0
IOR26A/MGCLKT_1/RPLL MGCLKT_1/RPLL0_T_fb1/
I/O 2 DQ22 True_of_IOR26B True x16 U21
0_T_fb1/RPLL1_T_fb1 RPLL1_T_fb1
IOR26B/MGCLKC_1/RPLL MGCLKC_1/RPLL0_C_fb1/
I/O 2 DQ22 Comp_of_IOR26A True none V21
0_C_fb1/RPLL1_C_fb1 RPLL1_C_fb1
IOR29A/SGCLKT_0/RPLL SGCLKT_0/RPLL0_T_in0/R
I/O 2 DQ21 True_of_IOR29B True x16 Y22
0_T_in0/RPLL1_T_in0 PLL1_T_in0
IOR29B/SGCLKC_0/RPLL SGCLKC_0/RPLL0_C_in0/
I/O 2 DQ21 Comp_of_IOR29A True none Y23
0_C_in0/RPLL1_C_in0 RPLL1_C_in0
IOR2A I/O 2 DQ23 True_of_IOR2B True x16 V16
IOR2B I/O 2 DQ23 Comp_of_IOR2A True none V17
IOR31A/MGCLKT_0/RPLL MGCLKT_0/RPLL0_T_in1/R
I/O 2 DQ21 True_of_IOR31B True x16 U22
0_T_in1/RPLL1_T_in1 PLL1_T_in1
IOR31B/MGCLKC_0/RPLL MGCLKC_0/RPLL0_C_in1/
I/O 2 DQ21 Comp_of_IOR31A True none V22
0_C_in1/RPLL1_C_in1 RPLL1_C_in1
IOR33A/FBTEST_R0 I/O 2 DQ21 FBTEST_R0 True_of_IOR33B True x16 AA22
IOR33B/CLKTEST_R0 I/O 2 DQ21 CLKTEST_R0 Comp_of_IOR33A True none AA23
IOR35A I/O 2 DQS21 True_of_IOR35B True x16 AB24
IOR35B I/O 2 DQS21 Comp_of_IOR35A True none AC24
IOR38A I/O 2 DQ21 True_of_IOR38B True x16 V23
IOR38B I/O 2 DQ21 Comp_of_IOR38A True none W23

© 2023 GOWINSEMI UG982-1.0E 42(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
TrueLVDS

Pin Name Function BANK DQS Configuration Function Differential Pair LVDS X16 FPG676A
IOR40A I/O 2 DQ21 True_of_IOR40B True x16 AA24
IOR40B I/O 2 DQ21 Comp_of_IOR40A True none AB25
IOR42A I/O 2 DQ20 True_of_IOR42B True x16 Y25
IOR42B I/O 2 DQ20 Comp_of_IOR42A True none AA25
IOR44A I/O 2 DQS20 True_of_IOR44B True x16 AB26
IOR44B I/O 2 DQS20 Comp_of_IOR44A True none AC26
IOR47A I/O 2 DQ20 True_of_IOR47B True x16 V24
IOR47B/VREF I/O 2 DQ20 VREF Comp_of_IOR47A True none W24
IOR49A I/O 2 DQ20 True_of_IOR49B True x16 W25
IOR49B I/O 2 DQ20 Comp_of_IOR49A True none Y26
IOR4A I/O 2 DQ23 True_of_IOR4B True x16 V18
IOR4B/VREF I/O 2 DQ23 VREF Comp_of_IOR4A True none W18
IOR51A I/O 2 DQ20 True_of_IOR51B True x16 V26
IOR51B I/O 2 DQ20 Comp_of_IOR51A True none W26
IOR53A I/O 2 DQ20 True_of_IOR53B True x16 U25
IOR53B I/O 2 DQ20 Comp_of_IOR53A True none U26
IOR6A I/O 2 DQ23 True_of_IOR6B True x16 U15
IOR6B I/O 2 DQ23 Comp_of_IOR6A True none U16
IOR8A I/O 2 DQS23 True_of_IOR8B True x16 T17
IOR8B I/O 2 DQS23 Comp_of_IOR8A True none T18

© 2023 GOWINSEMI UG982-1.0E 43(44)

Arora Ⅴ Series of FPGA Products
GW5AT-138 Pinout Preliminary
Power

Recommended Operating Conditions of Package FPG676A in GW5AT-138

Name Description Min. Max.
VCC Core voltage 0.87V 1V
VCCO2, VCCO3, VCCO4,
I/O Bank voltage 1V 3.465V
VCCO5, VCCO6, VCCO7, VCCO10
VCC/VCCC Core voltage and clock tree voltage are internally short-circuited. 0.87V 1V
VCCX Auxiliary voltage 1.71V 1.89V
VCC_REG Regulator voltage 1.14V 1.26V
Q1_VDDHA SerDes voltage 1.71V 1.89V
Q0_VDDHA SerDes voltage 1.71V 1.89V
Q1_VDDT_IN0/Q1_VDDT_IN1/Q1_VDDT_I SerDes voltage and
0.87V 1V
N2/Q1_VDDT_IN3 Q1_VDDT_IN0/Q1_VDDT_IN1/Q1_VDDT_IN2/Q1_VDDT_IN3 are internally
Q0_VDDT_IN0/Q0_VDDT_IN1/Q0_VDDT_I SerDes voltage and
0.87V 1V
N2/Q0_VDDT_IN3 Q0_VDDT_IN0/Q0_VDDT_IN1/Q0_VDDT_IN2/Q0_VDDT_IN3 are internally
Q1_VDDA/Q1_VDDD_IN0/Q1_VDDD_IN1/ SerDes voltage and
Q1_VDDD_IN2/Q1_VDDD_IN3/Q1_VDDTC/ Q1_VDDA/Q1_VDDD_IN0/Q1_VDDD_IN1/Q1_VDDD_IN2/Q1_VDDD_IN3/Q1_V
0.87V 1V
Q1_VDDTC_IN0/Q1_VDDTC_IN1/Q1_VDD DDTC/Q1_VDDTC_IN0/Q1_VDDTC_IN1/Q1_VDDTC_IN2/Q1_VDDTC_IN3 are
TC_IN2/Q1_VDDTC_IN3 internally short-circuited.
Q0_VDDA/Q0_VDDD_IN0/Q0_VDDD_IN1/ SerDes voltage and
Q0_VDDD_IN2/Q0_VDDD_IN3/Q0_VDDTC/ Q0_VDDA/Q0_VDDD_IN0/Q0_VDDD_IN1/Q0_VDDD_IN2/Q0_VDDD_IN3/Q0_V
0.87V 1V
Q0_VDDTC_IN0/Q0_VDDTC_IN1/Q0_VDD DDTC/Q0_VDDTC_IN0/Q0_VDDTC_IN1/Q0_VDDTC_IN2/Q0_VDDTC_IN3 are
TC_IN2/Q0_VDDTC_IN3 internally short-circuited.
MIPI voltage and M0_VDDA/M0_VDDD/M1_VDDA/M1_VDDD are internally
M0_VDDA/M0_VDDD/M1_VDDA/M1_VDDD 0.87V 1V
short-circuited.
M0_VDDX/M1_VDDX MIPI voltage and M0_VDDX/M1_VDDX are internally short-circuited. 1.71V 1.89V

© 2023 GOWINSEMI UG982-1.0E 44(44)