 XC4000 Series

Field Programmable Gate Arrays

September 18, 1996 (Version 1.04) Product Specification

XC4000-Series Features Additional XC4000EX/XL Features

Note: XC4000-Series devices described in this data sheet • Highest Capacity — Over 130,000 Usable Gates
include the XC4000E, XC4000EX, XC4000L, and • Additional Routing Over XC4000E
XC4000XL. This information does not apply to the older - almost twice the routing capacity for high-density
Xilinx families: XC4000, XC4000A, XC4000D or XC4000H. designs
For information on these devices, see the Xilinx WEBLINX • Buffered Interconnect for Maximum Speed
at http://www.xilinx.com. • New Latch Capability in Configurable Logic Blocks
• Third Generation Field-Programmable Gate Arrays • Improved VersaRingTM I/O Interconnect for Better Fixed
- Select-RAMTM memory: on-chip ultra-fast RAM with Pinout Flexibility
- synchronous write option • Flexible New High-Speed Clock Network
- dual-port RAM option - 8 additional Early Buffers for shorter clock delays
- Fully PCI compliant (speed grades -3 and faster) - 4 additional FastCLKTM buffers for fastest clock input
- Abundant flip-flops - Virtually unlimited number of clock signals
- Flexible function generators • Optional Multiplexer or 2-input Function Generator on
- Dedicated high-speed carry logic Device Outputs
- Wide edge decoders on each edge • High-Speed Parallel ExpressTM Configuration Mode
- Hierarchy of interconnect lines • Improved I/O Setup and Clock-to-Output with FastCLK
- Internal 3-state bus capability and Global Early Buffers
- 8 global low-skew clock or signal distribution • 4 Additional Address Bits in Master Parallel
networks Configuration Mode
• System Performance to 66 MHz
• Flexible Array Architecture Introduction
• Systems-Oriented Features XC4000-Series high-performance, high-capacity Field Pro-
- IEEE 1149.1-compatible boundary scan logic grammable Gate Arrays (FPGAs) provide the benefits of
support custom CMOS VLSI, while avoiding the initial cost, long
- Individually programmable output slew rate development cycle, and inherent risk of a conventional
- Programmable input pull-up or pull-down resistors masked gate array.
- 12-mA sink current per XC4000E output (4 mA per
The result of eleven years of FPGA design experience and
XC4000L output)
feedback from thousands of customers, these FPGAs com-
• Configured by Loading Binary File
bine architectural versatility, on-chip Select-RAM memory
- Unlimited reprogrammability
with edge-triggered and dual-port modes, increased speed,
• Readback Capability
abundant routing resources, and new, sophisticated soft-
• Backward Compatible with XC4000 Devices
ware to achieve fully automated implementation of com-
• XACTstep Development System runs on '386/'486/
plex, high-density, high-performance designs.
Pentium-type PC, Sun-4, and Hewlett-Packard 700
series The XC4000 Series currently has 19 members, as shown
- Interfaces to popular design environments in Table 1.
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
- RAM/ROM compiler

Low-Voltage Versions Available

• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000L: Low-Voltage Versions of XC4000E devices
• XC4000XL: Low-Voltage Versions of XC4000EX
devices

September 18, 1996 (Version 1.04) 4-5

XC4000 Series Field Programmable Gate Arrays

Table 1: XC4000-Series Field Programmable Gate Arrays

Max.
Max Logic Max. RAM Typical Total Number Decode
Gates Bits Gate Range CLB Logic of Inputs Max.
Device (No RAM) (No Logic) (Logic and RAM)* Matrix Blocks Flip-Flops per side User I/O
XC4003E 3,000 3,200 2,000 - 5,000 10 x 10 100 360 30 80
XC4005E/L 5,000 6,272 3,000 - 9,000 14 x 14 196 616 42 112
XC4006E 6,000 8,192 4,000 - 12,000 16 x 16 256 768 48 128
XC4008E 8,000 10,368 6,000 - 15,000 18 x 18 324 936 54 144
XC4010E/L 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 60 160
XC4013E/L 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 72 192
XC4020E 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 84 224
XC4025E 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 96 256
XC4028EX/XL 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 96 256
XC4036EX/XL 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 108 288
XC4044EX/XL 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 120 320
XC4052XL 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 132 352
XC4062XL 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 144 384
Larger Devices Available in the First Half of 1997
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Note: Throughout the functional descriptions in this docu- can be written into the FPGA from an external device
ment, references to the XC4000E device family include the (slave, peripheral and Express modes).
XC4000L, and references to the XC4000EX device family XC4000-Series FPGAs are supported by powerful and
include the XC4000XL, unless explicitly stated otherwise. sophisticated software, covering every aspect of design
References to the XC4000 Series include the XC4000E, from schematic or behavioral entry, floorplanning, simula-
XC4000EX, XC4000L, and XC4000XL families. All func- tion, automatic block placement and routing of intercon-
tionality in low-voltage families is the same as in the corre- nects, to the creation, downloading, and readback of the
sponding 5-Volt family, except where numerical references configuration bit stream.
are made to timing, power, or current-sinking capability.
Because Xilinx FPGAs can be reprogrammed an unlimited
Description number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
XC4000-Series devices are implemented with a regular,
ware must be adapted to different user applications.
flexible, programmable architecture of Configurable Logic
FPGAs are ideal for shortening design and development
Blocks (CLBs), interconnected by a powerful hierarchy of
cycles, and also offer a cost-effective solution for produc-
versatile routing resources, and surrounded by a perimeter
tion rates well beyond 5,000 systems per month. For lowest
of programmable Input/Output Blocks (IOBs). They have
high-volume unit cost, a design can first be implemented in
generous routing resources to accommodate the most
the XC4000E or XC4000EX, then migrated to one of Xilinx’
complex interconnect patterns.
compatible HardWire mask-programmed devices.
The devices are customized by loading configuration data
Table 2 shows density and performance for a few common
into internal memory cells. The FPGA can either actively
circuit functions that can be implemented in XC4000-Series
read its configuration data from an external serial or byte-
devices.
parallel PROM (master modes), or the configuration data

4-6 September 18, 1996 (Version 1.04)

Table 2: Density and Performance for Several Common Circuit Functions in XC4000E1

Design Class Function CLBs Used XC4000E-3 XC4000E-2 Units

256 x 8 Single Port (read/modify/write) 72 63 80 MHz
32 x 16 bit FIFO
Memory
simultaneous read/write 48 63 80 MHz
MUXed read/write 32 63 80 MHz
9 bit Shift Register (with enable) 5 170 200 MHz
16 bit Pre-Scaled Counter 8 142 170 MHz
16 bit Loadable Counter 8 65 76 MHz
16 bit Accumulator 9 65 76 MHz
8 bit, 16 tap FIR Filter sample rate
Logic parallel 400 55 65 MHz
serial 68 8.1 10 MHz
8 x 8 Parallel Multiplier
single stage, register to register 73 37 30 ns
16 bit Address Decoder (internal decode) 3 4.7 3.9 ns
9 bit Parity Checker 1 4.3 2.7 ns
Note: 1. Most functions are faster in XC4000EX due to faster carry logic, direct connects, and other additional interconnect.

Taking Advantage of Reconfiguration figured dynamically to perform different functions at differ-

ent times.
FPGA devices can be reconfigured to change logic function
while resident in the system. This capability gives the sys- Reconfigurable logic can be used to implement system
tem designer a new degree of freedom not available with self-diagnostics, create systems capable of being reconfig-
any other type of logic. ured for different environments or operations, or implement
multi-purpose hardware for a given application. As an
Hardware can be changed as easily as software. Design added benefit, using reconfigurable FPGA devices simpli-
updates or modifications are easy, and can be made to fies hardware design and debugging and shortens product
products already in the field. An FPGA can even be recon- time-to-market.

September 18, 1996 (Version 1.04) 4-7

XC4000 Series Field Programmable Gate Arrays

XC4000E and XC4000EX Families Select-RAM Memory: Edge-Triggered, Synchronous

RAM Modes
Compared to the XC4000
The RAM in any CLB can be configured for synchronous,
For readers already familiar with the XC4000 family of Xil- edge-triggered, write operation. The read operation is not
inx Field Programmable Gate Arrays, the major new fea- affected by this change to an edge-triggered write.
tures in the XC4000-Series devices are listed in this
section. The biggest advantages of XC4000E and Dual-Port RAM
XC4000EX devices are significantly increased system
A separate option converts the 16x2 RAM in any CLB into a
speed, greater capacity, and new architectural features,
16x1 dual-port RAM with simultaneous Read/Write.
particularly Select-RAM memory. The XC4000EX devices
also offer many new routing features, including special The function generators in each CLB can be configured as
high-speed clock buffers that can be used to capture input either level-sensitive (asynchronous) single-port RAM,
data with minimal delay. edge-triggered (synchronous) single-port RAM, edge-trig-
gered (synchronous) dual-port RAM, or as combinatorial
Any XC4000E device is pinout- and bitstream-compatible
logic.
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E Configurable RAM Content
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an The RAM content can now be loaded at configuration time,
XC4000 device. so that the RAM starts up with user-defined data.

Most XC4000EX devices have no corresponding XC4000 H Function Generator

devices, because of the larger CLB arrays. The XC4028EX In XC4000-Series devices, the H function generator is
has the same array size as the XC4025 and XC4025E, but more versatile than in the XC4000. Its inputs can come not
is not bitstream-compatible. However, the XC4025, only from the F and G function generators but also from up
XC4025E, and XC4028EX are all pinout-compatible. to three of the four control input lines. The H function gen-
erator can thus be totally or partially independent of the
Improvements in XC4000E and XC4000EX other two function generators, increasing the maximum
Increased System Speed capacity of the device.

Delays in FPGA-based designs are layout dependent. IOB Clock Enable

There is a rule of thumb designers can consider—the sys-
The two flip-flops in each IOB have a common clock enable
tem clock rate should not exceed one third to one half of the
input, which through configuration can be activated individ-
specified toggle rate. Critical portions of a design, such as
ually for the input or output flip-flop or both. This clock
shift registers and simple counters, can run faster—approx-
enable operates exactly like the EC pin on the XC4000
imately two thirds of the specified toggle rate.
CLB. This new feature makes the IOBs more versatile, and
XC4000E and XC4000EX devices can run at synchronous avoids the need for clock gating.
system clock rates of up to 66 MHz, and internal perfor-
mance can exceed 150 MHz. This increase in performance Output Drivers
over the previous families stems from improvements in both The output pull-up structure defaults to a TTL-like totem-
device processing and system architecture. XC4000- pole. This driver is an n-channel pull-up transistor, pulling
Series devices use a sub-micron triple-layer metal process. to a voltage one transistor threshold below Vcc, just like the
In addition, many architectural improvements have been XC4000 outputs. Alternatively, XC4000-Series devices can
made, as described below. be globally configured with CMOS outputs, with p-channel
pull-up transistors pulling to Vcc. Also, the configurable pull-
PCI Compliance
up resistor in the XC4000 Series is a p-channel transistor
XC4000-Series -3 and faster speed grades are fully PCI that pulls to Vcc, whereas in the XC4000 it is an n-channel
compliant. XC4000E and XC4000EX devices can be used transistor that pulls to a voltage one transistor threshold
to implement a one-chip PCI solution. below Vcc.

Carry Logic Input Thresholds

The speed of the carry logic chain has increased dramati- The input thresholds can be globally configured for either
cally. Some parameters, such as the delay on the carry TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like
chain through a single CLB (TBYP), have improved by as XC2000 and XC3000 inputs. The two global adjustments of
much as 50% from XC4000 values. See “Fast Carry Logic” input threshold and output level are independent of each
on page 21 for more information. other.

4-8 September 18, 1996 (Version 1.04)

Global Signal Access to Logic Faster Input and Output
There is additional access from global clocks to the F and G A fast, dedicated early clock sourced by global clock buffers
function generator inputs. is available for the IOBs. To ensure synchronization with
the regular global clocks, a Fast Capture latch driven by the
Configuration Pin Pull-Up Resistors early clock is available. The input data can be initially
During configuration, the three mode pins, M0, M1, and loaded into the Fast Capture latch with the early clock, then
M2, have weak pull-up resistors. For the most popular con- transferred to the input flip-flop or latch with the low-skew
figuration mode, Slave Serial, the mode pins can thus be global clock. A programmable delay on the input can be
left unconnected. used to avoid hold-time requirements. See “IOB Input Sig-
nals” on page 24 for more information.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu- Latch Capability in CLBs
ration.
Storage elements in the XC4000EX CLB can be configured
The PROGRAM input pin has a permanent weak pull-up. as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
Soft Start-up
Like the XC3000A, XC4000-Series devices have “Soft IOB Output MUX From Output Clock
Start-up.” When the configuration process is finished and A multiplexer in the IOB allows the output clock to select
the device starts up, the first activation of the outputs is either the output data or the IOB clock enable as the output
automatically slew-rate limited. This feature avoids poten- to the pad. Thus, two different data signals can share a sin-
tial ground bounce when all outputs are turned on simulta- gle output pad, effectively doubling the number of device
neously. Immediately after start-up, the slew rate of the outputs without requiring a larger, more expensive pack-
individual outputs is, as in the XC4000 family, determined age. This multiplexer can also be configured as an AND-
by the individual configuration option. gate to implement a very fast pin-to-pin path. See “IOB
Output Signals” on page 27 for more information.
XC4000 and XC4000A Compatibility
Existing XC4000 bitstreams can be used to configure an Express Configuration Mode
XC4000E device. XC4000A bitstreams must be recom- A new slave configuration mode accepts parallel data input.
piled for use with the XC4000E due to improved routing Data is processed in parallel, rather than serialized inter-
resources, although the devices are pin-for-pin compatible. nally. Therefore, the data rate is eight times that of the six
conventional configuration modes.
Additional Improvements in XC4000EX
Only Additional Address Bits
Larger devices require more bits of configuration data. A
Increased Routing
daisy chain of several large XC4000EX devices may
New interconnect in the XC4000EX includes twenty-two require a PROM that cannot be addressed by the eighteen
additional vertical lines in each column of CLBs and twelve address bits supported in the XC4000E. The XC4000EX
new horizontal lines in each row of CLBs. The twelve family therefore extends the addressing in Master Parallel
“Quad Lines” in each CLB row and column include optional configuration mode to 22 bits.
repowering buffers for maximum speed. Additional high-
performance routing near the IOBs enhances pin flexibility.

September 18, 1996 (Version 1.04) 4-9

XC4000 Series Field Programmable Gate Arrays

Table 3: CLB Count of Selected XC4000-Series Soft Macros

7400 Equivalents CLBs Barrel Shifters CLBs Multiplexers CLBs

‘138 5 brlshft4 4 m2-1e 1
‘139 2 brlshft8 13 m4-1e 1
‘147 5 m8-1e 3
4-Bit Counters
‘148 6 m16-1e 5
‘150 5 cd4cd 3 Registers
‘151 3 cd4cle 5 rd4r 2
‘152 3 cd4rle 6 rd8r 4
‘153 2 cb4ce 3 rd16r 8
‘154 16 cb4cle 6
‘157 2 cb4re 5
‘158 2 8- and 16-Bit Counters Shift Registers
‘160 5
cb8ce 6 sr8ce 4
‘161 6
cb8re 10 sr16re 8
‘162 8
cc16ce 9 Decoders
‘163 8
cc16cle 9 d2-4e 2
‘164 4
cc16cled 21 d3-8e 4
‘165s 9
‘166 5 Identity Comparators d4-16e 16
‘168 7 comp4 1
‘174 3 comp8 2
‘194 5 comp16 5
‘195 3 Magnitude Comparators Explanation of counter nomenclature
‘280 3 compm4 4 cb = binary counter
‘283 8 compm8 9 cd = BCD counter
‘298 2 compm16 20 cc = cascadable binary counter
‘352 2 d = bidirectional
‘390 3 l = loadable
‘518 3 e = clock enable
‘521 3 r = synchronous reset
Explanation of RAM nomenclature RAMs c = asynchronous clear
s = single-port edge-triggered ram16x4 2
d = dual-port edge-triggered ram16x4s 2
no extension = level-sensitive ram16x4d 4

4-10 September 18, 1996 (Version 1.04)

Detailed Functional Description zero, one, or both of these inputs can be the outputs of F
and G; the other input(s) are from outside the CLB. The
XC4000-Series devices achieve high speed through CLB can, therefore, implement certain functions of up to
advanced semiconductor technology and improved archi- nine variables, like parity check or expandable-identity
tecture. The XC4000E and XC4000EX support system comparison of two sets of four inputs.
clock rates of up to 66 MHz and internal performance in
excess of 150 MHz. Compared to older Xilinx FPGA fami- Each CLB contains two storage elements that can be used
lies, XC4000-Series devices are more powerful. They offer to store the function generator outputs. However, the stor-
on-chip edge-triggered and dual-port RAM, clock enables age elements and function generators can also be used
on I/O flip-flops, and wide-input decoders. They are more independently. These storage elements can be configured
versatile in many applications, especially those involving as flip-flops in both XC4000E and XC4000EX devices; in
RAM. Design cycles are faster due to a combination of the XC4000EX they can optionally be configured as
increased routing resources and more sophisticated soft- latches. DIN can be used as a direct input to either of the
ware. two storage elements. H1 can drive the other through the H
function generator. Function generator outputs can also
Basic Building Blocks drive two outputs independent of the storage element out-
puts. This versatility increases logic capacity and simplifies
Xilinx user-programmable gate arrays include two major routing.
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs). Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
• CLBs provide the functional elements for constructing inputs and outputs connect to the programmable intercon-
the user’s logic. nect resources outside the block.
• IOBs provide the interface between the package pins
and internal signal lines. Function Generators
Three other types of circuits are also available: Four independent inputs are provided to each of two func-
• 3-State buffers (TBUFs) driving horizontal longlines are tion generators (F1 - F4 and G1 - G4). These function gen-
associated with each CLB. erators, with outputs labeled F’ and G’, are each capable of
• Wide edge decoders are available around the periphery implementing any arbitrarily defined Boolean function of
of each device. four inputs. The function generators are implemented as
• An on-chip oscillator is provided. memory look-up tables. The propagation delay is therefore
independent of the function implemented.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config- A third function generator, labeled H’, can implement any
urable elements to the appropriate networks. Boolean function of its three inputs. Two of these inputs
can optionally be the F’ and G’ functional generator out-
The functionality of each circuit block is customized during puts. Alternatively, one or both of these inputs can come
configuration by programming internal static memory cells. from outside the CLB (H2, H0). The third input must come
The values stored in these memory cells determine the from outside the block (H1).
logic functions and interconnections implemented in the
FPGA. Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’
Each of these available circuits is described in this section. or H’ can be connected to the Y output.
Configurable Logic Blocks (CLBs) A CLB can be used to implement any of the following func-
tions:
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in • any function of up to four variables, plus any second
Figure 1. The number of CLBs needed to implement function of up to four unrelated variables, plus any third
selected soft macros is shown in Table 3. function of up to three unrelated variables1
• any single function of five variables
Two 4-input function generators (F and G) offer unrestricted • any function of four variables together with some
versatility. Most combinatorial logic functions need four or functions of six variables
fewer inputs. However, a third function generator (H) is pro- • some functions of up to nine variables.
vided. The H function generator has three inputs. Either

1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.

September 18, 1996 (Version 1.04) 4-11

XC4000 Series Field Programmable Gate Arrays

4
C1 • • • C4

H1 D IN /H 2 SR/H 0 EC

G4 S/R Bypass
CONTROL
DIN YQ
G3 LOGIC SD
F' D
FUNCTION G' Q
G'
OF
H'
G2 G1-G4

G1
LOGIC
EC
FUNCTION RD
G'
OF H' H'
F', G', 1
AND Y
H1
F4 Bypass
S/R
CONTROL
DIN XQ
F3 LOGIC SD
F'
FUNCTION F' D Q
G'
OF
H'
F2 F1-F4

F1

EC
RD
K
(CLOCK) 1
H'
X
F'

Multiplexer Controlled
by Configuration Program
X6692

Figure 1: Simplified Block Diagram of XC4000-Series CLB (RAM and Carry Logic functions not shown)

Implementing wide functions in a single block reduces both

the number of blocks required and the delay in the signal Table 4: CLB Storage Element Functionality
path, achieving both increased capacity and speed. (active rising edge is shown)

The versatility of the CLB function generators significantly Mode K EC SR D Q

improves system speed. In addition, the design-software Power-Up or
tools can deal with each function generator independently. X X X X SR
GSR
This flexibility improves cell usage. X X 1 X SR
Flip-Flops Flip-Flop __/ 1* 0* D D
0 X 0* X Q
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial 1 1* 0* X Q
Latch
results or other incoming data in one or two flip-flops, and 0 1* 0* D D
connect their outputs to the interconnect network as well. Both X 0 0* X Q
The two edge-triggered D-type flip-flops have common Legend:
X Don’t care
clock (K) and clock enable (EC) inputs. Either or both clock __/ Rising edge
inputs can also be permanently enabled. Storage element SR Set or Reset value. Reset is default.
functionality is described in Table 4. 0* Input is Low or unconnected (default value)
1* Input is High or unconnected (default value)
Latches (XC4000EX only)
The CLB storage elements can also be configured as Clock Input
latches. The two latches have common clock (K) and clock Each flip-flop can be triggered on either the rising or falling
enable (EC) inputs. Storage element functionality is clock edge. The clock pin is shared by both storage ele-
described in Table 4. ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.

4-12 September 18, 1996 (Version 1.04)

Clock Enable Data Inputs and Outputs
The clock enable signal (EC) is active High. The EC pin is The source of a storage element data input is programma-
shared by both storage elements. If left unconnected for ble. It is driven by any of the functions F’, G’, and H’, or by
either, the clock enable for that storage element defaults to the Direct In (DIN) block input. The flip-flops or latches drive
the active state. EC is not invertible within the CLB. the XQ and YQ CLB outputs.

Set/Reset Two fast feed-through paths are available, as shown in

Figure 1. A two-to-one multiplexer on each of the XQ and
An asynchronous storage element input (SR) can be con- YQ outputs selects between a storage element output and
figured as either set or reset. This configuration option any of the control inputs. This bypass is sometimes used
determines the state in which each flip-flop becomes oper- by the automated router to repower internal signals.
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the Control Signals
effect of a pulse on the SR pin of the CLB. All three set/ Multiplexers in the CLB map the four control inputs (C1 - C4
reset functions for any single flip-flop are controlled by the in Figure 1) into the four internal control signals (H1, DIN/
same configuration data bit. H2, SR/H0, and EC). Any of these inputs can drive any of
The set/reset state can be independently specified for each the four internal control signals.
flip-flop. This input can also be independently disabled for When the logic function is enabled, the four inputs are:
either flip-flop.
• EC — Enable Clock
The set/reset state is specified by using the INIT attribute, • SR/H0 — Asynchronous Set/Reset or H function
or by placing the appropriate set or reset flip-flop library generator Input 0
symbol. • DIN/H2 — Direct In or H function generator Input 2
SR is active High. It is not invertible within the CLB. • H1 — H function generator Input 1.

Global Set/Reset When the memory function is enabled, the four inputs are:

A separate Global Set/Reset line (not shown in Figure 1) • EC — Enable Clock

sets or clears each storage element during power-up, • WE — Write Enable
reconfiguration, or when a dedicated Reset net is driven • D0 — Data Input to F and/or G function generator
active. This global net (GSR) does not compete with other • D1 — Data input to G function generator (16x1 and
routing resources; it uses a dedicated distribution network. 16x2 modes) or 5th Address bit (32x1 mode).

Each flip-flop is configured as either globally set or reset in Using FPGA Flip-Flops and Latches
the same way that the local set/reset (SR) is specified. The abundance of flip-flops in the XC4000 Series invites
Therefore, if a flip-flop is set by SR, it is also set by GSR. pipelined designs. This is a powerful way of increasing per-
Similarly, a reset flip-flop is reset by both SR and GSR. formance by breaking the function into smaller subfunc-
GSR can be driven from any user-programmable pin as a tions and executing them in parallel, passing on the results
global reset input. To use this global net, place an input through pipeline flip-flops. This method should be seriously
pad and input buffer in the schematic or HDL code, driving considered wherever throughput is more important than
the GSR pin of the STARTUP symbol. (See Figure 2.) A latency.
specific pin location can be assigned to this input using a To include a CLB flip-flop, place the appropriate library
LOC attribute or property, just as with any other user-pro- symbol. For example, FDCE is a D-type flip-flop with clock
grammable pad. An inverter can optionally be inserted enable and asynchronous clear. The corresponding latch
after the input buffer to invert the sense of the Global Set/ symbol (for the XC4000EX only) is called LDCE.
Reset signal.
In XC4000-Series devices, the flip flops can be used as
Alternatively, GSR can be driven from any internal node. registers or shift registers without blocking the function gen-
erators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
STARTUP
The CLB setup time is specified between the function gen-
PAD GSR Q2 erator inputs and the clock input K. Therefore, the specified
GTS Q3
IBUF CLB flip-flop setup time includes the delay through the
Q1Q4 function generator.
CLK DONEIN

X5260
Figure 2: Schematic Symbols for Global Set/Reset

September 18, 1996 (Version 1.04) 4-13

XC4000 Series Field Programmable Gate Arrays

Using Function Generators as RAM RAM Configuration Options

Optional modes for each CLB make the memory look-up The function generators in any CLB can be configured as
tables in the F’ and G’ function generators usable as an RAM arrays in the following sizes:
array of Read/Write memory cells. Available modes are • Two 16x1 RAMs: two data inputs and two data outputs
level-sensitive (similar to the XC4000/A/H families), edge- with identical or, if preferred, different addressing for
triggered, and dual-port edge-triggered. Depending on the each RAM
selected mode, a single CLB can be configured as either a • One 32x1 RAM: one data input and one data output.
16x2, 32x1, or 16x1 bit array.
One F or G function generator can be configured as a 16x1
Supported CLB memory configurations and timing modes RAM while the other function generators are used to imple-
for single- and dual-port modes are shown in Table 5. ment any function of up to 5 inputs.
XC4000-Series devices are the first programmable logic Additionally, the XC4000-Series RAM may have either of
devices with edge-triggered (synchronous) and dual-port two timing modes:
RAM accessible to the user. Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective • Edge-Triggered (Synchronous): data written by the
throughput of FIFO applications. These features can be designated edge of the CLB clock. WE acts as a true
individually programmed in any XC4000-Series CLB. clock enable.
• Level-Sensitive (Asynchronous): an external WE signal
Advantages of On-Chip and Edge-Triggered RAM acts as the write strobe.
The on-chip RAM is extremely fast. The read access time The selected timing mode applies to both function genera-
is the same as the logic delay. The write access time is tors within a CLB when both are configured as RAM.
slightly slower. Both access times are much faster than The number of read ports is also programmable:
any off-chip solution, because they avoid I/O delays.
• Single Port: each function generator has a common
Edge-triggered RAM, also called synchronous RAM, is a read and write port
feature never before available in a Field Programmable • Dual Port: both function generators are configured
Gate Array. The simplicity of designing with edge-triggered together as a single 16x1 dual-port RAM with one write
RAM, and the markedly higher achievable performance, port and two read ports. Simultaneous read and write
add up to a significant improvement over existing devices operations to the same or different addresses are
with on-chip RAM. supported.
Three application notes are available from Xilinx that dis- RAM configuration options are selected by placing the
cuss edge-triggered RAM: “XC4000E Edge-Triggered and appropriate library symbol.
Dual-Port RAM Capability,” “Implementing FIFOs in
XC4000E RAM,” and “Synchronous and Asynchronous Choosing a RAM Configuration Mode
FIFO Designs.” All three application notes apply to both
The appropriate choice of RAM mode for a given design
XC4000E and XC4000EX RAM.
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
Table 5: Supported RAM Modes cess. Recommended usage is shown in Table 6.
The difference between level-sensitive, edge-triggered,
16 16 32 Edge- Level-
and dual-port RAM is only in the write operation. Read
x x x Triggered Sensitive
operation and timing is identical for all modes of operation.
1 2 1 Timing Timing
Single-Port √ √ √ √ √ Table 6: RAM Mode Selection
Dual-Port √ √ Dual-Port
Level- Edge- Edge-
Sensitive Triggered Triggered
Use for New
No Yes Yes
Designs?
Size (16x1,
1/2 CLB 1/2 CLB 1 CLB
Registered)
Simultaneous
No No Yes
Read/Write
Relative 2X (4X
X 2X
Performance effective)

4-14 September 18, 1996 (Version 1.04)

 4
C1 • • • C4

WE D1 D0 EC

DIN

WRITE 16-LATCH
DECODER ARRAY MUX G'
4 4
G1 • • • G4
1 of 16

LATCH
ENABLE
READ
WRITE PULSE ADDRESS

DIN

WRITE 16-LATCH
DECODER ARRAY MUX F'
4 4
F1 • • • F4
1 of 16

LATCH
ENABLE
K
(CLOCK) READ
WRITE PULSE ADDRESS

X6752

Figure 3: 16x2 (or 16x1) Edge-Triggered Single-Port RAM

4
C1 • • • C4

EC
WE D1/A4 D0 EC

DIN

WRITE 16-LATCH
DECODER ARRAY MUX G'
G1 • • • G4 4 4
F1 • • • F4 1 of 16

LATCH
ENABLE
READ
WRITE PULSE ADDRESS

H'

DIN

WRITE 16-LATCH
DECODER ARRAY MUX F'
4 4
1 of 16

LATCH
ENABLE
K
(CLOCK) READ
WRITE PULSE ADDRESS
X6754

Figure 4: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)

September 18, 1996 (Version 1.04) 4-15

XC4000 Series Field Programmable Gate Arrays

RAM Inputs and Outputs

TWPS
The F1-F4 and G1-G4 inputs to the function generators act WCLK (K)
as address lines, selecting a particular memory cell in each
TWSS TWHS
look-up table.
The functionality of the CLB control signals changes when WE
the function generators are configured as RAM. The DIN/
TDSS TDHS
H2, H1, and SR/H0 lines become the two data inputs (D0,
D1) and the Write Enable (WE) input for the 16x2 memory. DATA IN
When the 32x1 configuration is selected, D1 acts as the
fifth address bit and D0 is the data input. TASS TAHS
The contents of the memory cell(s) being addressed are
ADDRESS
available at the F’ and G’ function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be cap-
TILO TILO
tured in the CLB flip-flop(s). TWOS
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other por- DATA OUT OLD NEW
tions of the CLB, with the exception of the redefinition of the
X6461
control signals. In 16x2 and 16x1 modes, the H’ function
Figure 5: Edge-Triggered RAM Write Timing
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or
D0 signals. CLB either by the same clock edge as the RAM, or by the
opposite edge of this clock. The sense of WCLK applies to
Single-Port Edge-Triggered Mode both function generators in the CLB when both are config-
ured as RAM.
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000-Series edge-triggered RAM timing The WE pin is active-High and is not invertible within the
operates like writing to a data register. Data and address CLB.
are presented. The register is enabled for writing by a logic Note: The pulse following the active edge of WCLK (TWPS
High on the write enable input, WE. Then a rising or falling in Figure 5) must be less than one millisecond wide. For
clock edge loads the data into the register, as shown in most applications, this requirement is not overly restrictive;
Figure 5. however, it must not be forgotten. Stopping WCLK at this
Complex timing relationships between address, data, and point in the write cycle could result in excessive current and
write enable signals are not required, and the external write even damage to the larger devices if many CLBs are con-
enable pulse becomes a simple clock enable. The active figured as edge-triggered RAM.
edge of WCLK latches the address, input data, and WE sig-
nals. An internal write pulse is generated that performs the Table 7: Single-Port Edge-Triggered RAM Signals
write. See Figure 3 and Figure 4 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, single- RAM Signal CLB Pin Function
port RAM. D D0 or D1 Data In
(16x2, 16x1)
The relationships between CLB pins and RAM inputs and
D0 (32x1)
outputs for single-port, edge-triggered mode are shown in
Table 7. A[3:0] F1-F4 or Address
G1-G4
The Write Clock input (WCLK) can be configured as active
A[4] D1 (32x1) Address
on either the rising edge (default) or the falling edge. It
WE WE Write Enable
uses the same CLB pin (K) used to clock the CLB flip-flops,
but it can be independently inverted. Consequently, the WCLK K Clock
RAM output can optionally be registered within the same SPO F’ or G’ Single Port Out
(Data Out) (Data Out)

4-16 September 18, 1996 (Version 1.04)

Dual-Port Edge-Triggered Mode Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
In dual-port mode, both the F and G function generators
output, a FIFO that can read and write simultaneously is
are used to create a single 16x1 RAM array with one write
easily generated. Simultaneous access doubles the effec-
port and two read ports. The resulting RAM array can be
tive throughput of the FIFO.
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the The relationships between CLB pins and RAM inputs and
same address are also supported. outputs for dual-port, edge-triggered mode are shown in
Table 8. See Figure 7 for a block diagram of a CLB config-
Dual-port mode always has edge-triggered write timing, as
ured in this mode.
shown in Figure 5.
Note: The pulse following the active edge of WCLK (TWPS
Figure 6 shows a simple model of an XC4000-Series CLB
in Figure 5) must be less than one millisecond wide. For
configured as dual-port RAM. One address port, labeled
most applications, this requirement is not overly restrictive;
A[3:0], supplies both the read and write address for the F
however, it must not be forgotten. Stopping WCLK at this
function generator. This function generator behaves the
point in the write cycle could result in excessive current and
same as a 16x1 single-port edge-triggered RAM array. The
even damage to the larger devices if many CLBs are con-
RAM output, Single Port Out (SPO), appears at the F func-
figured as edge-triggered RAM.
tion generator output. SPO, therefore, reflects the data at
address A[3:0]. Table 8: Dual-Port Edge-Triggered RAM Signals
The other address port, labeled DPRA[3:0] for Dual Port RAM Signal CLB Pin Function
Read Address, supplies the read address for the G function D D0 Data In
generator. The write address for the G function generator,
A[3:0] F1-F4 Read Address for F,
however, comes from the address A[3:0]. The output from
Write Address for F and G
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the DPRA[3:0] G1-G4 Read Address for G
data at address DPRA[3:0]. WE WE Write Enable
WCLK K Clock
RAM16X1D Primitive
SPO F’ Single Port Out
DPO (Dual Port Out) (addressed by A[3:0])
WE WE
DPO G’ Dual Port Out
D D D Q Registered DPO
DPRA[3:0] AR[3:0]
(addressed by
AW[3:0] DPRA[3:0])

G Function Generator

SPO (Single Port Out)

WE
D D Q Registered SPO
A[3:0] AR[3:0]
AW[3:0]

F Function Generator

WCLK

X6755

Figure 6: XC4000-Series Dual-Port RAM, Simple

Model

September 18, 1996 (Version 1.04) 4-17

XC4000 Series Field Programmable Gate Arrays

4
C1 • • • C4

WE D1 D0 EC

DIN

WRITE 16-LATCH
DECODER ARRAY MUX G'
4
1 of 16

LATCH
ENABLE

READ
4 WRITE PULSE ADDRESS
G1 • • • G4

DIN

WRITE 16-LATCH
DECODER ARRAY MUX F'
4 4
F1 • • • F4 1 of 16

LATCH
ENABLE
K
READ
(CLOCK) WRITE PULSE ADDRESS

X6748
Figure 7: 16x1 Edge-Triggered Dual-Port RAM

4-18 September 18, 1996 (Version 1.04)

Single-Port Level-Sensitive Timing Mode However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
Note: Edge-triggered mode is recommended for all new
application.
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000-Series backward-com- Figure 8 shows the write timing for level-sensitive, single-
patibility with the XC4000 family. port RAM.
Level-sensitive RAM timing is simple in concept but can be The relationships between CLB pins and RAM inputs and
complicated in execution. Data and address signals are outputs for single-port level-sensitive mode are shown in
presented, then a positive pulse on the write enable pin Table 9.
(WE) performs a write into the RAM at the designated Figure 9 and Figure 10 show block diagrams of a CLB con-
address. As indicated by the “level-sensitive” label, this figured as 16x2 and 32x1 level-sensitive, single-port RAM.
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address. Initializing RAM at Configuration
Changing the address lines while WE is High results in spu-
Both RAM and ROM implementations of the XC4000-
rious data written to the new address—and possibly at
Series devices are initialized during configuration. The ini-
other addresses as well, as the address lines inevitably do
tial contents are defined via an INIT attribute or property
not all change simultaneously.
attached to the RAM or ROM symbol, as described in the
The user must generate a carefully timed WE signal. The schematic library guide.
delay on the WE signal and the address lines must be care-
If not defined, all RAM contents are initialized to all zeros,
fully verified to ensure that WE does not become active until
by default.
after the address lines have settled, and that WE goes inac-
tive before the address lines change again. The data must RAM initialization occurs only during configuration. The
be stable before and after the falling edge of WE. RAM content is not affected by Global Set/Reset.
In practical terms, WE is usually generated by a 2X clock. If Table 9: Single-Port Level-Sensitive RAM Signals
a 2X clock is not available, the falling edge of the system
RAM Signal CLB Pin Function
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive D D0 or D1 Data In
before the next rising edge of the system clock. Several A[3:0] F1-F4 or Address
older application notes are available from Xilinx that dis- G1-G4
cuss the design of level-sensitive RAMs. These application WE WE Write Enable
notes include XAPP031, “Using the XC4000 RAM Capabil- O F’ or G’ Data Out
ity,” and XAPP042, “High-Speed RAM Design in XC4000.”

T WC

ADDRESS

TAS T WP T AH
WRITE ENABLE

T DS T DH

DATA IN REQUIRED

X6462

Figure 8: Level-Sensitive RAM Write Timing

September 18, 1996 (Version 1.04) 4-19

XC4000 Series Field Programmable Gate Arrays

4
C1 • • • C4

WE D1 D0 EC

DIN
Enable

WRITE 16-LATCH
DECODER ARRAY MUX G'
4
G1 • • • G4
1 of 16

4
READ ADDRESS

DIN
Enable

WRITE 16-LATCH
DECODER ARRAY MUX F'
4
F1 • • • F4
1 of 16

4
X6746 READ ADDRESS

Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM

4
C1 • • • C4

WE D1/A4 D0 EC

DIN
Enable

WRITE 16-LATCH
DECODER ARRAY MUX G'
G1 • • • G4 4
F1 • • • F4 1 of 16

4
READ ADDRESS

H'

DIN
Enable

WRITE 16-LATCH
DECODER ARRAY MUX F'
4
1 of 16

4
READ ADDRESS X6749

Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)

4-20 September 18, 1996 (Version 1.04)

Fast Carry Logic The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: “Using the Dedicated Carry Logic in
Each CLB F and G function generator contains dedicated
XC4000.” This discussion also applies to XC4000E
arithmetic logic for the fast generation of carry and borrow
devices, and to XC4000EX devices when the minor logic
signals. This extra output is passed on to the function gen-
changes are taken into account.
erator in the adjacent CLB. The carry chain is independent
of normal routing resources. The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
Dedicated fast carry logic greatly increases the efficiency
ros (RPMs) that already include these symbols.
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
CLB CLB CLB CLB
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in
microprocessor or graphics systems, and high-speed addi-
tion in digital signal processing are two typical applications.
The two 4-input function generators can be configured as a CLB CLB CLB CLB
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level. CLB CLB CLB CLB

This fast carry logic is one of the more significant features

of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or CLB CLB CLB CLB
down. At the top and bottom of the columns where there
are no CLBs above and below, the carry is propagated to X6687
the right. (See Figure 11.) In order to improve speed in the
Figure 11: Available XC4000E Carry Propagation
high-capacity XC4000EX devices, which can potentially
Paths
have very long carry chains, the carry chain travels upward
only, as shown in Figure 12. This restriction should have lit-
tle impact, because the smallest XC4000EX device, the
XC4028EX, can accommodate a 64-bit carry chain in a sin-
gle column. Additionally, standard interconnect can be CLB CLB CLB CLB
used to route a carry signal in the downward direction.
Figure 13 on page 22 shows an XC4000E CLB with dedi-
cated fast carry logic. The carry logic in the XC4000EX is
similar, except that COUT exits at the top only, and the sig-
nal CINDOWN does not exist. As shown in Figure 13, the CLB CLB CLB CLB
carry logic shares operand and control inputs with the func-
tion generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums. CLB CLB CLB CLB
Figure 14 and Figure 15 on page 23 show the details of the
carry logic for the XC4000E and the XC4000EX respec-
tively. These diagrams show the contents of the box
labeled “CARRY LOGIC” in Figure 13. As shown, the
CLB CLB CLB CLB
XC4000EX carry logic eliminated a multiplexer to reduce
delay on the pass-through carry chain. Additionally, the
multiplexer on the G4 path now has a memory-programma-
X6610
ble input, which permits G4 to directly connect to COUT.
G4 thus becomes an additional high-speed initialization Figure 12: Available XC4000EX Carry Propagation
path for carry-in. Paths (dotted lines use general interconnect)

September 18, 1996 (Version 1.04) 4-21

XC4000 Series Field Programmable Gate Arrays

C OUT C IN DOWN D IN
CARRY
LOGIC

Y
G H
CARRY

G4

G3
G
G2 DIN
H S/R
G D Q YQ
F
G1
EC
COUT0

H1 H

DIN
F H S/R
CARRY G D Q XQ
F

EC
F4

F3
F
F2

H
F1
X
F

CIN UP C OUT K S/R EC

X6699

Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000EX)

4-22 September 18, 1996 (Version 1.04)

 C OUT

M
G1
M
1
0 1 G2
I 0

G4

G3
C OUT0
TO
M FUNCTION
GENERATORS
F2
M
1
0 1
F1
M 0
F4

M 0 1

M 3
F3 1 M
M 0

M 1 0

C IN UP
X2000
C IN DOWN

Figure 14: Detail of XC4000E Dedicated Carry Logic

COUT

G1 M

M
1
0 1
G2
M 0

G4

G3
COUT0
TO
M FUNCTION
F2 GENERATORS
M
1
0 1
F1
M 0
F4
M 0 1
M 3
F3 1
M 0 M

C IN UP
M X6701

Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences from XC4000E carry logic)

September 18, 1996 (Version 1.04) 4-23

XC4000 Series Field Programmable Gate Arrays

Input/Output Blocks (IOBs) Table 10: Supported Sources for XC4000-Series Device
Inputs
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal XC4000-Series Inputs
logic. Each IOB controls one package pin and can be con- 3.3 V, 5 V, 5 V,
figured for input, output, or bidirectional signals. Source
CMOS TTL CMOS
Figure 16 shows a simplified block diagram of the Any device, Vcc = 3.3 V,
√ √
XC4000E IOB. A more complete diagram of the XC4000E CMOS outputs
Unreli-
IOB can be found in Figure 42 on page 51, in the “Boundary XC4000-Series, Vcc = 5 V,
√ √ able
Scan” section. Figure 42 includes the boundary scan logic TTL outputs
Data
in the IOB. Any device, Vcc = 5 V,
√ √
Figure 17 shows a simplified block diagram of the TTL outputs (Voh ≤ 3.7 V)
XC4000EX IOB. The XC4000EX IOB contains some spe- Any device, Vcc = 5 V,
Danger1 √ √
cial features not included in the XC4000E IOB. These fea- CMOS outputs
tures are highlighted in Figure 17, and discussed
1. Acceptable for XC4000XL if the designated 5-Volt
throughout this section. When XC4000EX special features supply pad (VTT) is tied to 5V.
are discussed, they are clearly identified in the text. Any
feature not so identified is present in both XC4000E and Registered Inputs
XC4000EX devices. The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.
IOB Input Signals
The input and output storage elements in each IOB have a
Two paths, labeled I1 and I2 in Figure 16 and Figure 17,
common clock enable input, which, through configuration,
bring input signals into the array. Inputs also connect to an
can be activated individually for the input or output flip-flop,
input register that can be programmed as either an edge-
or both. This clock enable operates exactly like the EC pin
triggered flip-flop or a level-sensitive latch.
on the XC4000-Series CLB. It cannot be inverted within
The choice is made by placing the appropriate library sym- the IOB.
bol. For example, IFD is the basic input flip-flop (rising
The storage element behavior is shown in Table 11.
edge triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and Table 11: Input Register Functionality
some combinations of latches and flip-flops can be imple- (active rising edge is shown)
mented in a single IOB, as described in the XACT Libraries
Clock
Guide. Mode Clock D Q
Enable
The inputs can be globally configured for either TTL (1.2V, Power-Up or X X X SR
default) or CMOS thresholds, using an option in the Make- GSR
Bits program. There is a slight hysteresis of about 300mV.
Flip-Flop __/ 1* D D
The output levels are also configurable; the two global
0 X X Q
adjustments of input threshold and output level are inde-
pendent. Latch 1 1* X Q
0 1* D D
Inputs of the low-voltage devices must be configured as
CMOS at all times. They can be driven by the outputs of all Both X 0 X Q
5-Volt XC4000-Series devices, provided that the 5-Volt out- Legend:
X Don’t care
puts are in TTL mode. They can also be driven by any TTL __/ Rising edge
output that does not exceed 3.7 V. 5-Volt XC3000-family SR Set or Reset value. Reset is default.
device outputs, for example, are TTL-compatible, but since 0* Input is Low or unconnected (default value)
the output voltage can exceed 3.7 V, they cannot be used to 1* Input is High or unconnected (default value)
drive an XC4000L or XC4000XL input.
The inputs of XC4000-Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000-Series device inputs are
shown in Table 10.

4-24 September 18, 1996 (Version 1.04)

 Slew Rate Passive
Pull-Up/
Control Pull-Down

T
Flip-Flop
D Q
Out Output
CE Buffer
Pad
Output
Clock

I1
Flip- Input
Flop/ Buffer
Latch
I2
Q D
Delay

Clock
Enable CE

Input
Clock
X6704

Figure 16: Simplified Block Diagram of XC4000E IOB

Slew Rate Passive

Pull-Up/
Control Pull-Down

T
Output MUX

0
1
Flip-Flop
Out D Q
Output
CE Buffer
Pad

Output Clock Input

Buffer

I1

Flip-Flop/
Latch
I2 Delay Delay
Q D

Q D
Latch
Clock Enable CE Fast G
Capture
Latch
Input Clock
X5984

Figure 17: Simplified Block Diagram of XC4000EX IOB (shaded areas indicate differences from XC4000E)

September 18, 1996 (Version 1.04) 4-25

XC4000 Series Field Programmable Gate Arrays

Optional Delay Guarantees Zero Hold Time Additional Input Latch for Fast Capture (XC4000EX
only)
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup The XC4000EX IOB has an additional optional latch on the
time of the input flip-flop is increased so that normal clock input. This latch, as shown in Figure 17, is clocked by the
routing does not result in a positive hold-time requirement. output clock — the clock used for the output flip-flop —
A positive hold time requirement can lead to unreliable, rather than the input clock. Therefore, two different clocks
temperature- or processing-dependent operation. can be used to clock the two input storage elements. This
additional latch allows the very fast capture of input data,
The input flip-flop setup time is defined between the data
which is then synchronized to the internal clock by the IOB
measured at the device I/O pin and the clock input at the
flip-flop or latch.
IOB (not at the clock pin). Any routing delay from the
device clock pin to the clock input of the IOB must, there- To use this Fast Capture technique, drive the output clock
fore, be subtracted from this setup time to arrive at the real pin (the Fast Capture latching signal) from the output of one
setup time requirement relative to the device pins. A short of the Global Early or FastCLK buffers supplied in the
specified setup time might, therefore, result in a negative XC4000EX. The second storage element should be
setup time at the device pins, i.e., a positive hold-time clocked by a Global Low-Skew buffer, to synchronize the
requirement. incoming data to the internal logic. (See Figure 18.) These
special buffers are described in “Global Nets and Buffers
When a delay is inserted on the data line, more clock delay
(XC4000EX only)” on page 43.
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a The Fast Capture latch is designed primarily for use with a
data hold-time requirement at the external pin. The maxi- Global Early buffer. For Fast Capture, a single clock signal
mum delay is therefore inserted as the default. is routed through both a Global Early buffer and a Global
Low-Skew buffer. (The two buffers share an input pad.)
The XC4000E IOB has a one-tap delay element: either the
The Fast Capture latch is clocked by the Global Early
delay is inserted (default), or it is not. The delay guarantees
buffer, and the standard IOB flip-flop or latch is clocked by
a zero hold time with respect to clocks routed through any
the Global Low-Skew buffer. This mode is the safest way to
of the XC4000E global clock buffers. (See “Global Nets
use the Fast Capture latch, because the clock buffers on
and Buffers (XC4000E only)” on page 41 for a description
both storage elements are driven by the same pad. There
of the global clock buffers in the XC4000E.) For a shorter
is no external skew between clock pads to create potential
input register setup time, with non-zero hold, attach a
problems.
NODELAY attribute or property to the flip-flop.
Alternatively, a FastCLK buffer can be used to minimize the
The XC4000EX IOB has a two-tap delay element, with
setup time of device inputs, if a positive hold time is accept-
choices of a full delay, a partial delay, or no delay. The
able. Use the FastCLK buffer to clock the Fast Capture
attributes or properties used to select the desired delay are
latch, and a slower clock buffer to clock the standard IOB
shown in Table 12. The choices are no added attribute,
flip-flop or latch. Either the Global Early buffer or the Global
MEDDELAY, and NODELAY. The default setting, with no
Low-Skew buffer can be used for the second storage ele-
added attribute, ensures no hold time with respect to any of
the XC4000EX clock buffers, including the Global Low-
ILFFX
Skew buffers. MEDDELAY ensures no hold time with
respect to the Global Early and FastCLK buffers. Inputs IPAD D Q to internal
logic
with NODELAY may have a positive hold time with respect
to all clock buffers, including the FastCLK buffers. For a GF
BUFGE
description of each of these buffers, see “Global Nets and CE
Buffers (XC4000EX only)” on page 43. IPAD
C

BUFGLS
Table 12: XC4000EX IOB Input Delay Element

Value When to Use ILFFX

full delay Zero Hold with respect to Global Low- IPAD D Q to internal
logic
(default, no Skew Buffer, Global Early Buffer, or
attribute added) FastCLK Buffer IPAD GF
BUFFCLK
MEDDELAY Zero Hold with respect to Global Early CE

Buffer or FastCLK Buffer IPAD

C
NODELAY
NODELAY Short Setup, positive Hold time BUFGLS
X6705

Figure 18: Examples Using XC4000EX Fast

Capture Latch

4-26 September 18, 1996 (Version 1.04)

ment, but whichever one is used should be the same clock Table 13: Output Flip-Flop Functionality (active rising
as the related internal logic. Since the FastCLK pads are edge is shown)
different from the Global Early and Global Low-Skew pads,
care must be taken to ensure that skew external to the Clock
device does not create internal timing difficulties. Mode Clock Enable T D Q
Power-Up X X 0* X SR
To place the Fast Capture latch in a design, use one of the or GSR
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
X 0 0* X Q
parent-Low Fast Capture latch followed by an active-High
input flip-flop. ILFLX is a transparent-Low Fast Capture Flip-Flop __/ 1* 0* D D
latch followed by a transparent-High input latch. Any of the X X 1 X Z
clock inputs can be inverted before driving the library ele- 0 X 0* X Q
ment, and the inverter is absorbed into the IOB. If a single Legend:
BUFG output is used to drive both clock inputs, the soft- X Don’t care
ware automatically runs the clock through both a Global __/ Rising edge
SR Set or Reset value. Reset is default.
Low-Skew buffer and a Global Early buffer, and clocks the 0* Input is Low or unconnected (default value)
Fast Capture latch appropriately. 1* Input is High or unconnected (default value)
Z 3-state
Figure 17 on page 25 also shows a two-tap delay on the
input. By default, if the Fast Capture latch is used, the Xilinx By default, the output pull-up structure is configured as a
software assumes a Global Early buffer is driving the clock, TTL-like totem-pole. The High driver is an n-channel pull-
and selects MEDDELAY to ensure a zero hold time. This up transistor, pulling to a voltage one transistor threshold
default can be overridden to remove the delay, if FastClk is below Vcc. Alternatively, the outputs can be globally con-
used, by attaching a NODELAY attribute or property to the figured as CMOS drivers, with p-channel pull-up transistors
ILFFX or ILFLX latch. Select the desired delay based on pulling to Vcc. This MakeBits option applies to all outputs
the discussion in the previous subsection. on the device. It is not individually programmable.

IOB Output Signals Outputs of low-voltage devices must be configured as

CMOS at all times. They can drive the inputs of any 5-Volt
Output signals can be optionally inverted within the IOB, device with TTL-compatible thresholds.
and can pass directly to the pad or be stored in an edge-
triggered flip-flop. The functionality of this flip-flop is shown Any XC4000-Series 5-Volt device with its outputs config-
in Table 13. ured in TTL mode can drive the inputs of any typical 3.3-
Volt device. (For a detailed discussion of how to interface
An active-High 3-state signal can be used to place the out- between 5 V and 3.3 V devices, see the 3V Products sec-
put buffer in a high-impedance state, implementing 3-state tion of The Programmable Logic Data Book.)
outputs or bidirectional I/O. Under configuration control,
the output (OUT) and output 3-state (T) signals can be Supported destinations for XC4000-Series device outputs
inverted. The polarity of these signals is independently are shown in Table 14.
configured for each IOB. Table 14: Supported Destinations for XC4000-Series
The 4-mA maximum output current specification of many Outputs
FPGAs often forces the user to add external buffers, which XC4000-Series
are especially cumbersome on bidirectional I/O lines. The Outputs
XC4000E and XC4000EX devices solve many of these Destination 3.3 V, 5 V, 5 V,
problems by providing a guaranteed output sink current of
CMOS TTL CMOS
12 mA. Two adjacent outputs can be interconnected exter-
Any typical device, Vcc = 3.3 V, √ √ some1
nally to sink up to 24 mA. (XC4000L and XC4000XL out-
CMOS-threshold inputs
puts can sink up to 4 mA, and two adjacent XC4000L and
XC4000XL outputs can sink up to 8 mA.) The XC4000E Any device, Vcc = 5 V, √ √ √
and XC4000EX FPGAs can thus directly drive buses on a TTL-threshold inputs
printed circuit board. Any device, Vcc = 5 V, Unreliable √
CMOS-threshold inputs Data
1. Only if destination device has 5-V tolerant inputs

September 18, 1996 (Version 1.04) 4-27

XC4000 Series Field Programmable Gate Arrays

GTS can be driven from any user-programmable pin as a

global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
OPAD the GTS pin of the STARTUP symbol. A specific pin loca-
OBUFT tion can be assigned to this input using a LOC attribute or
X6702
property, just as with any other user-programmable pad.
Figure 19: Open-Drain Output An inverter can optionally be inserted after the input buffer
to invert the sense of the Global 3-State signal. Using GTS
An output can be configured as open-drain (open-collector) is similar to GSR. See Figure 2 on page 13 for details.
by placing an OBUFT symbol in a schematic or HDL code,
Alternatively, GTS can be driven from any internal node.
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 19.) Output Multiplexer/2-Input Function Generator
(XC4000EX only)
Output Slew Rate
As shown in Figure 17 on page 25, the output path in the
The slew rate of each output buffer is, by default, reduced,
XC4000EX IOB contains an additional multiplexer not avail-
to minimize power bus transients when switching non-criti-
able in the XC4000E IOB. The multiplexer can also be con-
cal signals. For critical signals, attach a FAST attribute or
figured as a 2-input function generator, implementing a
property to the output buffer or flip-flop.
pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2
For XC4000E devices, maximum total capacitive load for inverted inputs. The logic used to implement these func-
simultaneous fast mode switching in the same direction is tions is shown in the upper gray area of Figure 17.
200 pF for all package pins between each Power/Ground
When configured as a multiplexer, this feature allows two
pin pair. For XC4000EX devices, additional internal Power/
output signals to time-share the same output pad; effec-
Ground pin pairs are connected to special Power and
tively doubling the number of device outputs without requir-
Ground planes within the packages, to reduce ground
ing a larger, more expensive package.
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair. When the MUX is configured as a 2-input function genera-
Maximum loading may vary for the low-voltage devices. tor, logic can be implemented within the IOB itself. Com-
bined with either a FastCLK or Global Early buffer, this
For slew-rate limited outputs this total is two times larger for
arrangement allows very high-speed gating of a single sig-
each device type: 400 pF for XC4000E devices and 600 pF
nal. For example, a wide decoder can be implemented in
for XC4000EX devices. This maximum capacitive load
CLBs, and its output gated with a Read or Write Strobe
should not be exceeded, as it can result in ground bounce
driven by a FastCLK buffer, as shown in Figure 20. The
of greater than 1.5 V amplitude and more than 5 ns dura-
critical-path pin-to-pin delay of this circuit is less than 6
tion. This level of ground bounce may cause undesired
nanoseconds. (This value may not be achievable in
transient behavior on an output, or in the internal logic.
XC4000XL devices.)
This restriction is common to all high-speed digital ICs, and
is not particular to Xilinx or the XC4000 Series. As shown in Figure 17, the IOB input pins Out, Output
Clock, and Clock Enable have different delays and different
XC4000-Series devices have a feature called “Soft Start-
flexibilities regarding polarity. Additionally, Output Clock
up,” designed to reduce ground bounce when all outputs
sources are more limited than the other inputs. Therefore,
are turned on simultaneously at the end of configuration.
the Xilinx software does not move logic into the IOB func-
When the configuration process is finished and the device
tion generators unless explicitly directed to do so.
starts up, the first activation of the outputs is automatically
slew-rate limited. Immediately following the initial activation
of the I/O, the slew rate of the individual outputs is deter-
mined by the individual configuration option for each IOB. IPAD
BUFFCLK
Global Three-State F
OPAD
A separate Global 3-State line (not shown in Figure 16 or from
FAST
Figure 17) forces all FPGA outputs to the high-impedance internal OAND2
state, unless boundary scan is enabled and is executing an logic
EXTEST instruction. This global net (GTS) does not com- X6698

pete with other routing resources; it uses a dedicated distri- Figure 20: Fast Pin-to-Pin Path in XC4000E
bution network.

4-28 September 18, 1996 (Version 1.04)

 are independent, except that in the XC4000EX, the Fast
OMUX2 Capture latch shares an IOB input with the output clock pin.
D0
F O
D1 Early Clock for IOBs (XC4000EX only)
OAND2 S0 Special early clocks are available for IOBs. These clocks
X6598

X6599
are sourced by the same sources as the Global Low-Skew
Figure 21: Output AND and MUX Symbols in buffers, but are separately buffered. They have fewer loads
XC4000EX IOB and therefore less delay. The early clock can drive either
the IOB output clock or the IOB input clock, or both. The
The user can specify that the IOB function generator be early clock allows fast capture of input data, and fast clock-
used, by placing special library symbols beginning with the to-output on output data. The Global Early buffers that
letter “O.” For example, a 2-input AND-gate in the IOB func- drive these clocks are described in “Global Nets and Buff-
tion generator is called OAND2. Use the symbol input pin ers (XC4000EX only)” on page 43.
labelled “F” for the signal on the critical path. This signal is
Fast Clock for IOBs (XC4000EX only)
placed on the OK pin — the IOB input with the shortest
delay to the function generator. Two examples are shown in Very fast clocks driven by FastCLK buffers are also avail-
Figure 21. able for IOBs. These clocks are sourced by semi-dedicated
pads—the pads can be used as general I/O if not used to
Other IOB Options drive FastCLK buffers. There are two FastCLK buffers on
There are a number of other programmable options in the the left edge, and two on the right edge of the device. They
XC4000-Series IOB. provide the fastest method of reaching the IOB clock pins.
The FastCLK buffer can drive either the IOB output clock or
Pull-up and Pull-down Resistors the IOB input clock, or both. These buffers allow the fastest
Programmable pull-up and pull-down resistors are useful possible setup times and clock-to-output times. The Fast-
for tying unused pins to Vcc or Ground to minimize power CLK buffers are described in “Global Nets and Buffers
consumption and reduce noise sensitivity. The configurable (XC4000EX only)” on page 43.
pull-up resistor is a p-channel transistor that pulls to Vcc. Global Set/Reset
The configurable pull-down resistor is an n-channel transis-
tor that pulls to Ground. As with the CLB registers, the Global Set/Reset signal
(GSR) can be used to set or clear the input and output reg-
The value of these resistors is 50 kΩ − 100 kΩ. This high isters, depending on the value of the INIT attribute or prop-
value makes them unsuitable as wired-AND pull-up resis- erty. The two flip-flops can be individually configured to set
tors. or clear on reset and after configuration. Other than the
The pull-up resistors for most user-programmable IOBs are global GSR net, no user-controlled set/reset signal is avail-
active during the configuration process. See Table 24 on able to the I/O flip-flops. The choice of set or clear applies
page 78 for a list of pins with pull-ups active before and dur- to both the initial state of the flip-flop and the response to
ing configuration. the Global Set/Reset pulse. See “Global Set/Reset” on
page 13 for a description of how to use GSR.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise JTAG Support
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis- Embedded logic attached to the IOBs contains test struc-
tor active. Alternatively, they can be individually configured tures compatible with IEEE Standard 1149.1 for boundary
with the pull-down resistor, or as a driven output, or to be scan testing, permitting easy chip and board-level testing.
driven by an external source. To activate the internal pull- More information is provided in “Boundary Scan” on
up, attach the PULLUP library component to the net page 50.
attached to the pad. To activate the internal pull-down,
Three-State Buffers
attach the PULLDOWN library component to the net
attached to the pad. A pair of 3-state buffers is associated with each CLB in the
array. (See Figure 27 on page 34.) These 3-state buffers
Independent Clocks can be used to drive signals onto the nearest horizontal
Separate clock signals are provided for the input and output longlines above and below the CLB. They can therefore be
flip-flops. The clock can be independently inverted for each used to implement multiplexed or bidirectional buses on the
flip-flop within the IOB, generating either falling-edge or ris- horizontal longlines, saving logic resources. Programma-
ing-edge triggered flip-flops. The clock inputs for each IOB ble pull-up resistors attached to these longlines help to
implement a wide wired-AND function.

September 18, 1996 (Version 1.04) 4-29

XC4000 Series Field Programmable Gate Arrays

The buffer enable is an active-High 3-state (i.e. an active- WAND4, WAND8, and WAND16 are also available. See
Low enable), as shown in Table 15. the XACT Libraries Guide for further information.
Another 3-state buffer with similar access is located near The T pin is internally tied to the I pin. Connect the input to
each I/O block along the right and left edges of the array. the I pin and the output to the O pin. Connect the outputs of
(See Figure 33 on page 39.) all the WAND1s together and attach a PULLUP symbol.
The horizontal longlines driven by the 3-state buffers have a Wired OR-AND
weak keeper at each end. This circuit prevents undefined
floating levels. However, it is overridden by any driver, even The buffer can be configured as a Wired OR-AND. A High
a pull-up resistor. level on either input turns off the output. Use the
WOR2AND library symbol, which is essentially an open-
Special longlines running along the perimeter of the array drain 2-input OR gate. The two input pins are functionally
can be used to wire-AND signals coming from nearby IOBs equivalent. Attach the two inputs to the I0 and I1 pins and
or from internal longlines. These longlines form the wide tie the output to the O pin. Tie the outputs of all the
edge decoders discussed in “Wide Edge Decoders” on WOR2ANDs together and attach a PULLUP symbol.
page 31.
Three-State Buffer Examples
Three-State Buffer Modes
Figure 22 shows how to use the 3-state buffers to imple-
The 3-state buffers can be configured in three modes: ment a wired-AND function. When all the buffer inputs are
• Standard 3-state buffer High, the pull-up resistor(s) provide the High output.
• Wired-AND with input on the I pin Figure 23 shows how to use the 3-state buffers to imple-
• Wired OR-AND ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Standard 3-State Buffer
Pay particular attention to the polarity of the T pin when
All three pins are used. Place the library element BUFT.
using these buffers in a design. Active-High 3-state (T) is
Connect the input to the I pin and the output to the O pin.
identical to an active-Low output enable, as shown in
The T pin is an active-High 3-state (i.e. an active-Low
Table 15.
enable). Tie the T pin to Ground to implement a standard
buffer. Table 15: Three-State Buffer Functionality

Wired-AND with Input on the I Pin IN T OUT

The buffer can be used as a Wired-AND. Use the WAND1 X 1 Z
library symbol, which is essentially an open-drain buffer. IN 0 IN

P
Z=D ●D ● (D +D ) ● (D +D ) U U
A B C D E F
L P
L

D D
C E
D D D D
A B D F
WAND1 WAND1
W0R2AND W0R2AND

X6465

Figure 22: Open-Drain Buffers Implement a Wired-AND Function

Z = DA • A + D B • B + D C • C + D N • N
~100 kΩ

DA DB DC DN
BUFT BUFT BUFT BUFT
A B C N
X6466

"Weak Keeper"

Figure 23: 3-State Buffers Implement a Multiplexer

4-30 September 18, 1996 (Version 1.04)

Wide Edge Decoders
INTERCONNECT
Dedicated decoder circuitry boosts the performance of
wide decoding functions. When the address or data field is IOB IOB
wider than the function generator inputs, FPGAs need .I1 .I1
multi-level decoding and are thus slower than PALs. A C B
XC4000-Series CLBs have nine inputs. Any decoder of up
to nine inputs is, therefore, compact and fast. However,
there is also a need for much wider decoders, especially for
address decoding in large microprocessor systems.
( C) .....
An XC4000-Series FPGA has four programmable decod- (A • B • C) .....
ers located on each edge of the device. The inputs to each (A • B • C) .....
decoder are any of the IOB I1 signals on that edge plus one (A • B • C) .....
local interconnect per CLB row or column. Each row or col-
umn of CLBs provides up to three variables or their compli- X2627

ments., as shown in Figure 24. Each decoder generates a Figure 24: XC4000-Series Edge Decoding Example
High output (resistor pull-up) when the AND condition of
the selected inputs, or their complements, is true. This is
analogous to a product term in typical PAL devices.
On-Chip Oscillator
Each of these wired-AND gates is capable of accepting up XC4000-Series devices include an internal oscillator. This
to 42 inputs on the XC4005E and 72 on the XC4013E. oscillator is used to clock the power-on time-out, for config-
There are up to 96 inputs for each decoder on the uration memory clearing, and as the source of CCLK in
XC4028EX and 132 on the XC4052EX. The decoders may Master configuration modes. The oscillator runs at a nom-
also be split in two when a larger number of narrower inal 8 MHz frequency that varies with process, Vcc, and
decoders are required, for a maximum of 32 decoders per temperature. The output frequency falls between 4 and 10
device. MHz. (The oscillator operates more slowly at lower volt-
ages. The output frequency may be reduced by as much
The decoder outputs can drive CLB inputs, so they can be as 10% for low-voltage devices.)
combined with other logic to form a PAL-like AND/OR struc-
ture. The decoder outputs can also be routed directly to the The oscillator output is optionally available after configura-
chip outputs. For fastest speed, the output should be on tion. Any two of four resynchronized taps of a built-in
the same chip edge as the decoder. Very large PALs can divider are also available. These taps are at the fourth,
be emulated by ORing the decoder outputs in a CLB. This ninth, fourteenth and nineteenth bits of the divider. There-
decoding feature covers what has long been considered a fore, if the primary oscillator output is running at the nomi-
weakness of older FPGAs. Users often resorted to exter- nal 8 MHz, the user has access to an 8 MHz clock, plus any
nal PALs for simple but fast decoding functions. Now, the two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower
dedicated decoders in the XC4000-Series device can for low-voltage devices). These frequencies can vary by as
implement these functions fast and efficiently. much as -50% or +25%.

To use the wide edge decoders, place one or more of the These signals can be accessed by placing the OSC4
WAND library symbols (WAND1, WAND4, WAND8, library element in a schematic or in HDL code (see
WAND16). Attach a DECODE attribute or property to each Figure 25).
WAND symbol. Tie the outputs together and attach a PUL- The oscillator is automatically disabled after configuration if
LUP symbol. Location attributes or properties such as L the OSC4 symbol is not used in the design.
(left edge) or TR (right half of top edge) should also be used
to ensure the correct placement of the decoder inputs.
OSC4
F8M
F500K
F16K
F490
F15

X6703

Figure 25: XC4000-Series Oscillator Symbol

September 18, 1996 (Version 1.04) 4-31

XC4000 Series Field Programmable Gate Arrays

Programmable Interconnect CLB Routing Connections

All internal connections are composed of metal segments A high-level diagram of the routing resources associated
with programmable switching points and switching matrices with one CLB is shown in Figure 26. The shaded arrows
to implement the desired routing. A structured, hierarchical represent routing present only in XC4000EX devices.
matrix of routing resources is provided to achieve efficient Table 16 shows how much routing of each type is available
automated routing. in XC4000E and XC4000EX CLB arrays. Clearly, very
The XC4000E and XC4000EX share a basic interconnect large designs, or designs with a great deal of interconnect,
structure. XC4000EX devices, however, have additional will route more easily in the XC4000EX. Smaller XC4000E
routing not available in the XC4000E. The extra routing designs, typically requiring significantly less interconnect,
resources allow high utilization in high-capacity devices. do not require the additional routing.
All XC4000EX-specific routing resources are clearly identi- Figure 27 on page 34 is a detailed diagram of both the
fied throughout this section. Any resources not identified XC4000E and the XC4000EX CLB, with associated rout-
as XC4000EX-specific are present in all XC4000-Series ing. The shaded square is the programmable switch
devices. matrix, present in both the XC4000E and the XC4000EX.
This section describes the varied routing resources avail- The L-shaped shaded area is present only in XC4000EX
able in XC4000-Series devices. The implementation soft- devices. As shown in the figure, the XC4000EX block is
ware automatically assigns the appropriate resources essentially an XC4000E block with additional routing.
based on the density and timing requirements of the CLB inputs and outputs are distributed on all four sides,
design. providing maximum routing flexibility. In general, the entire
architecture is symmetrical and regular. It is well suited to
Interconnect Overview established placement and routing algorithms. Inputs, out-
There are several types of interconnect. puts, and function generators can freely swap positions
• CLB routing is associated with each row and column of within a CLB to avoid routing congestion during the place-
the CLB array. ment and routing operation.
• IOB routing forms a ring (called a VersaRing) around Table 16: Routing per CLB in XC4000-Series Devices
the outside of the CLB array. It connects the I/O with
the internal logic blocks. XC4000E XC4000EX
• Global routing consists of dedicated networks primarily Vertical Horizontal Vertical Horizontal
designed to distribute clocks throughout the device with Singles 8 8 8 8
minimum delay and skew. Global routing can also be Doubles 4 4 4 4
used for other high-fanout signals. Quads 0 0 12 12
Five interconnect types are distinguished by the relative Longlines 6 6 10 6
length of their segments: single-length lines, double-length Direct 0 0 2 2
lines, quad and octal lines (XC4000EX only), and longlines. Connects
In the XC4000EX, direct connects allow fast data flow Globals 4 0 8 0
between adjacent CLBs, and between IOBs and CLBs.
Carry Logic 2 0 1 0
Extra routing is included in the IOB pad ring. The Total 24 18 45 32
XC4000EX also includes a ring of octal interconnect lines
near the IOBs to improve pin-swapping and routing to
locked pins.
XC4000E devices include two types of global buffers, while
XC4000EX devices have three different types. These glo-
bal buffers have different properties, and are intended for
different purposes. They are discussed in detail later in this
section.

4-32 September 18, 1996 (Version 1.04)

 Quad

Single

Double

Long

Direct
CLB Connect

Long

Quad Long Global Long Double Single Global Carry Direct

Clock Clock Chain Connect

x5994

Figure 26: High-Level Routing Diagram of XC4000-Series CLB (shaded arrows indicate XC4000EX only)

September 18, 1996 (Version 1.04) 4-33

XC4000 Series Field Programmable Gate Arrays

QUAD

DOUBLE

SINGLE

DOUBLE

LONG

F4 C4 G4
YQ
Y DIRECT
G1
C1
F1
CLB G3
C3 FEEDBACK
F3
K
X
XQ
F2 C2 G2

LONG

LO G LO D D LO G D
LO O O LO IR
Q N N U SI U N BA EC FE
U G BA G BL N BL G
AD L E G E L T ED
LE BA
C
K

Common to XC4000E and XC4000EX

XC4000EX only

Programmable Switch Matrix

Figure 27: Detail of Programmable Interconnect Associated with XC4000-Series CLB

4-34 September 18, 1996 (Version 1.04)

 Single-Length Lines
Single-length lines provide the greatest interconnect flexi-

e
es
e

bl
bl

gl

ou
ou bility and offer fast routing between adjacent blocks. There

in

D
S
D
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switch-
Double ing matrices that are located in every row and a column of
CLBs.
Singles Single-length lines are connected by way of the program-
Six Pass Transistors mable switch matrices, as shown in Figure 29. Routing
Per Switch Matrix
Interconnect Point connectivity is shown in Figure 27.
Double
Single-length lines incur a delay whenever they go through
X6600 a switching matrix. Therefore, they are not suitable for rout-
Figure 28: Programmable Switch Matrix (PSM) ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
Programmable Switch Matrices branching for nets with fanout greater than one.

The horizontal and vertical single- and double-length lines Double-Length Lines
intersect at a box called a programmable switch matrix The double-length lines consist of a grid of metal segments,
(PSM). Each switch matrix consists of programmable pass each twice as long as the single-length lines: they run past
transistors used to establish connections between the lines two CLBs before entering a switch matrix. Double-length
(see Figure 28). lines are grouped in pairs with the switch matrices stag-
For example, a single-length signal entering on the right gered, so that each line goes through a switch matrix at
side of the switch matrix can be routed to a single-length every other row or column of CLBs (see Figure 29).
line on the top, left, or bottom sides, or any combination There are four vertical and four horizontal double-length
thereof, if multiple branches are required. Similarly, a dou- lines associated with each CLB. These lines provide faster
ble-length signal can be routed to a double-length line on signal routing over intermediate distances, while retaining
any or all of the other three edges of the programmable routing flexibility. Double-length lines are connected by way
switch matrix. of the programmable switch matrices. Routing connectivity
is shown in Figure 27.

CLB CLB CLB

Doubles

PSM PSM Singles

Doubles

CLB CLB CLB

PSM PSM

CLB CLB CLB

X6601

Figure 29: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs)

September 18, 1996 (Version 1.04) 4-35

XC4000 Series Field Programmable Gate Arrays

Quad Lines (XC4000EX only) Each buffered switch matrix contains one buffer and six
pass transistors. It resembles the programmable switch
XC4000EX devices also include twelve vertical and twelve
matrix shown in Figure 28, with the addition of a program-
horizontal quad lines per CLB row and column. Quad lines
mable buffer. There can be up to two independent inputs
are four times as long as the single-length lines. They are
and up to two independent outputs. Only one of the inde-
interconnected via buffered switch matrices (shown as dia-
pendent inputs can be buffered.
monds in Figure 27 on page 34). Quad lines run past four
CLBs before entering a buffered switch matrix. They are The place and route software automatically uses the timing
grouped in fours, with the buffered switch matrices stag- requirements of the design to determine whether or not a
gered, so that each line goes through a buffered switch quad line signal should be buffered. A heavily loaded sig-
matrix at every fourth CLB location in that row or column. nal is typically buffered, while a lightly loaded one is not.
(See Figure 30.) One scenario is to alternate buffers and pass transistors.
This allows both vertical and horizontal quad lines to be
The buffered switch matrixes have four pins, one on each
buffered at alternating buffered switch matrices.
edge. All of the pins are bidirectional. Any pin can drive
any or all of the other pins. Due to the buffered switch matrices, quad lines are very
fast. They provide the fastest available method of routing
heavily loaded signals for long distances across the device.

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

X6602
Figure 30: Quad Lines (XC4000EX only)

4-36 September 18, 1996 (Version 1.04)

Longlines Direct Interconnect (XC4000EX only)
Longlines form a grid of metal interconnect segments that The XC4000EX offers two direct, efficient and fast connec-
run the entire length or width of the array. Longlines are tions between adjacent CLBs. These nets facilitate a data
intended for high fan-out, time-critical signal nets, or nets flow from the left to the right side of the device, or from the
that are distributed over long distances. In XC4000EX top to the bottom, as shown in Figure 31. Signals routed on
devices, quad lines are preferred for critical nets, because the direct interconnect exhibit minimum interconnect prop-
the buffered switch matrices make them faster for high fan- agation delay and use no general routing resources.
out nets. The direct interconnect is also present between CLBs and
Two horizontal longlines per CLB can be driven by 3-state adjacent IOBs. Each IOB on the left and top device edges
or open-drain drivers (TBUFs). They can therefore imple- has a direct path to the nearest CLB. Each CLB on the
ment unidirectional or bidirectional buses, wide multiplex- right and bottom edges of the array has a direct path to the
ers, or wired-AND functions. (See “Three-State Buffers” on nearest two IOBs, since there are two IOBs for each row or
page 29 for more details.) column of CLBs.
Each horizontal longline driven by TBUFs has either two The place and route software uses direct interconnect
(XC4000E) or eight (XC4000EX) pull-up resistors. To acti- whenever possible, to maximize routing resources and min-
vate these resistors, attach a PULLUP symbol to the long- imize interconnect delays.
line net. The software automatically activates the appropri-
ate number of pull-ups. There is also a weak keeper at
each end of these two horizontal longlines. This circuit pre-

IOB

IOB

IOB

IOB

IOB

IOB
vents undefined floating levels. However, it is overridden by
any driver, even a pull-up resistor.
Each XC4000E longline has a programmable splitter switch

~ ~
~
IOB IOB
at its center, as does each XC4000EX longline driven by CLB CLB CLB

~
TBUFs. This switch can separate the line into two indepen- IOB IOB
dent routing channels, each running half the width or height ~ ~
~ ~ ~ ~
~ ~ ~ ~
~ ~
of the array.
IOB ~ ~
~ IOB
Each XC4000EX longline not driven by TBUFs has a buff- CLB CLB CLB
~
ered programmable splitter switch at the 1/4, 1/2, and 3/4 IOB IOB
points of the array. Due to the buffering, XC4000EX lon-
gline performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
IOB

IOB

IOB

IOB

IOB

IOB
are independent. X6603

Routing connectivity of the longlines is shown in Figure 27 Figure 31: XC4000EX Direct Interconnect
on page 34.

September 18, 1996 (Version 1.04) 4-37

XC4000 Series Field Programmable Gate Arrays

I/O Routing Figure 33 is a detailed diagram of the XC4000E and

XC4000EX VersaRing. The area shown includes two IOBs.
XC4000-Series devices have additional routing around the There are two IOBs per CLB row or column, therefore this
IOB ring. This routing is called a VersaRing. The diagram corresponds to the CLB routing diagram shown in
VersaRing facilitates pin-swapping and redesign without Figure 27 on page 34. The shaded areas represent routing
affecting board layout. Included are eight double-length and routing connections present only in XC4000EX
lines spanning two CLBs (four IOBs), and four longlines. devices.
Global lines and Wide Edge Decoder lines are provided.
XC4000EX devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
Figure 32. The shaded arrows represent routing present
only in XC4000EX devices.

WED
IOB
Quad
WED
Single

Double
INTERCONNECT
Long

Direct
Connect

Long
IOB
WED

Direct Edge Double Long Global Octal

Connect Decode Clock
X5995

Figure 32: High-Level Routing Diagram of XC4000-Series VersaRing (Left Edge)

WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000EX only)

4-38 September 18, 1996 (Version 1.04)

 QUAD

T
O
DOUBLE

C
SINGLE L
B
DOUBLE

LONG
A
R
R
IOB
A
DECODER

I1 I2
IK
OK
T
CE
O
DIRECT
Y
DECODER

IOB
T O
OK CE
DECODER

IK
I1 I2

LONG
G
LO

ED EC

LO
D
N

G OD
D

O
BA
G

E
O

C
U

TA
L
BL

L
E
E

Common to XC4000E and XC4000EX

XC4000EX only

Figure 33: Detail of Programmable Interconnect Associated with XC4000-Series IOB (Left Edge)

September 18, 1996 (Version 1.04) 4-39

XC4000 Series Field Programmable Gate Arrays

Octal I/O Routing (XC4000EX only) most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Between the XC4000EX CLB array and the pad ring, eight
Figure 34.
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See Figure 34.) IOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
These routing tracks are called octals, because they can be
also used for communication between the octals and dou-
broken every eight CLBs (sixteen IOBs) by a programma-
ble-length lines, quads, and longlines within the CLB array.
ble buffer that also functions as a splitter switch. The buff-
ers are staggered, so each line goes through a buffer at Segmentation into buffered octals was found to be optimal
every eighth CLB location around the device edge. for distributing signals over long distances around the
device.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment

IOB IOB

IOB IOB

Segment with nearest buffer

connects to segment with furthest buffer

IOB IOB

IOB IOB

X6607

Figure 34: XC4000EX Octal I/O Routing

4-40 September 18, 1996 (Version 1.04)

Global Nets and Buffers Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
Both the XC4000E and the XC4000EX have dedicated glo- slightly longer delay and slightly more skew due to poten-
bal networks. These networks are designed to distribute tially heavier loading, but offer greater flexibility when used
clocks and other high fanout control signals throughout the to drive non-clock CLB inputs.
devices with minimal skew. The global buffers are
described in detail in the following sections. The text The Primary Global buffers must be driven by the semi-
descriptions and diagrams are summarized in Table 17. dedicated pads. The Secondary Global buffers can be
The table shows which CLB and IOB clock pins can be sourced by either semi-dedicated pads or internal nets.
sourced by which global buffers. Each CLB column has four dedicated vertical Global lines.
In both XC4000E and XC4000EX devices, placement of a Each of these lines can be accessed by one particular Pri-
library symbol called BUFG results in the software choos- mary Global buffer, or by any of the Secondary Global buff-
ing the appropriate clock buffer, based on the timing ers, as shown in Figure 35. Each corner of the device has
requirements of the design. The detailed information in one Primary buffer and one Secondary buffer.
these sections is included only for reference. IOBs along the left and right edges have four vertical global
longlines. Top and bottom IOBs can be clocked from the
Global Nets and Buffers (XC4000E only)
global lines in the adjacent CLB column.
Four vertical longlines in each CLB column are driven
A global buffer should be specified for all timing-sensitive
exclusively by special global buffers. These longlines are
global signal distribution. To use a global buffer, place a
in addition to the vertical longlines used for standard inter-
BUFGP (primary buffer), BUFGS (secondary buffer), or
connect. The four global lines can be driven by either of
BUFG (either primary or secondary buffer) element in a
two types of global buffers. The clock pins of every CLB
schematic or in HDL code. If desired, attach a LOC
and IOB can also be sourced from local interconnect.
attribute or property to direct placement to the designated
Two different types of clock buffers are available in the location. For example, attach a LOC=L attribute or property
XC4000E: to a BUFGS symbol to direct that a buffer be placed in one
• Primary Global Buffers (BUFGP) of the two Secondary Global buffers on the left edge of the
• Secondary Global Buffers (BUFGS) device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
Table 17: Clock Pin Access

XC4000E XC4000EX Local

L&R T&B BUFFCL Inter-
BUFGP BUFGS BUFGLS
BUFGE BUFGE K connect
All CLBs in Quadrant √ √ √ √ √ √
All CLBs in Device √ √ √ √
IOBs on Adjacent Vertical √ √ √ √ √ √ √
Half Edge
IOBs on Adjacent Vertical √ √ √ √ √
Full Edge
IOBs on Adjacent Horizontal √ √
Half Edge (Direct)
IOBs on Adjacent Horizontal √ √ √ √ √ √
Half Edge (through CLB globals)
IOBs on Adjacent Horizontal √ √ √ √
Full Edge (through CLB globals)
L = Left, R = Right, T = Top, B = Bottom

September 18, 1996 (Version 1.04) 4-41

XC4000 Series Field Programmable Gate Arrays

IOB IOB IOB IOB

locals

locals

locals

locals
BUFGS BUFGP
PGCK1 SGCK4
SGCK1 PGCK4
4
4
BUFGP BUFGS
4
4 locals locals
CLB CLB
IOB IOB

locals locals
X4 Any BUFGS X4 X4 Any BUFGS X4
locals locals
One BUFGP One BUFGP
IOB per Global Line per Global Line IOB
locals CLB CLB locals

BUFGS BUFGP

PGCK2 SGCK3
SGCK2 PGCK3
locals

locals

locals

locals
BUFGP BUFGS

IOB IOB IOB IOB

X6604

Figure 35: XC4000E Global Net Distribution

BUFGLS IOB IOB IOB IOB BUFGLS

GCK1 GCK8 GCK7 GCK6

BUFGE BUFGE
locals

locals

locals

locals

BUFGLS BUFGE BUFGE BUFGLS

BUFFCLK CLB CLB BUFFCLK

X4 BUFGLS 8 X8 X8 8 BUFGLS X8
FCLK1 BUFGLS 8 locals locals 8 BUFGLS FCLK4
locals locals
4 8
8 8

IOB CLB CLOCKS CLB CLOCKS IOB

IOB IOB
(PER COLUMN) (PER COLUMN)
CLOCKS CLOCKS
locals locals

locals locals
IOB CLB CLOCKS CLB CLOCKS IOB
IOB CLOCKS (PER COLUMN) (PER COLUMN) CLOCKS IOB
8 8
locals 4 8 locals
BUFGLS 8 locals locals 8 BUFGLS
FCLK2 BUFGLS 8 8 BUFGLS FCLK3
X4 X8 X8 X8

BUFFCLK CLB BUFFCLK

CLB
locals

locals

locals

locals

BUFGLS BUFGE BUFGE BUFGLS

BUFGE BUFGE

GCK2 GCK3 GCK4 GCK5

BUFGLS IOB IOB IOB IOB BUFGLS X6694

Figure 36: XC4000EX Global Net Distribution

4-42 September 18, 1996 (Version 1.04)

Global Nets and Buffers (XC4000EX only) Early and Global Low-Skew buffers share a common input;
they cannot be driven by two different signals.
Eight vertical longlines in each CLB column are driven by
special global buffers. These longlines are in addition to Choosing an XC4000EX Clock Buffer
the vertical longlines used for standard interconnect. The
global lines are broken in the center of the array, to allow The clocking structure of the XC4000EX provides a large
faster distribution and to minimize skew across the whole variety of features. However, it can be simple to use, with-
array. Each half-column global line has its own buffered out understanding all the details. The software automati-
multiplexer, as shown in Figure 36. The top and bottom glo- cally handles clocks, along with all other routing, when the
bal lines cannot be connected across the center of the appropriate clock buffer is placed in the design. In fact, if a
device, as this connection might introduce unacceptable buffer symbol called BUFG is placed, rather than a specific
skew. The top and bottom halves of the global lines must type of buffer, the software even chooses the buffer most
be separately driven — although they can be driven by the appropriate for the design. The detailed information in this
same global buffer. section is provided for those users who want a finer level of
control over their designs.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be If fine control is desired, use the following summary and
driven by internal logic, because they can be accessed by Table 17 on page 41 to choose an appropriate clock buffer.
single, double, and quad lines at the top, bottom, half, and • The simplest thing to do is to use a Global Low-Skew
quarter points. Consequently, the number of different buffer.
clocks that can be used simultaneously in an XC4000EX • If a faster clock path is needed, try a BUFG. The
device is very large. software will first try to use a Global Low-Skew Buffer. If
There are four global lines feeding the IOBs at the left edge timing requirements are not met, a faster buffer will
of the device. IOBs along the right edge have eight global automatically be used.
lines. There is a single global line along the top and bottom • If a single quadrant of the chip is sufficient for the
edges with access to the IOBs. All IOB global lines are bro- clocked logic, and the timing requires a faster clock than
ken at the center. They cannot be connected across the the Global Low-Skew buffer, use a Global Early buffer.
center of the device, as this connection might introduce • In special cases, where both external and internal
unacceptable skew. timing have been carefully studied, a FastCLK buffer
can be used, for the fastest possible I/O clock path.
IOB global lines can be driven from any of three types of
global buffers, or from local interconnect. Alternatively, top Global Low-Skew Buffers
and bottom IOBs can be clocked from the global lines in the Each corner of the XC4000EX device has two Global Low-
adjacent CLB column. Skew buffers. Any of the eight Global Low-Skew buffers
Three different types of clock buffers are available in the can drive any of the eight vertical Global lines in a column
XC4000EX: of CLBs. In addition, any of the buffers can drive any of the
four vertical lines accessing the IOBs on the left edge of the
• Global Low-Skew Buffers (BUFGLS)
device, and any of the eight vertical lines accessing the
• Global Early Buffers (BUFGE)
IOBs on the right edge of the device. (See Figure 37 on
• FastCLK Buffers (BUFFCLK)
page 44.)
Global Low-Skew Buffers are the standard clock buffers.
IOBs at the top and bottom edges of the device are
They should be used for most internal clocking, whenever a
accessed through the vertical Global lines in the CLB array,
large portion of the device must be driven.
as in the XC4000E. Any Global Low-Skew buffer can,
Global Early Buffers are designed to provide a faster clock therefore, access every IOB and CLB in the device.
access, but CLB access is limited to one-fourth of the
The Global Low-Skew buffers can be driven by either semi-
device. They also facilitate a faster I/O interface.
dedicated pads or internal logic.
FastCLK buffers are specifically designed to provide the
To use a Global Low-Skew buffer, place a BUFGLS ele-
fastest possible I/O clock. They have only the standard
ment in a schematic or in HDL code. If desired, attach a
input access to CLBs, through local interconnect.
LOC attribute or property to direct placement to the desig-
Figure 36 is a conceptual diagram of the global net struc- nated location. For example, attach a LOC=T attribute or
ture in the XC4000EX. property to direct that a BUFGLS be placed in one of the
Global Early buffers and Global Low-Skew buffers share a two Global Low-Skew buffers on the top edge of the device,
single pad. Therefore, the same IPAD symbol can drive or a LOC=TR to indicate the Global Low-Skew buffer on the
one buffer of each type, in parallel. This configuration is top edge of the device, on the right.
particularly useful when using the Fast Capture latches, as
described in “IOB Input Signals” on page 24. Paired Global

September 18, 1996 (Version 1.04) 4-43

XC4000 Series Field Programmable Gate Arrays

8 7 8 7
IOB IOB IOB IOB
1 6 1 6

I I I I
O CLB CLB O O CLB CLB O
B B B B

I I I I
O CLB CLB O
O CLB CLB O
B B
B B

2 5
2 5 IOB IOB
IOB IOB
3 4
3 4 X6751
X6753

Figure 37: Any BUFGLS (GCK1 - GCK8) Can Figure 38: Left and Right BUFGEs Can Drive Any or
Drive Any or All Clock Inputs on the Device All Clock Inputs in Same Quadrant or Edge (GCK1 is
shown. GCK2, GCK5 and GCK6 are similar.)
Global Early Buffers
The left-side Global Early buffers can each drive two of the
Each corner of the XC4000EX device has two Global Early
four vertical lines accessing the IOBs on the entire left edge
buffers. The primary purpose of the Global Early buffers is
of the device. The right-side Global Early buffers can each
to provide an earlier clock access than the potentially
drive two of the eight vertical lines accessing the IOBs on
heavily-loaded Global Low-Skew buffers. A clock source
the entire right edge of the device. (See Figure 38.)
applied to both buffers will result in the Global Early clock
edge occurring several nanoseconds earlier than the Glo- Each left and right Global Early buffer can also drive half of
bal Low-Skew buffer clock edge, due to the lighter loading. the IOBs along either the top or bottom edge of the device,
using a dedicated line that can only be accessed through
Global Early buffers also facilitate the fast capture of device
the Global Early buffers.
inputs, using the Fast Capture latches described in “IOB
Input Signals” on page 24. For Fast Capture, take a single The top and bottom Global Early buffers can drive half of
clock signal, and route it through both a Global Early buffer the IOBs along either the left or right edge of the device, as
and a Global Low-Skew buffer. (The two buffers share an shown in Figure 39. They can only access the top and bot-
input pad.) Use the Global Early buffer to clock the Fast tom IOBs via the CLB global lines.
Capture latch, and the Global Low-Skew buffer to clock the
normal input flip-flop or latch, as shown in Figure 18 on 8 7
page 26. IOB IOB
1 6
The Global Early buffers can also be used to provide a fast
Clock-to-Out on device output pins. However, an early I I
clock in the output flip-flop IOB must be taken into consid- O CLB CLB O
eration when calculating the internal clock speed for the B B
design.
The Global Early buffers at the left and right edges of the
chip have slightly different capabilities than the ones at the I I
top and bottom. Refer to Figure 38, Figure 39, and O CLB CLB O
Figure 36 on page 42 while reading the following explana- B B

tion.
2 5
Each Global Early buffer can access the eight vertical Glo- IOB IOB
bal lines for all CLBs in the quadrant. Therefore, only one- 3 4
X6747
fourth of the CLB clock pins can be accessed. This restric-
tion is in large part responsible for the faster speed of the Figure 39: Top and Bottom BUFGEs Can Drive Any
buffers, relative to the Global Low-Skew buffers. or All Clock Inputs in Same Quadrant (GCK8 is
shown. GCK3, GCK4 and GCK7 are similar.)

4-44 September 18, 1996 (Version 1.04)

The Global Early buffers can be driven by either semi-ded-
IOB IOB
icated pads or internal logic. They share pads with the Glo-
bal Low-Skew buffers, so a single net can drive both global
buffers, as described above.
I I
To use a Global Early buffer, place a BUFGE element in a 1 O CLB CLB O 4
schematic or in HDL code. If desired, attach a LOC B B
attribute or property to direct placement to the designated
location. For example, attach a LOC=T attribute or prop-
erty to direct that a BUFGE be placed in one of the two Glo-
bal Early buffers on the top edge of the device, or a I I
LOC=TR to indicate the Global Early buffer on the top edge 2 O CLB CLB O 3
B B
of the device, on the right.

FastCLK Buffers
IOB IOB
The fastest way to bring a clock into the XC4000EX device X6745

is through a FastCLK buffer. Two FastCLK buffers are Figure 40: Each BUFFCLK Can Drive Any or
present on the left edge, and two on the right edge, of the All Clock Inputs in Same Half-Edge (FCLK1 is shown.
XC4000EX die. There are no FastCLK buffers on the top or FCLK2, FCLK3 and FCLK4 are similar.)
bottom edges.
One purpose of the FastCLK buffers is to create a very fast The FastCLK buffers are limited to accessing IOBs on one-
pin-to-pin path by using the IOB 2-input function generator half of the die edge only, as shown in Figure 40 and
in conjunction with the FastCLK. Drive the F input of the Figure 36 on page 42. They can each drive two of the four
IOB function generator with the FastCLK buffer output, as vertical lines accessing the IOBs on the left edge of the
described in “IOB Output Signals” on page 27. device, or two of the eight vertical lines accessing the IOBs
on the right edge of the device. They can only access the
Alternatively, a FastCLK buffer can be used to minimize the CLB array through single- and double-length lines.
setup time of device inputs, if a positive hold time is accept-
able. Use the FastCLK buffer to clock the Fast Capture The FastCLK buffers must be driven by the semi-dedicated
latch, and a slower clock buffer to clock the standard IOB IOBs. They are not accessible from internal nets. Other
flip-flop or latch. Either the Global Early buffer or the Global than the FastCLK feature, these IOBs are identical to all
Low-Skew buffer can be used for the second storage ele- other IOBs.
ment, but whichever one is used should be the same clock To use a FastCLK buffer, place a BUFFCLK element in a
as the related internal logic. Since the FastCLK pads are schematic or in HDL code. If desired, attach a LOC
different from the Global Early and Global Low-Skew pads, attribute or property to direct placement to the designated
care must be taken to ensure that skew external to the location. For example, attach a LOC=LB attribute or prop-
device does not create internal timing difficulties. erty to direct that a BUFFCLK be placed on the left edge of
The FastCLK buffers can also be used to provide a fast the device at the bottom, or use LOC=L to indicate either of
Clock-to-Out on device output pins. However, a fast clock the buffers on the left edge.
in the output flip-flop IOB must be taken into consideration The input to the BUFFCLK symbol must be driven by a
when calculating the internal clock speed for the design. input pad symbol, such as IPAD, or by an input flip-flop or
latch, such as INFF, ILD, ILFFX, or ILFLX.

September 18, 1996 (Version 1.04) 4-45

XC4000 Series Field Programmable Gate Arrays

Power Distribution Pin Descriptions

Power for the FPGA is distributed through a grid to achieve There are three types of pins in the XC4000-Series
high noise immunity and isolation between logic and I/O. devices:
Inside the FPGA, a dedicated Vcc and Ground ring sur- • Permanently dedicated pins
rounding the logic array provides power to the I/O drivers, • User I/O pins that can have special functions
as shown in Figure 41. An independent matrix of Vcc and • Unrestricted user-programmable I/O pins.
Ground lines supplies the interior logic of the device.
Before and during configuration, all outputs not used for the
This power distribution grid provides a stable supply and configuration process are 3-stated with a 50 kΩ - 100 kΩ
ground for all internal logic, providing the external package pull-up resistor.
power pins are all connected and appropriately decoupled.
Typically, a 0.1 µF capacitor connected near the Vcc and After configuration, if an IOB is unused it is configured as
Ground pins of the package will provide adequate decou- an input with a 50 kΩ - 100 kΩ pull-up resistor.
pling. XC4000-Series devices have no dedicated Reset input.
Output buffers capable of driving/sinking the specified 12 Any user I/O can be configured to drive the Global Set/
mA (XC4000E) or 24 mA (XC4000EX) loads under speci- Reset net, GSR. See “Global Set/Reset” on page 13 for
fied worst-case conditions may be capable of driving/sink- more information on GSR.
ing up to 10 times as much current under best case XC4000-Series devices have no Powerdown control input,
conditions. as the XC3000 and XC2000 families do. The XC3000/
Noise can be reduced by minimizing external load capaci- XC2000 Powerdown control also 3-stated all of the device I/
tance and reducing simultaneous output transitions in the O pins. For XC4000-Series devices, use the global 3-state
same direction. It may also be beneficial to locate heavily net, GTS, instead. This net 3-states all outputs, but does
loaded output buffers near the Ground pads. The I/O Block not place the device in low-power mode. See “IOB Output
output buffers have a slew-rate limited mode (default) which Signals” on page 27 for more information on GTS.
should be used where output rise and fall times are not Device pins for XC4000-Series devices are described in
speed-critical. Table 18. Pin functions during configuration for each of the
seven configuration modes are summarized in Table 24 on
GND page 78, in the “Configuration Timing” section.

Ground and
Vcc Ring for
I/O Drivers

Vcc Vcc

Logic
Power Grid

GND X5422

Figure 41: XC4000-Series Power Distribution

4-46 September 18, 1996 (Version 1.04)

Table 18: Pin Descriptions

I/O I/O
During After
Pin Name Config. Config. Pin Description
Permanently Dedicated Pins
Eight or more (depending on package) connections to the nominal +5 V supply voltage
VCC I I (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled
with a 0.01 - 0.1 µF capacitor to Ground.
Eight or more (depending on package type) connections to Ground. All must be con-
GND I I
nected.
During configuration, Configuration Clock (CCLK) is an output in Master modes or Asyn-
chronous Peripheral mode, but is an input in Slave mode, Synchronous Peripheral
mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and
CCLK I or O I can be selected as the Readback Clock. There is no CCLK High time restriction on
XC4000-Series devices, except during Readback. See “Violating the Maximum High
and Low Time Specification for the Readback Clock” on page 65 for an explanation of
this exception.
DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it
indicates the completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the global logic initialization and the enabling of out-
DONE I/O O
puts.
The optional pull-up resistor is selected as an option in MakeBits, the XACTstep pro-
gram that creates the configuration bitstream. The resistor is included by default.
PROGRAM is an active Low input that forces the FPGA to clear its configuration mem-
ory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA
finishes the current clear cycle and executes another complete clear cycle, before it
PROGRAM I I
goes into a WAIT state and releases INIT.
The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled
up to Vcc.
User I/O Pins That Can Have Special Functions
During Peripheral mode configuration, this pin indicates when it is appropriate to write
another byte of data into the FPGA. The same status is also available on D7 in Asyn-
RDY/BUSY O I/O chronous Peripheral mode, if a read operation is performed when the device is selected.
After configuration, RDY/BUSY is a user-programmable I/O pin.
RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.
During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for
XC4000EX) is preceded by a rising edge on RCLK, a redundant output signal. RCLK
RCLK O I/O
is useful for clocked PROMs. It is rarely used during configuration. After configuration,
RCLK is a user-programmable I/O pin.
As Mode inputs, these pins are sampled after INIT goes High to determine the configu-
ration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1
can be used as a 3-state output. These three pins have no associated input or output
registers.
I (M0), During configuration, these pins have weak pull-up resistors. For the most popular con-
M0, M1, M2 I O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three
I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down re-
sistors. A pull-down resistor value of 4.7 kΩ is recommended.
These pins can only be used as inputs or outputs when called out by special schematic
definitions. To use these pins, place the library components MD0, MD1, and MD2 in-
stead of the usual pad symbols. Input or output buffers must still be used.

September 18, 1996 (Version 1.04) 4-47

XC4000 Series Field Programmable Gate Arrays

Table 18: Pin Descriptions (Continued)

I/O I/O
During After
Pin Name Config. Config. Pin Description
If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,
this pin is a 3-state output without a register, after configuration is completed.
TDO O O This pin can be user output only when called out by special schematic definitions. To
use this pin, place the library component TDO instead of the usual pad symbol. An out-
put buffer must still be used.
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
I/O
TDI, TCK, If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
I or I
TMS ited once configuration is completed, and these pins become user-programmable I/O.
(JTAG)
In this case, they must be called out by special schematic definitions. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
HDC O I/O a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
LDC O I/O control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
INIT I/O I/O
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay
PGCK1 - and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
PGCK4 Weak grammable I/O.
I or I/O
(XC4000E Pull-up The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
only) connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay
SGCK1 - and minimal skew. These internal global nets can also be driven from internal logic. If
SGCK4 Weak not used to drive a global net, any of these pins is a user-programmable I/O pin.
I or I/O
(XC4000E Pull-up The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
only) ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-
GCK1 - bal Early buffer. Each pair of global buffers can also be driven from internal logic, but
GCK8 Weak must share an input signal. If not used to drive a global buffer, any of these pins is a
I or I/O
(XC4000EX Pull-up user-programmable I/O.
only) Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol
is automatically placed on one of these pins.
Four FCLK inputs can each drive a FastCLK buffer. The FastCLK buffers cannot be
FCLK1 -
driven from internal logic. If not used to drive a global buffer, any of these pins is a user-
FCLK4 Weak
I or I/O programmable I/O.
(XC4000EX Pull-up
Any input pad symbol connected directly to the input of a BUFFCLK symbol is automat-
only)
ically placed on one of these pins.

4-48 September 18, 1996 (Version 1.04)

Table 18: Pin Descriptions (Continued)

I/O I/O
During After
Pin Name Config. Config. Pin Description
These four inputs are used in Asynchronous Peripheral mode. The chip is selected
when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe
(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low
CS0, CS1, on Read Strobe (RS) changes D7 into a status output — High if Ready, Low if Busy —
I I/O
WS, RS and drives D0 - D6 High.
In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.
WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write
Strobe overrides. After configuration, these are user-programmable I/O pins.
During Master Parallel configuration, these 18 output pins address the configuration
A0 - A17 O I/O
EPROM. After configuration, they are user-programmable I/O pins.
A18 - A21 During Master Parallel configuration with an XC4000EX master, these 4 output pins add
(XC4000EX O I/O 4 more bits to address the configuration EPROM. After configuration, they are user-pro-
only) grammable I/O pins.
During Master Parallel and Peripheral configuration, these eight input pins receive con-
D0 - D7 I I/O
figuration data. After configuration, they are user-programmable I/O pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
DIN I I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is
the D0 input. After configuration, DIN is a user-programmable I/O pin.
During configuration in any mode but Express mode, DOUT is the serial configuration
data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes
on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the
DOUT O I/O DIN input.
In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained
FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
These pins can be configured to be input and/or output after configuration is completed.
Weak
I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resis-
Pull-up
tor (50 kΩ - 100 kΩ) that defines the logic level as High.

September 18, 1996 (Version 1.04) 4-49

XC4000 Series Field Programmable Gate Arrays

Boundary Scan Data Registers

The ‘bed of nails’ has been the traditional method of testing The primary data register is the boundary scan register.
electronic assemblies. This approach has become less For each IOB pin in the FPGA, bonded or not, it includes
appropriate, due to closer pin spacing and more sophisti- three bits for In, Out and 3-State Control. Non-IOB pins
cated assembly methods like surface-mount technology have appropriate partial bit population for In or Out only.
and multi-layer boards. The IEEE Boundary Scan Stan- PROGRAM, CCLK and DONE are not included in the
dard 1149.1 was developed to facilitate board-level testing boundary scan register. Each EXTEST CAPTURE-DR
of electronic assemblies. Design and test engineers can state captures all In, Out, and 3-state pins.
imbed a standard test logic structure in their device to The data register also includes the following non-pin bits:
achieve high fault coverage for I/O and internal logic. This TDO.T, and TDO.O, which are always bits 0 and 1 of the
structure is easily implemented with a four-pin interface on data register, respectively, and BSCANT.UPD, which is
any boundary scan-compatible IC. IEEE 1149.1-compati- always the last bit of the data register. These three bound-
ble devices may be serial daisy-chained together, con- ary scan bits are special-purpose Xilinx test signals.
nected in parallel, or a combination of the two.
The other standard data register is the single flip-flop
The XC4000 Series implements IEEE 1149.1-compatible BYPASS register. It synchronizes data being passed
BYPASS, PRELOAD/SAMPLE and EXTEST boundary through the FPGA to the next downstream boundary scan
scan instructions. When the boundary scan configuration device.
option is selected, three normal user I/O pins become ded-
icated inputs for these functions. Another user output pin The FPGA provides two additional data registers that can
becomes the dedicated boundary scan output. The details be specified using the BSCAN macro. The FPGA provides
of how to enable this circuitry are covered later in this sec- two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
tion. the decodes of two user instructions. For these instruc-
tions, two corresponding pins (BSCAN.TDO1 and
By exercising these input signals, the user can serially load BSCAN.TDO2) allow user scan data to be shifted out on
commands and data into these devices to control the driv- TDO. The data register clock (BSCAN.DRCK) is available
ing of their outputs and to examine their inputs. This for control of test logic which the user may wish to imple-
method is an improvement over bed-of-nails testing. It ment with CLBs. The NAND of TCK and RUN-TEST-IDLE
avoids the need to over-drive device outputs, and it reduces is also provided (BSCAN.IDLE).
the user interface to four pins. An optional fifth pin, a reset
for the control logic, is described in the standard but is not Instruction Set
implemented in Xilinx devices.
The XC4000-Series boundary scan instruction set also
The dedicated on-chip logic implementing the IEEE 1149.1 includes instructions to configure the device and read back
functions includes a 16-state state machine, an instruction the configuration data. The instruction set is coded as
register and a number of data registers. The functional shown in Table 19.
details can be found in the IEEE 1149.1 specification and
Table 19: Boundary Scan Instructions
are also discussed in the Xilinx application note XAPP 017:
"Boundary Scan in XC4000 Devices." Instruction Test I/O Data
TDO Source
Figure 42 shows a simplified block diagram of the I2 I1 I0 Selected Source
XC4000E Input/Output Block with boundary scan imple- 0 0 0 EXTEST DR DR
mented. XC4000EX boundary scan logic is identical. 0 0 1 SAMPLE/ DR Pin/Logic
Figure 43 on page 52 is a diagram of the XC4000-Series PRELOAD
boundary scan logic. It includes three bits of Data Register 0 1 0 USER 1 BSCAN. User Logic
per IOB, the IEEE 1149.1 Test Access Port controller, and TDO1
the Instruction Register with decodes. 0 1 1 USER 2 BSCAN. User Logic
XC4000-Series devices can also be configured through the TDO2
boundary scan logic. See “Configuration Through the 1 0 0 READBACK Readback Pin/Logic
Boundary Scan Pins” on page 64. Data
1 0 1 CONFIGURE DOUT Disabled
1 1 0 Reserved — —
1 1 1 BYPASS Bypass —
Register

4-50 September 18, 1996 (Version 1.04)

 EXTEST SLEW PULL PULL
TS INV M RATE DOWN UP

TS/OE
3-State TS
TS - capture VCC
Boundary
Scan
TS - update
OUTPUT

INVERT
OUTPUT
M
sd
D Q
Ouput Data O
EC
M INVERT

Ouput Clock OK M PAD

rd OUT
M S/R SEL

O - capture
Clock Enable Boundary Q - capture
Scan
O - update

I - capture

Boundary
Scan
Input Data 1 I1
I - update
M M
sd
Q M M
D
EC Input Data 2 I2
DELAY QL
M INVERT
M
FLIP-FLOP/LATCH
Input Clock IK
rd
M S/R

INPUT

GLOBAL
S/R X5792

Figure 42: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown).
XC4000EX Boundary Scan Logic is Identical.

September 18, 1996 (Version 1.04) 4-51

XC4000 Series Field Programmable Gate Arrays

DATA IN

1 sd
D Q D Q
0

LE
1

IOB.Q 0

IOB.T 0
1 sd
D Q D Q 1
0

IOB IOB IOB IOB IOB LE

IOB IOB sd
1
D Q D Q
0
IOB IOB
LE

IOB IOB
1
IOB.I
0
IOB IOB

1 sd
IOB IOB D Q D Q
0

LE
IOB IOB
1

0
IOB IOB IOB.Q
BYPASS
REGISTER
IOB.T 0
M TDO
1 sd
INSTRUCTION REGISTER U 1
TDI D Q D Q
X 0

LE

M TDI
U INSTRUCTION REGISTER
TDO X

BYPASS 1 sd
REGISTER D Q D Q
IOB IOB 0

LE
IOB IOB

1
IOB IOB IOB.I
0

IOB IOB 1 sd
D Q D Q
0
IOB IOB
LE

IOB IOB 0

1
IOB IOB IOB.O

DATAOUT UPDATE EXTEST

IOB IOB IOB IOB IOB SHIFT/ CLOCK DATA

CAPTURE REGISTER

X1523

Figure 43: XC4000-Series Boundary Scan Logic

4-52 September 18, 1996 (Version 1.04)

Bit Sequence Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
The bit sequence within each IOB is: In, Out, 3-State. The inputs to be routed to internal logic. Care must be taken not
input-only M0 and M2 mode pins contribute only the In bit to force the chip into an undesired boundary scan state by
to the boundary scan I/O data register, while the output- inadvertently applying boundary scan input patterns to
only M1 pin contributes all three bits. these pins. The simplest way to prevent this is to keep TMS
The first two bits in the I/O data register are TDO.T and High, and then apply whatever signal is desired to TDI and
TDO.O, which can be used for the capture of internal sig- TCK.
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by Avoiding Inadvertent Boundary Scan
Xilinx for internal testing. Activation
From a cavity-up view of the chip (as shown in XDE or If TMS or TCK is used as user I/O, care must be taken to
Epic), starting in the upper right chip corner, the boundary ensure that at least one of these pins is held constant dur-
scan data-register bits are ordered as shown in Figure 44. ing configuration. In some applications, a situation may
The device-specific pinout tables for the XC4000 Series occur where TMS or TCK is driven during configuration.
include the boundary scan locations for each IOB pin. This may cause the device to go into boundary scan mode
BSDL (Boundary Scan Description Language) files for and disrupt the configuration process.
XC4000-Series devices are available on the Xilinx BBS. To prevent activation of boundary scan during configura-
tion, do either of the following:
Including Boundary Scan in a Schematic
• TMS: Tie High to put the Test Access Port controller
If boundary scan is only to be used during configuration, no in a benign RESET state
special schematic elements need be included in the sche- • TCK: Tie High or Low—don't toggle this clock input.
matic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user func- For more information regarding boundary scan, refer to the
tions after configuration. Xilinx Application Note XAPP 017.001, “Boundary Scan in
XC4000E Devices.“
To indicate that boundary scan remain enabled after config-
uration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 45.

Optional To User
Logic
Bit 0 ( TDO end) TDO.T
Bit 1 TDO.O IBUF
Bit 2
Top-edge IOBs (Right to Left) BSCAN
TDI TDI TDO TDO
Left-edge IOBs (Top to Bottom) TMS TMS DRCK

MD1.T TCK TCK IDLE

To User
MD1.O TDO1 SEL1 Logic
MD1.I From
MD0.I User Logic TDO2 SEL2
MD2.I X2675

Bottom-edge IOBs (Left to Right)

Figure 45: Boundary Scan Schematic Example
Right-edge IOBs (Bottom to Top)

(TDI end) B SCANT.UPD

X6075
Figure 44: Boundary Scan Bit Sequence

September 18, 1996 (Version 1.04) 4-53

XC4000 Series Field Programmable Gate Arrays

Configuration Table 20: Configuration Modes

Configuration is the process of loading design-specific pro- Mode M2 M1 M0 CCLK Data

gramming data into one or more FPGAs to define the func- Master Serial 0 0 0 output Bit-Serial
tional operation of the internal blocks and their Slave Serial 1 1 1 input Bit-Serial
interconnections. This is somewhat like loading the com- Master 1 0 0 output Byte-Wide,
mand registers of a programmable peripheral chip. Parallel Up increment
XC4000-Series devices use several hundred bits of config- from 00000
uration data per CLB and its associated interconnects.
Master 1 1 0 output Byte-Wide,
Each configuration bit defines the state of a static memory
Parallel Down decrement
cell that controls either a function look-up table bit, a multi-
from 3FFFF
plexer input, or an interconnect pass transistor. The XACT-
step development system translates the design into a Peripheral 0 1 1 input Byte-Wide
netlist file. It automatically partitions, places and routes the Synchronous*
logic and generates the configuration data in PROM format. Peripheral 1 0 1 output Byte-Wide
Asynchronous
Special Purpose Pins Express 0 1 0 input Byte-Wide
Three configuration mode pins (M2, M1, M0) are sampled (XC4000EX
prior to configuration to determine the configuration mode. only)
After configuration, these pins can be used as auxiliary Reserved 0 0 1 — —
connections. M2 and M0 can be used as inputs, and M1 Note: * Peripheral Synchronous can be considered byte-
can be used as an output. The XACTstep development wide Slave Parallel
system does not use these resources unless they are A detailed description of each configuration mode, with tim-
explicitly specified in the design entry. This is done by plac- ing information, is included later in this data sheet. During
ing a special pad symbol called MD2, MD1, or MD0 instead configuration, some of the I/O pins are used temporarily for
of the input or output pad symbol. the configuration process. All pins used during configura-
In XC4000-Series devices, the mode pins have weak pull- tion are shown in Table 24 on page 78.
up resistors during configuration. With all three mode pins
High, Slave Serial mode is selected, which is the most pop- Master Modes
ular configuration mode. Therefore, for the most common The three Master modes use an internal oscillator to gener-
configuration mode, the mode pins can be left uncon- ate a Configuration Clock (CCLK) for driving potential slave
nected. (Note, however, that the internal pull-up resistor devices. They also generate address and timing for exter-
value can be as high as 100 kΩ.) After configuration, these nal PROM(s) containing the configuration data.
pins can individually have weak pull-up or pull-down resis-
Master Parallel (Up or Down) modes generate the CCLK
tors, as specified in the design. A pull-down resistor value
signal and PROM addresses and receive byte parallel data.
of 4.7 kΩ is recommended.
The data is internally serialized into the FPGA data-frame
These pins are located in the lower left chip corner and are format. The up and down selection generates starting
near the readback nets. This location allows convenient addresses at either zero or 3FFFF, for compatibility with dif-
routing if compatibility with the XC2000 and XC3000 family ferent microprocessor addressing conventions. The Master
conventions of M0/RT, M1/RD is desired. Serial mode generates CCLK and receives the configura-
tion data in serial form from a Xilinx serial-configuration
Configuration Modes PROM.
XC4000E devices have six configuration modes. CCLK speed is selectable as either 1 MHz (default) or 8
XC4000EX devices have the same six modes, plus an MHz (up to 10% lower for low-voltage devices). Configura-
additional configuration mode. These modes are selected tion always starts at the default slow frequency, then can
by a 3-bit input code applied to the M2, M1, and M0 inputs. switch to the higher frequency during the first frame. Fre-
There are three self-loading Master modes, two Peripheral quency tolerance is -50% to +25%.
modes, and a Serial Slave mode, which is used primarily
for daisy-chained devices. The seventh mode, called Peripheral Modes
Express mode, is an additional slave mode that allows The two Peripheral modes accept byte-wide data from a
high-speed parallel configuration of the high-capacity bus. A RDY/BUSY status is available as a handshake sig-
XC4000EX devices. The coding for mode selection is nal. In Asynchronous Peripheral mode, the internal oscilla-
shown in Table 20. tor generates a CCLK burst signal that serializes the byte-
wide data. CCLK can also drive slave devices. In the syn-

4-54 September 18, 1996 (Version 1.04)

chronous mode, an externally supplied clock input to CCLK CCLK pulses until it reaches its finish point F. The different
serializes the data. families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
Slave Serial Mode the device does not really finish its configuration, although
In Slave Serial mode, the FPGA receives serial configura- DONE may have gone High, the outputs became active,
tion data on the rising edge of CCLK and, after loading its and the internal reset was released. For the XC4000-
configuration, passes additional data out, resynchronized Series device, not reaching F means that readback cannot
on the next falling edge of CCLK. be initiated and most boundary scan instructions cannot be
used.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices The user has some control over the relative timing of these
can be configured simultaneously. events and can, therefore, make sure that they occur at the
proper time and the finish point F is reached. Timing is con-
Serial Daisy Chain trolled using MakeBits options.
Multiple devices with different configurations can be con-
XC3000 Master with an XC4000-Series Slave
nected together in a “daisy chain,” and a single combined
bitstream used to configure the chain of slave devices. Some designers want to use an inexpensive lead device in
peripheral mode and have the more precious I/O pins of the
To configure a daisy chain of devices, wire the CCLK pins
XC4000-Series devices all available for user I/O. Figure 46
of all devices in parallel, as shown in Figure 55 on page 68.
provides a solution for that case.
Connect the DOUT of each device to the DIN of the next.
The lead or master FPGA and following slaves each This solution requires one CLB, one IOB and pin, and an
passes resynchronized configuration data coming from a internal oscillator with a frequency of up to 5 MHz as a
single source. The header data, including the length count, clock source. The XC3000 master device must be config-
is passed through and is captured by each FPGA when it ured with late Internal Reset, which is the default option.
recognizes the 0010 preamble. Following the length-count One CLB and one IOB in the lead XC3000-family device
data, each FPGA outputs a High on DOUT until it has are used to generate the additional CCLK pulse required by
received its required number of data frames. the XC4000-Series devices. When the lead device
After an FPGA has received its configuration data, it removes the internal RESET signal, the 2-bit shift register
passes on any additional frame start bits and configuration responds to its clock input and generates an active Low
data on DOUT. When the total number of configuration output signal for the duration of the subsequent clock
clocks applied after memory initialization equals the value period. An external connection between this output and
of the 24-bit length count, the FPGAs begin the start-up CCLK thus creates the extra CCLK pulse.
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configura-
Express Mode (XC4000EX only)
tion bit is received. Figure 49 on page 61 shows the start- Express mode is similar to Slave Serial mode, except the
up timing for an XC4000-Series device. data is presented in parallel format, and is clocked into the
target device a byte at a time rather than a bit at a time. The
The daisy-chained bitstream is not simply a concatenation
data is loaded in parallel into eight different columns: it is
of the individual bitstreams. The MakePROM program
not internally serialized. Eight bits of configuration data are
must be used to combine the bitstreams for a daisy-
loaded with every CCLK cycle, therefore this configuration
chained configuration.

Multi-Family Daisy Chain

All Xilinx FPGAs of the XC2000, XC3000, and XC4000
Series use a compatible bitstream format and can, there-
fore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. The lead
device must belong to the highest family in the chain. If the
OE/T
chain contains XC4000-Series devices, the master nor- Output
Connected
mally cannot be an XC2000 or XC3000 device. Reset to CCLK
0 0
The reason for this rule is shown in Figure 49 on page 61. 1 0 Active Low Output
1 1 Active High Output
Since all devices in the chain store the same length count 0 1
0 1
value and generate or receive one common sequence of . etc .
. . X5223
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of Figure 46: CCLK Generation for XC3000 Master
Figure 49. The master device then generates additional Driving an XC4000-Series Slave

September 18, 1996 (Version 1.04) 4-55

XC4000 Series Field Programmable Gate Arrays

mode runs at eight times the data rate of the other six Data Stream Format
modes. A length count is not used in Express mode.
The data stream (“bitstream”) format is identical for all con-
Express mode must be specified as an option to the Make- figuration modes, with the exception of Express mode. In
Bits program, which generates the bitstream. The Express Express mode, the device becomes active when DONE
mode bitstream is not compatible with the other six config- goes High, therefore no length count is required. Addition-
uration modes. ally, CRC error checking is not supported in Express mode.
Multiple slave devices with identical configurations can be The data stream formats are shown in Table 21. Express
wired with parallel D0-D7 inputs. In this way, multiple mode data is shown with D0 at the left and D7 at the right.
devices can be configured simultaneously. For all other modes, bit-serial data is read from left to right,
and byte-parallel data is effectively assembled from this
Pseudo Daisy Chain
serial bitstream, with the first bit in each byte assigned to
Multiple devices with different configurations can be con- D0.
nected together in a pseudo daisy chain, provided that all of
The configuration data stream begins with a string of eight
the devices are in Express mode. A single combined bit-
ones, a preamble code, followed by a 24-bit length count
stream is used to configure the chain of Express mode
and a separator field of ones (or 24 fill bits, in Express
devices, but the input data bus must drive D0-D7 of each
mode). This header is followed by the actual configuration
device. Tie High the CS1 pin of the first device to be con-
data in frames. The length and number of frames depends
figured. Connect the DOUT pin of each FPGA to the CS1
on the device type (see Table 22 and Table 23). Each
pin of the next device in the chain. The D0-D7 inputs are
frame begins with a start field and ends with an error check.
wired to each device in parallel. The DONE pins are wired
In all modes except Express mode, a postamble code is
together, with one or more internal DONE pull-ups acti-
required to signal the end of data for a single device. In all
vated. Alternatively, a 4.7 kΩ external resistor can be used,
cases, additional start-up bytes of data are required to pro-
if desired. (See Figure 63 on page 76.)
vide four clocks for the startup sequence at the end of con-
The requirement that all DONE pins in a daisy chain be figuration. Long daisy chains require additional startup
wired together applies only to Express mode, and only if all bytes to shift the last data through the chain. All startup
devices in the chain are to become active simultaneously. bytes are don’t-cares; these bytes are not included in bit-
All XC4000EX devices in Express mode are synchronized streams created by the Xilinx software.
to the DONE pin. User I/O for each device become active
Table 21: XC4000-Series Data Stream Formats
after the DONE pin for that device goes High. (The exact
timing is determined by MakeBits options.) Since the Express Mode All Other
DONE pin is open-drain and does not drive a High value, Data Type
(D0-D7) Modes (D0...)
tying the DONE pins of all devices together prevents all Fill Byte 11111111b 11111111b
devices in the chain from going High until the last device in
Preamble Code 11110010b 0010b
the chain has completed its configuration cycle.
Length Count FFFFFFh COUNT(23:0)
Because only XC4000EX and XC5200 devices support Fill Bits — 1111b
Express mode, only these devices can be used to form an
Start Field 11010010b 0b
Express mode daisy chain. XC5200 devices used in a
combined daisy chain with XC4000EX devices should be Data Frame DATA(n-1:0) DATA(n-1:0)
configured as synchronized to DONE (MakeBits option CRC or Constant 11010010b xxxx (CRC)
CCLK_SYNC or UCLK_SYNC), and their DONE pins wired Field Check or 0110b
together with those of the XC4000EX devices. Extend Write Cycle FFFFFFFFFFh —
Postamble — 01111111b
Setting CCLK Frequency Start-Up Bytes xxxxxxxxh xxh
For Master modes, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency LEGEND:
ranges from 0.5 MHz to 1.25 MHz (up to 10% lower for low- Unshaded Once per bitstream
voltage devices). In fast CCLK mode, the frequency ranges
Light Once per data frame
from 4 MHz to 10 MHz (up to 10% lower for low-voltage
devices). The frequency is selected by an option when run- Dark Once per device
ning MakeBits, the bitstream generation software tool. If an
XC4000-Series Master is driving an XC3000- or XC2000-
family slave, slow CCLK mode must be used. Slow mode is
the default.

4-56 September 18, 1996 (Version 1.04)

Table 22: XC4000E Program Data

Device XC4003E XC4005E/L XC4006E XC4008E XC4010E/L XC4013E/L XC4020E XC4025E

Max Logic Gates 3,000 5,000 6,000 8,000 10,000 13,000 20,000 25,000
CLBs 100 196 256 324 400 576 784 1,024
(Row x Col.) (10 x 10) (14 x 14) (16 x 16) (18 x 18) (20 x 20) (24 x 24) (28 x 28) (32 x 32)
IOBs 80 112 128 144 160 192 224 256
Flip-Flops 360 616 768 936 1,120 1,536 2,016 2,560
Horizontal 20 28 32 36 40 48 56 64
Longlines
TBUFs per 12 16 18 20 22 26 30 34
Longline
Bits per Frame 126 166 186 206 226 266 306 346
Frames 428 572 644 716 788 932 1,076 1,220
Program Data 53,936 94,960 119,792 147,504 178,096 247,920 329,264 422,128
PROM Size 53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176
(bits)
Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.

The MakeBits software creates the configuration bitstream. performs an identical calculation on the bitstream and com-
In Express mode, only non-CRC error checking is sup- pares the result with the received checksum.
ported. In all other modes, MakeBits allows a selection of Each data frame of the configuration bitstream has four
CRC or non-CRC error checking. The non-CRC error error bits at the end, as shown in Table 21. If a frame data
checking tests for a designated end-of-frame field for each error is detected during the loading of the FPGA, the con-
frame. For CRC error checking, MakeBits calculates a run- figuration process with a potentially corrupted bitstream is
ning CRC and inserts a unique four-bit partial check at the terminated. The FPGA pulls the INIT pin Low and goes into
end of each frame. The 11-bit CRC check of the last frame a Wait state.
of an FPGA includes the last seven data bits.
During Readback, 11 bits of the 16-bit checksum are added
Detection of an error results in the suspension of data load- to the end of the Readback data stream. The checksum is
ing and the pulling down of the INIT pin. In Master modes, computed using the CRC-16 CCITT polynomial, as shown
CCLK and address signals continue to operate externally. in Figure 47. The checksum consists of the 11 most signif-
The user must detect INIT and initialize a new configuration icant bits of the 16-bit code. A change in the checksum
by pulsing the PROGRAM pin Low or cycling Vcc. indicates a change in the Readback bitstream. A compari-
son to a previous checksum is meaningful only if the read-
Cyclic Redundancy Check (CRC) for
back data is independent of the current device state. CLB
Configuration and Readback outputs should not be included (Read Capture MakeBits
The Cyclic Redundancy Check is a method of error detec- option not used), and if RAM is present, the RAM content
tion in data transmission applications. Generally, the trans- must be unchanged.
mitting system performs a calculation on the serial Statistically, one error out of 2048 might go undetected.
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system

September 18, 1996 (Version 1.04) 4-57

XC4000 Series Field Programmable Gate Arrays

Table 23: XC4000EX Program Data

Device XC4028EX/XL XC4036EX/XL XC4044EX/XL XC4052XL XC4062XL

Max Logic Gates 28,000 36,000 44,000 52,000 62,000
CLBs 1,024 1,296 1,600 1,936 2,304
(Row x Col.) (32 x 32) (36 x 36) (40 x 40) (44 x 44) (48 x 48)
IOBs 256 288 320 352 384
Flip-Flops 2,560 3,168 3,840 4,576 5,376
Horizontal Longlines 192 216 240 264 288
TBUFs per Longline 34 38 42 46 50
Bits per Frame 421 469 517 565 613
Frames 1587 1775 1963 2151 2,339
Program Data 668,127 832,483 1,014,879 1,215,323 1,433,807
PROM Size (bits) 668,167 832,523 1,014,919 1,215,363 1,433,847
Notes: 1. Bits per Frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits
Number of Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
2. The user can add more “one” bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra “one”
bits, even for extra leading ones at the beginning of the header.
3. Express mode bitfiles are slightly larger (see Table 21).

X2 X15
X16
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SERIAL DATA IN

Polynomial: X16 + X15 + X2 + 1

1 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5
START BIT

LAST DATA FRAME CRC – CHECKSUM

X1789
Readback Data Stream
Figure 47: Circuit for Generating CRC-16

4-58 September 18, 1996 (Version 1.04)

Configuration Sequence
There are four major steps in the XC4000-Series power-up
VCC No
configuration sequence. Boundary Scan >3.5 V
Instructions
• Configuration Memory Clear Available:
Yes
• Initialization
• Configuration
Test M0 Generate
• Start-Up One Time-Out Pulse PROGRAM
of 16 or 64 ms = Low
The full process is illustrated in Figure 48. Yes

Configuration Memory Clear Keep Clearing

Configuration Memory
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic. EXTEST*
When Vcc reaches an operational level, and the circuit SAMPLE/PRELOAD Completely Clear
BYPASS Configuration Memory ~1.3 µs per Frame
passes the write and read test of a sample pair of configu- CONFIGURE* Once More
ration bits, a time delay is started. This time delay is nomi- (* if PROGRAM = High)

nally 16 ms, and up to 10% longer in the low-voltage

devices. The delay is four times as long when in Master INIT No
High? if
Modes (M0 Low), to allow ample time for all slaves to reach Master
a stable Vcc. When all INIT pins are tied together, as rec- Yes Master Waits 50 to 250 µs
ommended, the longest delay takes precedence. There- Before Sampling Mode Lines

fore, devices with different time delays can easily be mixed Sample
and matched in a daisy chain. Mode Lines

Master CCLK
This delay is applied only on power-up. It is not applied Goes Active
when reconfiguring an FPGA by pulsing the PROGRAM pin

LDC Output = L, HDC Output = H

Load One
Low. During this time delay, or as long as the PROGRAM Configuration
Data Frame
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
Frame Yes
lator. Error
Pull INIT Low
and Stop

At the end of each complete pass through the frame No

addressing, the power-on time-out delay circuitry and the
SAMPLE/PRELOAD Config-
level of the PROGRAM pin are tested. If neither is BYPASS uration No
asserted, the logic initiates one additional clearing of the memory
Full
configuration frames and then tests the INIT input. Yes

Initialization Pass
Configuration
During initialization and configuration, user pins HDC, LDC, Data to DOUT

INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and CCLK
HDC is held High starting at the initial application of power. Count Equals No
Length
The open drain INIT pin is released after the final initializa- Count
Yes
tion pass through the frame addresses. There is a deliber-
ate delay of 50 to 250 µs (up to 10% longer for low-voltage
Start-Up
devices) before a Master-mode device recognizes an inac- Sequence
tive INIT. Two internal clocks after the INIT pin is recognized F
I/O Active

as High, the FPGA samples the three mode lines to deter- Operational
EXTEST
mine the configuration mode. The appropriate interface SAMPLE PRELOAD
lines become active and the configuration preamble and BYPASS
USER 1 If Boundary Scan
data can be loaded. USER 2 is Selected
CONFIGURE
READBACK
X6076

Figure 48: Power-up Configuration Sequence

September 18, 1996 (Version 1.04) 4-59

XC4000 Series Field Programmable Gate Arrays

Configuration to make sure that any slaves in the optional daisy chain
have seen that INIT is High.
The 0010 preamble code, included for all modes except
Express mode, indicates that the following 24 bits repre- Start-Up
sent the length count. The length count is the total number
Start-up is the transition from the configuration process to
of configuration clocks needed to load the complete config-
the intended user operation. This transition involves a
uration data. (Four additional configuration clocks are
change from one clock source to another, and a change
required to complete the configuration process, as dis-
from interfacing parallel or serial configuration data where
cussed below.) After the preamble and the length count
most outputs are 3-stated, to normal operation with I/O pins
have been passed through to all devices in the daisy chain,
active in the user-system. Start-up must make sure that the
DOUT is held High to prevent frame start bits from reaching
user-logic ‘wakes up’ gracefully, that the outputs become
any daisy-chained devices. In Express mode, the length
active without causing contention with the configuration sig-
count bits are ignored, and DOUT is held Low, to disable
nals, and that the internal flip-flops are released from the
the next device in the pseudo daisy chain.
global Reset or Set at the right time.
A specific configuration bit, early in the first frame of a mas-
Figure 49 describes start-up timing for the three Xilinx fam-
ter device, controls the configuration-clock rate and can
ilies in detail. Express mode configuration always uses
increase it by a factor of eight. Therefore, if a fast configu-
either CCLK_SYNC or UCLK_SYNC timing, the other con-
ration clock is selected by the bitstream, the slower clock
figuration modes can use any of the four timing sequences.
rate is used until this configuration bit is detected.
To access the internal start-up signals, place the STARTUP
Each frame has a start field followed by the frame-configu-
library symbol.
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error Start-up Timing
by pulling the open-drain INIT pin Low. After all configura-
tion frames have been loaded into an FPGA, DOUT again Different FPGA families have different start-up sequences.
follows the input data so that the remaining data is passed The XC2000 family goes through a fixed sequence. DONE
on to the next device. In Express mode, when the first goes High and the internal global Reset is de-activated one
device is fully programmed, DOUT goes High to enable the CCLK period after the I/O become active.
next device in the chain.
The XC3000A family offers some flexibility. DONE can be
Delaying Configuration After Power-Up programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
There are two methods of delaying configuration after
global Reset is de-activated one CCLK period before or
power-up: put a logic Low on the PROGRAM input, or pull
after the I/O become active.
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 48 on page 59.) The XC4000 Series offers additional flexibility. The three
events — DONE going High, the internal Set/Reset being
A Low on the PROGRAM input is the more radical
de-activated, and the user I/O going active — can all occur
approach, and is recommended when the power-supply
in any arbitrary sequence. Each of them can occur one
rise time is excessive or poorly defined. As long as PRO-
CCLK period before or after, or simultaneous with, any of
GRAM is Low, the FPGA keeps clearing its configuration
the others. This relative timing is selected by means of soft-
memory. When PROGRAM goes High, the configuration
ware options in MakeBits, the bitstream generation soft-
memory is cleared one more time, followed by the begin-
ware.
ning of configuration, provided the INIT input is not exter-
nally held Low. Note that a Low on the PROGRAM input The default option, and the most practical one, is for DONE
automatically forces a Low on the INIT output. The to go High first, disconnecting the configuration data source
XC4000-Series PROGRAM pin has a permanent weak and avoiding any contention when the I/Os become active
pull-up. one clock later. Reset/Set is then released another clock
period later to make sure that user-operation starts from
Using an open-collector or open-drain driver to hold INIT
stable internal conditions. This is the most common
Low before the beginning of configuration causes the
sequence, shown with heavy lines in Figure 49, but the
FPGA to wait after completing the configuration memory
designer can modify it to meet particular requirements.
clear operation. When INIT is no longer held Low exter-
nally, the device determines its configuration mode by cap- Normally, the start-up sequence is controlled by the internal
turing its mode pins, and is ready to start the configuration device oscillator output (CCLK), which is asynchronous to
process. A master device waits up to an additional 250 µs the system clock.

4-60 September 18, 1996 (Version 1.04)

 Length Count Match
CCLK Period

CCLK
F
DONE

I/O
XC2000

Global Reset

F = Finished, no more
F
configuration clocks needed
DONE Daisy-chain lead device
XC3000 must have latest F
I/O
Heavy lines describe
default timing
Global Reset

F
DONE
C1 C2 C3 C4

XC4000E/EX I/O
CCLK_NOSYNC
C2 C3 C4

GSR Active
C2 C3 C4
DONE IN
F
DONE

C1, C2 or C3
XC4000E/EX I/O
CCLK_SYNC
Di Di+1

GSR Active
Di Di+1
F

DONE
C1 U2 U3 U4
I/O
XC4000E/EX
UCLK_NOSYNC U2 U3 U4

GSR Active
U2 U3 U4
DONE IN
F
DONE
C1 U2
I/O
XC4000E/EX
UCLK_SYNC Di Di+1 Di+2

GSR Active
Di Di+1 Di+2
Synchronization
Uncertainty UCLK Period

X6700

Figure 49: Start-up Timing

September 18, 1996 (Version 1.04) 4-61

XC4000 Series Field Programmable Gate Arrays

The XC4000 Series offers another start-up clocking option, Start-up from CCLK
UCLK_NOSYNC. The three events described above need If CCLK is used to drive the start-up, Q0 through Q3 pro-
not be triggered by CCLK. They can, as a configuration vide the timing. Heavy lines in Figure 49 show the default
option, be triggered by a user clock. This means that the timing, which is compatible with XC2000 and XC3000
device can wake up in synchronism with the user system. devices using early DONE and late Reset. The thin lines
When the UCLK_SYNC option is enabled, the user can indicate all other possible timing options.
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until Start-up from a User Clock (STARTUP.CLK)
DONE is released and has gone High. This option can be When, instead of CCLK, a user-supplied start-up clock is
used to force synchronization of several FPGAs to a com- selected, Q1 is used to bridge the unknown phase relation-
mon user clock, or to guarantee that all devices are suc- ship between CCLK and the user clock. This arbitration
cessfully configured before any I/Os go active. causes an unavoidable one-cycle uncertainty in the timing
If either of these two options is selected, and no user clock of the rest of the start-up sequence.
is specified in the design or attached to the device, the chip DONE Goes High to Signal End of Configuration
could reach a point where the configuration of the device is
complete and the Done pin is asserted, but the outputs do In all configuration modes except Express mode, XC4000-
not become active. The solution is either to recreate the bit- Series devices read the expected length count from the bit-
stream specifying the start-up clock as CCLK, or to supply stream and store it in an internal register. The length count
the appropriate user clock. varies according to the number of devices and the compo-
sition of the daisy chain. Each device also counts the num-
Start-up Sequence ber of CCLKs during configuration.
The Start-up sequence begins when the configuration Two conditions have to be met in order for the DONE pin to
memory is full, and the total number of configuration clocks go high:
received since INIT went High equals the loaded value of
• the chip's internal memory must be full, and
the length count.
• the configuration length count must be met, exactly.
The next rising clock edge sets a flip-flop Q0, shown in
This is important because the counter that determines
Figure 50. Q0 is the leading bit of a 5-bit shift register. The
when the length count is met begins with the very first
outputs of this register can be programmed to control three
CCLK, not the first one after the preamble.
events.
Therefore, if a stray bit is inserted before the preamble, or
• The release of the open-drain DONE output
the data source is not ready at the time of the first CCLK,
• The change of configuration-related pins to the user
the internal counter that holds the number of CCLKs will be
function, activating all IOBs.
one ahead of the actual number of data bits read. At the
• The termination of the global Set/Reset initialization of
end of configuration, the configuration memory will be full,
all CLB and IOB storage elements.
but the number of bits in the internal counter will not match
The DONE pin can also be wire-ANDed with DONE pins of the expected length count.
other FPGAs or with other external signals, and can then
As a consequence, a Master mode device will continue to
be used as input to bit Q3 of the start-up register. This is
send out CCLKs until the internal counter turns over to
called “Start-up Timing Synchronous to Done In” and is
zero, and then reaches the correct length count a second
selected by the CCLK_SYNC and UCLK_SYNC MakeBits
time. This will take several seconds [224 ∗ CCLK period] —
options.
which is sometimes interpreted as the device not configur-
When DONE is not used as an input, the operation is called ing at all.
“Start-up Timing Not Synchronous to DONE In,” and is
If it is not possible to have the data ready at the time of the
selected by the CCLK_NOSYNC and UCLK_NOSYNC
first CCLK, the problem can be avoided by increasing the
MakeBits options.
number in the length count by the appropriate value. The
As a configuration option, the start-up control register XACT User Guide includes detailed information about man-
beyond Q0 can be clocked either by subsequent CCLK ually altering the length count.
pulses or from an on-chip user net called STARTUP.CLK.
In Express mode, there is no length count. The DONE pin
These signals can be accessed by placing the STARTUP
for each device goes High when the device has received its
library symbol.
quota of configuration data. Wiring the DONE pins of sev-
eral devices together delays start-up of all devices until all
are fully configured.

4-62 September 18, 1996 (Version 1.04)

 Q3 Q1/Q4
STARTUP DONE
Q2
IN

* IOBs OPERATIONAL PER CONFIGURATION

* GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP

1
0

GSR ENABLE
GSR INVERT
STARTUP.GSR CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
STARTUP.GTS LIBRARIES GUIDE)
GTS INVERT
GTS ENABLE

0
GLOBAL 3-STATE OF ALL IOBs
1

Q S

* DONE

" FINISHED "

1 1 ENABLES BOUNDARY
0 0 SCAN, READBACK AND
CONTROLS THE OSCILLATOR

Q0 Q1 Q2 Q3 Q4

FULL 1
LENGTH COUNT S Q D Q D Q D Q D Q
0

K K K * K K

CLEAR MEMORY

CCLK 0
STARTUP.CLK 1
USER NET

M
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
* * X1528

Figure 50: Start-up Logic

Note that DONE is an open-drain output and does not go Release of Global Set/Reset After DONE Goes
High unless an internal pull-up is activated or an external High
pull-up is attached. The internal pull-up is activated as the
By default, Global Set/Reset (GSR) is released two CCLK
default by MakeBits, the bitstream generation software.
cycles after the DONE pin goes High. If CCLK is not
Release of User I/O After DONE Goes High clocked twice after DONE goes High, all flip-flops are held
in their initial set or reset state. The delay from DONE High
By default, the user I/O are released one CCLK cycle after
to GSR inactive is controlled by a MakeBits option.
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state — Configuration Complete After DONE Goes High
3-stated, with a 50 kΩ - 100 kΩ pull-up. The delay from
Three full CCLK cycles are required after the DONE pin
DONE High to active user I/O is controlled by a MakeBits
goes High, as shown in Figure 49 on page 61. If CCLK is
option.
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.

September 18, 1996 (Version 1.04) 4-63

XC4000 Series Field Programmable Gate Arrays

Configuration Through the Boundary Scan Readback

Pins The user can read back the content of configuration mem-
XC4000-Series devices can be configured through the ory and the level of certain internal nodes without interfer-
boundary scan pins. The basic procedure is as follows: ing with the normal operation of the device.
• Power up the FPGA with INIT held Low (or drive the Readback not only reports the downloaded configuration
PROGRAM pin Low for more than 300 ns followed by a bits, but can also include the present state of the device,
High while holding INIT Low). Holding INIT Low allows represented by the content of all flip-flops and latches in
enough time to issue the CONFIG command to the CLBs and IOBs, as well as the content of function genera-
FPGA. The pin can be used as I/O after configuration if tors used as RAMs.
a resistor is used to hold INIT Low. Note that in XC4000-Series devices, configuration data is
• Issue the CONFIG command to the TMS input not inverted with respect to configuration as it is in XC2000
• Wait for INIT to go High and XC3000 families.
• Sequence the boundary scan Test Access Port to the
SHIFT-DR state Readback of Express mode bitstreams results in data that
• Toggle TCK to clock data into TDI pin. does not resemble the original bitstream, because the bit-
stream format differs from other modes.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count XC4000-Series Readback does not use any dedicated
compare. pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
For more detailed information, refer to the Xilinx application To access the internal Readback signals, place the READ-
note XAPP017, “Boundary Scan in XC4000 Devices.” This BACK library symbol and attach the appropriate pad sym-
application note also applies to XC4000E and XC4000EX bols, as shown in Figure 51.
devices.
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.

IF UNCONNECTED,
DEFAULT IS CCLK

CLK DATA READ_DATA

MD1
READBACK OBUF
READ_TRIGGER TRIG RIP
MD0
IBUF X1786

Figure 51: Readback Schematic Example

4-64 September 18, 1996 (Version 1.04)

Readback Options
Readback options are: Read Capture, Read Abort, and I/O I/O
Clock Select. They are set with MakeBits, the bitstream PROGRAMMABLE
generation software. INTERCONNECT

Read Capture

DATA
When the Read Capture option is selected, the readback

TRIG

RIP
data stream includes sampled values of CLB and IOB sig-

I
rdbk I/O I/O I/O rdclk
nals. The rising edge of RDBK.TRIG latches the inverted
values of the four CLB outputs, the IOB output flip-flops and
X1787
the input signals I1 and I2. Note that while the bits describ-
ing configuration (interconnect, function generators, and Figure 52: READBACK Symbol in Graphical Editor
RAM content) are not inverted, the CLB and IOB output sig-
nals are inverted.
When the Read Capture option is not selected, the values Violating the Maximum High and Low Time
of the capture bits reflect the configuration data originally Specification for the Readback Clock
written to those memory locations.
The readback clock has a maximum High and Low time
If the RAM capability of the CLBs is used, RAM data are specification. In some cases, this specification cannot be
available in readback, since they directly overwrite the F met. For example, if a processor is controlling readback, an
and G function-table configuration of the CLB. interrupt may force it to stop in the middle of a readback.
RDBK.TRIG is located in the lower-left corner of the device, This necessitates stopping the clock, and thus violating the
as shown in Figure 52. specification.
The specification is mandatory only on clocking data at the
Read Abort
end of a frame prior to the next start bit. The transfer mech-
When the Read Abort option is selected, a High-to-Low anism will load the data to a shift register during the last six
transition on RDBK.TRIG terminates the readback opera- clock cycles of the frame, prior to the start bit of the follow-
tion and prepares the logic to accept another trigger. ing frame. This loading process is dynamic, and is the
After an aborted readback, additional clocks (up to one source of the maximum High and Low time requirements.
readback clock per configuration frame) may be required to Therefore, the specification only applies to the six clock
re-initialize the control logic. The status of readback is indi- cycles prior to and including any start bit, including the
cated by the output control net RDBK.RIP. RDBK.RIP is clocks before the first start bit in the readback data stream.
High whenever a readback is in progress. At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
Clock Select like a regular shift register.
CCLK is the default clock. However, the user can insert The user must precisely calculate the location of the read-
another clock on RDBK.CLK. Readback control and data back data relative to the frame. The system must keep
are clocked on rising edges of RDBK.CLK. If readback track of the position within a data frame, and disable inter-
must be inhibited for security reasons, the readback control rupts before frame boundaries. Frame lengths and data
nets are simply not connected. formats are listed in Table 21, Table 22 and Table 23.
RDBK.CLK is located in the lower right chip corner, as
shown in Figure 52. Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
Logic Probe uses the readback feature for bitstream verifi-
cation. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-cir-
cuit emulator.

September 18, 1996 (Version 1.04) 4-65

XC4000 Series Field Programmable Gate Arrays

Configuration Timing In MakeBits, the user can specify Fast ConfigRate, which,
starting several bits into the first frame, increases the CCLK
The seven configuration modes are discussed in detail in frequency by a factor of eight. The value increases from
this section. Timing specifications are included. between 0.5 and 1.25 MHz, to a value between 4 and 10
MHz. (For low-voltage devices, the frequency can be up to
Master Serial Mode 10% lower.) Be sure that the serial PROM and slaves are
In Master Serial mode, the CCLK output of the lead FPGA fast enough to support this data rate. XC2000, XC3000/A,
drives a Xilinx Serial PROM that feeds the FPGA DIN input. and XC3100A devices do not support the Fast ConfigRate
Each rising edge of the CCLK output increments the Serial option.
PROM internal address counter. The next data bit is put on The SPROM CE input can be driven from either LDC or
the SPROM data output, connected to the FPGA DIN pin. DONE. Using LDC avoids potential contention on the DIN
The lead FPGA accepts this data on the subsequent rising pin, if this pin is configured as user-I/O, but LDC is then
CCLK edge. restricted to be a permanently High user output after con-
The lead FPGA then presents the preamble data—and all figuration. Using DONE can also avoid contention on DIN,
data that overflows the lead device—on its DOUT pin. provided the early DONE option is invoked.
There is an internal pipeline delay of 1.5 CCLK periods, Figure 53 shows a full master/slave system. The leftmost
which means that DOUT changes on the falling CCLK device is in Master Serial mode.
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge. Master Serial mode is selected by a <000> on the mode
pins (M2, M1, M0).

NOTE: NOTE:
M2, M1, M0 can be shorted M2, M1, M0 can be shorted
to Ground if not used as I/O to VCC if not used as I/O
VCC
N/C
4.7 KΩ 4.7 KΩ 4.7 KΩ 4.7 KΩ 4.7 KΩ
4.7 KΩ

M0 M1 M0 M1 M0 M1 PWRDN
M2 N/C M2 M2

DOUT DIN DOUT DIN DOUT

VCC CCLK CCLK

XC4000E/EX
MASTER XC1700D +5 V XC4000E/EX, XC3100A
4.7 KΩ
SERIAL XC5200 SLAVE
CCLK CLK VPP SLAVE
DIN DATA

PROGRAM LDC CE CEO PROGRAM RESET

DONE INIT RESET/OE DONE INIT D/P INIT

(Low Reset Option Used)

PROGRAM X6608

Figure 53: Master Serial Mode Circuit Diagram

4-66 September 18, 1996 (Version 1.04)

 CCLK
(Output)

2 TCKDS

1 TDSCK

Serial Data In n n+1 n+2

Serial DOUT n–3 n–2 n–1 n

(Output)

X3223

Description Symbol Min Max Units

DIN setup 1 TDSCK 20 ns
CCLK
DIN hold 2 TCKDS 0 ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. Master Serial mode timing is based on testing in slave mode.

Figure 54: Master Serial Mode Programming Switching Characteristics

September 18, 1996 (Version 1.04) 4-67

XC4000 Series Field Programmable Gate Arrays

Slave Serial Mode the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must Figure 55 shows a full master/slave system. An XC4000-
be available at the DIN input of the lead FPGA a short setup Series device in Slave Serial mode should be connected as
time before each rising CCLK edge. shown in the third device from the left.

The lead FPGA then presents the preamble data—and all Slave Serial mode is selected by a <111> on the mode pins
data that overflows the lead device—on its DOUT pin. (M2, M1, M0). Slave Serial is the default mode if the mode
There is an internal delay of 0.5 CCLK periods, which pins are left unconnected, as they have weak pull-up resis-
means that DOUT changes on the falling CCLK edge, and tors during configuration.

NOTE: NOTE:
M2, M1, M0 can be shorted M2, M1, M0 can be shorted
to Ground if not used as I/O to VCC if not used as I/O
VCC
N/C
4.7 KΩ 4.7 KΩ 4.7 KΩ 4.7 KΩ 4.7 KΩ
4.7 KΩ

M0 M1 M0 M1 M0 M1 PWRDN
M2 N/C M2 M2

DOUT DIN DOUT DIN DOUT

CCLK CCLK
XC4000E/EX VCC
MASTER XC1700D +5 V XC4000E/EX, XC3100A
4.7 KΩ
SERIAL XC5200 SLAVE
CCLK CLK VPP SLAVE
DIN DATA

PROGRAM LDC CE CEO PROGRAM RESET

DONE INIT RESET/OE DONE INIT D/P INIT

(Low Reset Option Used)

PROGRAM X6608

Figure 55: Slave Serial Mode Circuit Diagram

4-68 September 18, 1996 (Version 1.04)

 DIN Bit n Bit n + 1

1 TDCC 2 TCCD 5 TCCL

CCLK

4 TCCH 3 TCCO

DOUT
Bit n - 1 Bit n
(Output)
X5379

Description Symbol Min Max Units

DIN setup 1 TDCC 20 ns
DIN hold 2 TCCD 0 ns
DIN to DOUT 3 TCCO 30 ns
CCLK
High time 4 TCCH 45 ns
Low time 5 TCCL 45 ns
Frequency FCC 10 MHz
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 56: Slave Serial Mode Programming Switching Characteristics

September 18, 1996 (Version 1.04) 4-69

XC4000 Series Field Programmable Gate Arrays

Master Parallel Modes The PROM address pins can be incremented or decre-
mented, depending on the mode pin settings. This option
In the two Master Parallel modes, the lead FPGA directly allows the FPGA to share the PROM with a wide variety of
addresses an industry-standard byte-wide EPROM, and microprocessors and microcontrollers. Some processors
accepts eight data bits just before incrementing or decre- must boot from the bottom of memory (all zeros) while oth-
menting the address outputs. ers must boot from the top. The FPGA is flexible and can
The eight data bits are serialized in the lead FPGA, which load its configuration bitstream from either end of the mem-
then presents the preamble data—and all data that over- ory.
flows the lead device—on its DOUT pin. There is an inter- Master Parallel Up mode is selected by a <100> on the
nal delay of 1.5 CCLK periods, after the rising CCLK edge mode pins (M2, M1, M0). The EPROM addresses start at
that accepts a byte of data (and also changes the EPROM 00000 and increment.
address) until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT Master Parallel Down mode is selected by a <110> on the
changes on the falling CCLK edge, and the next FPGA in mode pins. The EPROM addresses start at 3FFFF and
the daisy chain accepts data on the subsequent rising decrement.
CCLK edge.

HIGH TO DIN OF OPTIONAL

or DAISY-CHAINED FPGAS
4.7KΩ N/C
LOW

N/C
M0 M1 M2 TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
CCLK
DOUT
NOTE:M0 can be shorted
to Ground if not used A17 ... M0 M1 M2
as I/O.
A16 ... DIN DOUT
VCC
A15 ... EPROM
(8K x 8) CCLK
A14 ...
4.7KΩ (OR LARGER)
USER CONTROL OF HIGHER
INIT A13 ...
ORDER PROM ADDRESS BITS XC4000E/EX
CAN BE USED TO SELECT BETWEEN SLAVE
A12 A12
ALTERNATIVE CONFIGURATIONS
A11 A11
PROGRAM
A10 A10

PROGRAM A9 A9
DONE INIT
D7 A8 A8

D6 A7 A7 D7

D5 A6 A6 D6

D4 A5 A5 D5

D3 A4 A4 D4

D2 A3 A3 D3

D1 A2 A2 D2

D0 A1 A1 D1

A0 A0 D0

DONE OE

CE

DATA BUS 8

PROGRAM

X6697

Figure 57: Master Parallel Mode Circuit Diagram

4-70 September 18, 1996 (Version 1.04)

 A0-A17
(output) Address for Byte n Address for Byte n + 1

1 TRAC

D0-D7
Byte

2 TDRC 3 TRCD

RCLK
(output)

7 CCLKs CCLK

CCLK
(output)

DOUT
(output) D6 D7

Byte n - 1 X6078

Description Symbol Min Max Units

Delay to Address valid 1 TRAC 0 200 ns
RCLK Data setup time 2 TDRC 60 ns
Data hold time 3 TRCD 0 ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vcc is valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 58: Master Parallel Mode Programming Switching Characteristics

September 18, 1996 (Version 1.04) 4-71

XC4000 Series Field Programmable Gate Arrays

Synchronous Peripheral Mode The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
Synchronous Peripheral mode can also be considered its DOUT pin. There is an internal delay of 1.5 CCLK peri-
Slave Parallel mode. An external signal drives the CCLK ods, which means that DOUT changes on the falling CCLK
input(s) of the FPGA(s). The first byte of parallel configura- edge, and the next FPGA in the daisy chain accepts data
tion data must be available at the Data inputs of the lead on the subsequent rising CCLK edge.
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con- In order to complete the serial shift operation, 10 additional
secutive rising CCLK edge. CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisy-
The same CCLK edge that accepts data, also causes the chained device.
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is Synchronous Peripheral mode is selected by a <011> on
really an ACKNOWLEDGE signal. Synchronous operation the mode pins (M2, M1, M0).
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.

NOTE:
M2 can be shorted to Ground
if not used as I/O

N/C 4.7 kΩ N/C

M0 M1 M2 M0 M1 M2
CLOCK CCLK CCLK
OPTIONAL
8 DAISY-CHAINED
DATA BUS D0-7 FPGAs
DOUT DIN DOUT

VCC XC4000E/EX XC4000E/EX

SYNCHRO- SLAVE
NOUS
4.7 kΩ
PERIPHERAL

CONTROL RDY/BUSY
SIGNALS INIT DONE INIT DONE
4.7 kΩ

PROGRAM PROGRAM PROGRAM

X5996

Figure 59: Synchronous Peripheral Mode Circuit Diagram

4-72 September 18, 1996 (Version 1.04)

 CCLK

INIT
BYTE BYTE
0 1

BYTE 0 OUT BYTE 1 OUT

DOUT 0 1 2 3 4 5 6 7 0 1

RDY/BUSY

X6096

Description Symbol Min Max Units

INIT (High) setup time TIC 5 µs
D0 - D7 setup time TDC 60 ns
D0 - D7 hold time TCD 0 ns
CCLK
CCLK High time TCCH 50 ns
CCLK Low time TCCL 60 ns
CCLK Frequency FCC 8 MHz
Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.

Figure 60: Synchronous Peripheral Mode Programming Switching Characteristics

September 18, 1996 (Version 1.04) 4-73

XC4000 Series Field Programmable Gate Arrays

Asynchronous Peripheral Mode The READY/BUSY handshake can be ignored if the delay
from any one Write to the end of the next Write is guaran-
Write to FPGA teed to be longer than 10 CCLK periods.
Asynchronous Peripheral mode uses the trailing edge of Status Read
the logic AND condition of WS and CS0 being Low and RS
and CS1 being High to accept byte-wide data from a micro- The logic AND condition of the CS0, CS1and RS inputs
processor bus. In the lead FPGA, this data is loaded into a puts the device status on the Data bus.
double-buffered UART-like parallel-to-serial converter and • D7 High indicates Ready
is serially shifted into the internal logic. • D7 Low indicates Busy
The lead FPGA presents the preamble data (and all data • D0 through D6 go unconditionally High
that overflows the lead device) on its DOUT pin. The RDY/ It is mandatory that the whole start-up sequence be started
BUSY output from the lead FPGA acts as a handshake sig- and completed by one byte-wide input. Otherwise, the pins
nal to the microprocessor. RDY/BUSY goes Low when a used as Write Strobe or Chip Enable might become active
byte has been received, and goes High again when the outputs and interfere with the final byte transfer. If this
byte-wide input buffer has transferred its information into transfer does not occur, the start-up sequence is not com-
the shift register, and the buffer is ready to receive new pleted all the way to the finish (point F in Figure 49 on page
data. A new write may be started immediately, as soon as 61).
the RDY/BUSY output has gone Low, acknowledging
receipt of the previous data. Write may not be terminated In this case, at worst, the internal reset is not released. At
until RDY/BUSY is High again for one CCLK period. Note best, Readback and Boundary Scan are inhibited. The
that RDY/BUSY is pulled High with a high-impedance pull- length-count value, as generated by MakeBits and
up prior to INIT going High. MakePROM, ensures that these problems never occur.

The length of the BUSY signal depends on the activity in Although RDY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
the UART. If the shift register was empty when the new
one of the data lines. For this purpose, D7 represents the
byte was received, the BUSY signal lasts for only two CCLK
RDY/BUSY status when RS is Low, WS is High, and the
periods. If the shift register was still full when the new byte
two chip select lines are both active.
was received, the BUSY signal can be as long as nine
CCLK periods. Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, M0).
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.

N/C
N/C N/C
4.7 kΩ

M0 M1 M2 M0 M1 M2

DATA 8
D0–7 CCLK CCLK
BUS
OPTIONAL
DAISY-CHAINED
FPGAs
DOUT DIN DOUT
VCC ADDRESS CS0
ADDRESS DECODE XC4000E/EX
...

BUS LOGIC
ASYNCHRO- XC4000E/EX
NOUS SLAVE
4.7 kΩ
PERIPHERAL
4.7 kΩ CS1

RS

WS

CONTROL RDY/BUSY
SIGNALS
INIT INIT

DONE DONE
REPROGRAM
PROGRAM PROGRAM
4.7 kΩ

X6696

Figure 61: Asynchronous Peripheral Mode Circuit Diagram

4-74 September 18, 1996 (Version 1.04)

 Write to LCA Read Status

WS/CS0 RS, CS0

RS, CS1 WS, CS1

1 TCA
3 TCD 7 4
2 TDC
READY D7
D0-D7
BUSY

CCLK

TWTRB 4
6 TBUSY
RDY/BUSY

DOUT Previous Byte D6 D7 D0 D1 D2

X6097

Description Symbol Min Max Units

Effective Write time 1 TCA 100 ns
(CS0, WS=Low; RS, CS1=High)
Write
DIN setup time 2 TDC 60 ns
DIN hold time 3 TCD 0 ns
RDY/BUSY delay after end of 4 TWTRB 60 ns
Write or Read
RDY RDY/BUSY active after beginning 7 60 ns
of Read
RDY/BUSY Low output (Note 4) 6 TBUSY 2 9 CCLK
periods
Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 62: Asynchronous Peripheral Mode Programming Switching Characteristics

September 18, 1996 (Version 1.04) 4-75

XC4000 Series Field Programmable Gate Arrays

Express Mode (XC4000EX only) nized as High, and remains Low until the device’s configu-
ration memory is full. DOUT is then pulled High to signal
Express mode is similar to Slave Serial mode, except that the next device in the chain to accept the configuration data
data is processed one byte per CCLK cycle instead of one on the D0-D7 bus.
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con- The DONE pins of all devices in the chain should be tied
figuration data shift registers. A CCLK frequency of 1 MHz together, with one or more active internal pull-ups. If a
is equivalent to a 8 MHz serial rate, because eight bits of large number of devices are included in the chain, deacti-
configuration data are loaded per CCLK cycle. Express vate some of the internal pull-ups, since the Low-driving
mode does not support CRC error checking, but does sup- DONE pin of the last device in the chain must sink the cur-
port constant-field error checking. rent from all pull-ups in the chain. The DONE pull-up is
activated by default. It can be deactivated using a Make-
In Express mode, an external signal drives the CCLK input Bits option.
of the FPGA device. The first byte of parallel configuration
data must be available at the D inputs of the FPGA a short XC4000EX devices in Express mode are always synchro-
setup time before the second rising CCLK edge. Subse- nized to DONE. The device becomes active after DONE
quent data bytes are clocked in on each consecutive rising goes High. DONE is an open-drain output. With the DONE
CCLK edge. pins tied together, therefore, the external DONE signal
stays low until all devices are configured, then all devices in
Express mode is only supported by the XC4000EX and the daisy chain become active simultaneously. If the DONE
XC5200 families. It may not be used, therefore, when an pin of a device is left unconnected, the device becomes
XC4000EX or XC5200 device is daisy-chained with active as soon as that device has been configured.
devices from other Xilinx families. XC5200 devices in the chain should be configured as syn-
If the first device is configured in Express mode, additional chronized to DONE (MakeBits option CCLK_SYNC or
devices may be daisy-chained only if every device in the UCLK_SYNC), and their DONE pins wired together with
chain is also configured in Express mode. CCLK pins are those of the XC4000EX devices.
tied together and D0-D7 pins are tied together for all Express mode must be specified as an option to the Make-
devices along the chain. A status signal is passed from Bits program, which generates the bitstream. The Express
DOUT to CS1 of successive devices along the chain. The mode bitstream is not compatible with the other six config-
lead device in the chain has its CS1 input tied High (or float- uration modes.
ing, since there is an internal pullup). Frame data is
accepted only when CS1 is High and the device’s configu- Express mode is selected by a <010> on the mode pins
ration memory is not already full. The status pin DOUT is (M2, M1, M0).
pulled Low two internal-oscillator cycles after INIT is recog-

VCC
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
4.7KΩ
8

To Additional
M0 M1 M2 M0 M1 M2 Optional
Daisy-Chained
Devices
CS1 DOUT CS1 DOUT
8 8
DATA BUS D0-D7 D0-D7
Optional
VCC
XC4000EX/ Daisy-Chained
XC5200 XC4000EX/
4.7KΩ
XC5200
PROGRAM PROGRAM PROGRAM

INIT INIT DONE INIT DONE

CCLK CCLK

To Additional
Optional
CCLK Daisy-Chained
Devices

X6611

Figure 63: Express Mode Circuit Diagram

4-76 September 18, 1996 (Version 1.04)

 Description Symbol Min Max Units
INIT (High) setup time TIC - µs
D0 - D7 setup time TDC - ns
D0 - D7 hold time TCD 0 ns
CCLK
CCLK High time TCCH - ns
CCLK Low time TCCL - ns
CCLK Frequency FCC - MHz
Preliminary

CCLK
1 TIC

INIT
TCD 3
2 T
DC

D0-D7 BYTE BYTE BYTE BYTE

0 1 2 3

DOUT

FPGA Filled
Internal INIT

RDY/BUSY

CS1 X6710

Note: If not driven by the preceding DOUT, CS1 must remain High until the device is fully configured.

Figure 64: Express Mode Programming Switching Characteristics

September 18, 1996 (Version 1.04) 4-77

XC4000 Series Field Programmable Gate Arrays

Table 24: Pin Functions During Configuration

CONFIGURATION MODE <M2:M1:M0>
SYNCH. ASYNCH. MASTER
MASTER
SLAVE MASTER PERIPH- PERIPH- PARALLEL
PARALLEL UP EXPRESS USER
SERIAL SERIAL ERAL ERAL DOWN
<1:0:0> <0:1:0> OPERATION
<1:1:1> <0:0:0> <0:1:1> <1:0:1> <1:1:0>
M2(HIGH) (I) M2(LOW) (I) M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M2(HIGH) (I) M2(LOW) (I) (I)
M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) (O)
M0(HIGH) (I) M0(LOW) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) M0(LOW) (I) M0(HIGH) (I) (I)
HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) I/O
LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) I/O
INIT INIT INIT INIT INIT INIT INIT I/O
DONE DONE DONE DONE DONE DONE DONE DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM
CCLK (I) CCLK (O) CCLK (I) CCLK (O) CCLK (O) CCLK (O) CCLK (I) CCLK (I)
RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RCLK (O) I/O
RS (I) I/O
CS0 (I) I/O
DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) I/O
DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) I/O
DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) I/O
DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) I/O
DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) I/O
DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) I/O
DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) I/O
DIN (I) DIN (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) I/O
DOUT DOUT DOUT DOUT DOUT DOUT DOUT SGCK4-GCK5-I/O
TDI TDI TDI TDI TDI TDI TDI TDI-I/O
TCK TCK TCK TCK TCK TCK TCK TCK-I/O
TMS TMS TMS TMS TMS TMS TMS TMS-I/O
TDO TDO TDO TDO TDO TDO TDO TDO-(O)
WS (I) A0 A0 I/O
A1 A1 PGCK4-GCK6-I/O
CS1 A2 A2 I/O
A3 A3 I/O
A4 A4 I/O
A5 A5 I/O
A6 A6 I/O
A7 A7 I/O
A8 A8 I/O
A9 A9 I/O
A10 A10 I/O
A11 A11 I/O
A12 A12 I/O
A13 A13 I/O
A14 A14 I/O
A15 A15 SGCK1-GCK7-I/O
A16 A16 PGCK1-GCK8-I/O
A17 A17 I/O
A18* A18* I/O
A19* A19* I/O
A20* A20* I/O
A21* A21* I/O
ALL OTHERS
* XC4000EX only
Notes 1. A shaded table cell represents a 50 kΩ - 100 kΩ pull-up before and during configuration.
2. (I) represents an input; (O) represents an output.
3. INIT is an open-drain output during configuration.

4-78 September 18, 1996 (Version 1.04)

Configuration Switching Characteristics

Vcc T POR
RE-PROGRAM
>300 ns
PROGRAM
T PI

INIT

T ICCK TCCLK

CCLK OUTPUT or INPUT

<300 ns
M0, M1, M2
VALID DONE RESPONSE
(Required)
X1532
<300 ns

I/O

Master Modes
Description Symbol Min Max Units
M0 = High TPOR 10 40 ms
Power-On Reset M0 = Low TPOR 40 130 ms
Program Latency TPI 30 200 µs per
CLB column
CCLK (output) Delay TICCK 40 250 µs
CCLK (output) Period, slow TCCLK 640 2000 ns
CCLK (output) Period, fast TCCLK 80 250 ns

Slave and Peripheral Modes

Description Symbol Min Max Units
Power-On Reset TPOR 10 33 ms
Program Latency TPI 30 200 µs per
CLB column
CCLK (input) Delay (required) TICCK 4 µs
CCLK (input) Period (required) TCCLK 100 ns

September 18, 1996 (Version 1.04) 4-79

XC4000 Series Field Programmable Gate Arrays

XC4000E Switching Characteristics

Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.1

XC4000E Operating Conditions

Symbol Description Min Max Units
VCC Supply voltage relative to GND, TJ = -0 °C to +85°C Commercial 4.75 5.25 V
Supply voltage relative to GND, TJ = -40°C to +100°C Industrial 4.5 5.5 V
Supply voltage relative to GND, TC = -55°C to +125°C Military 4.5 5.5 V
VIH High-level input voltage TTL inputs 2.0 VCC V
CMOS inputs 70% 100% VCC
VIL Low-level input voltage TTL inputs 0 0.8 V
CMOS inputs 0 20% VCC
TIN Input signal transition time (Note 2) 250 ns

Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
Note 2: Typical value only. Not tested or characterized.
Note 3: Input and output measurement thresholds for TTL are 1.5 V. Input and output measurement thresholds for CMOS are 2.5 V.

XC4000E DC Characteristics Over Operating Conditions

Symbol Description Min Max Units
VOH High-level output voltage @ IOH = -4.0mA, VCC min TTL outputs 2.4 V
High-level output voltage @ IOH = -1.0mA, VCC min CMOS outputs VCC-0.5 V
VOL Low-level output voltage @ IOL = 12.0mA, VCC min TTL outputs 0.4 V
(Note 1) CMOS outputs 0.4 V
ICCO Quiescent FPGA supply current (Note 2) TTL input levels 10 mA
CMOS input levels 1 mA
IL Input or output leakage current -10 +10 µA
CIN Input capacitance (sample tested) PQFP and MQFP 10 pF
packages
Other packages 16 pF
IRIN Pad pull-up (when selected) @ VIN = 0V (sample tested) 0.02 0.25 mA
IRLL Horizontal Longline pull-up (when selected) @ logic Low 0.2 2.5 mA

Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with a MakeBits Tie option.

1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.

4-80 September 18, 1996 (Version 1.04)

XC4000E Absolute Maximum Ratings
Symbol Description Units
VCC Supply voltage relative to GND -0.5 to +7.0 V
VIN Input voltage relative to GND (Note 1) -0.5 to VCC +0.5 V
VTS Voltage applied to 3-state output (Note 1) -0.5 to VCC +0.5 V
TSTG Storage temperature (ambient) -65 to +150 °C
TSOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 °C
TJ Junction temperature Ceramic packages +150 °C
Plastic packages +125 °C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.

XC4000E Program Readback Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.

Finished
Internal Net

rdbk.TRIG
TRCRT TRCRT 2
1 TRTRC 2 1 TRTRC

rdclk.I

4 TRCL TRCH 5

rdbk.RIP
6
TRCRR

rdbk.DATA DUMMY DUMMY VALID VALID

TRCRD
7 X1790

Description Symbol Min Max Units

rdbk.TRIG rdbk.TRIG setup to initiate and abort Readback 1 TRTRC 200 - ns
rdbk.TRIG hold to initiate and abort Readback 2 TRCRT 50 - ns
rdclk.1 rdbk.DATA delay 7 TRCRD - 250 ns
rdbk.RIP delay 6 TRCRR - 250 ns
High time 5 TRCH 250 500 ns
Low time 4 TRCL 250 500 ns

Note 1: Timing parameters apply to all speed grades.

Note 2: If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.

September 18, 1996 (Version 1.04) 4-81

XC4000 Series Field Programmable Gate Arrays

XC4000E Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions.

Speed Grade -4 -3 -2
Description Symbol Device Max Max Max Units
From pad through TPG XC4003E 7.0 4.7 4.0 ns
Primary buffer, XC4005E 7.0 4.7 4.3 ns
to any clock K XC4006E 7.5 5.3 5.2 ns
XC4008E 8.0 6.1 5.2 ns
XC4010E 11.0 6.3 5.4 ns
XC4013E 11.5 6.8 5.8 ns
XC4020E 12.0 7.0 6.4 ns
XC4025E 12.5 7.2 6.9 ns
From pad through TSG XC4003E 7.5 5.2 4.4 ns
Secondary buffer, XC4005E 7.5 5.2 4.7 ns
to any clock K XC4006E 8.0 5.8 5.6 ns
XC4008E 8.5 6.6 5.6 ns
XC4010E 11.5 6.8 5.8 ns
XC4013E 12.0 7.3 6.2 ns
XC4020E 12.5 7.5 6.7 ns
XC4025E 13.0 7.7 7.2 ns
Preliminary

4-82 September 18, 1996 (Version 1.04)

XC4000E Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions.

Speed Grade -4 -3 -2
Description Symbol Device Max Max Max Units
Full length, both pull-ups, TWAF XC4003E 9.2 5.0 5.0 ns
inputs from IOB I-pins XC4005E 9.5 6.0 6.0 ns
XC4006E 12.0 7.0 7.0 ns
XC4008E 12.5 8.0 8.0 ns
XC4010E 15.0 9.0 9.0 ns
XC4013E 16.0 11.0 11.0 ns
XC4020E 17.0 13.9 13.9 ns
XC4025E 18.0 16.9 16.9 ns
Full length, both pull-ups, TWAFL XC4003E 12.0 7.0 7.0 ns
inputs from internal logic XC4005E 12.5 8.0 8.0 ns
XC4006E 14.0 9.0 9.0 ns
XC4008E 16.0 10.0 10.0 ns
XC4010E 18.0 11.0 11.0 ns
XC4013E 19.0 13.0 13.0 ns
XC4020E 20.0 15.5 15.5 ns
XC4025E 21.0 18.9 18.9 ns
Half length, one pull-up, TWAO XC4003E 10.5 6.0 6.0 ns
inputs from IOB I-pins XC4005E 10.5 7.0 7.0 ns
XC4006E 13.5 8.0 8.0 ns
XC4008E 14.0 9.0 9.0 ns
XC4010E 16.0 10.0 10.0 ns
XC4013E 17.0 12.0 12.0 ns
XC4020E 18.0 15.0 15.0 ns
XC4025E 19.0 17.6 17.6 ns
Half length, one pull-up, TWAOL XC4003E 12.0 8.0 8.0 ns
inputs from internal logic XC4005E 12.5 9.0 9.0 ns
XC4006E 14.0 10.0 10.0 ns
XC4008E 16.0 11.0 11.0 ns
XC4010E 18.0 12.0 12.0 ns
XC4013E 19.0 14.0 14.0 ns
XC4020E 20.0 16.8 16.8 ns
XC4025E 21.0 19.6 19.6 ns
Preliminary

Note 1: These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore
the values cannot be directly compared. Use XDelay to determine the delay for each destination.
Note 2: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID)
and output delay (TOPF or TOPS), as listed under “IOB Switching Characteristic Guidelines.”

September 18, 1996 (Version 1.04) 4-83

XC4000 Series Field Programmable Gate Arrays

XC4000E Horizontal Longline Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions.

Speed Grade -4 -3 -2
Description Symbol Device Max Max Max Units
TBUF driving a Horizontal Longline TIO1 XC4003E 5.0 4.2 3.4 ns
(LL): XC4005E 5.0 5.0 4.0 ns
XC4006E 6.0 5.9 4.7 ns
I going High or Low to LL going High or XC4008E 7.0 6.3 5.0 ns
Low, while T is Low. XC4010E 8.0 6.4 5.1 ns
Buffer is constantly active. XC4013E 9.0 7.2 5.7 ns
(Note1) XC4020E 10.0 8.2 7.3 ns
XC4025E 11.0 9.1 7.3 ns
I going Low to LL going from resistive TIO2 XC4003E 5.0 4.2 3.6 ns
pull-up High to active Low. XC4005E 6.0 5.3 4.5 ns
XC4006E 7.8 6.4 5.4 ns
TBUF configured as open-drain. XC4008E 8.1 6.8 5.8 ns
XC4010E 10.5 6.9 5.9 ns
(Note1) XC4013E 11.0 7.7 6.5 ns
XC4020E 12.0 8.7 8.7 ns
XC4025E 12.0 9.6 9.6 ns
T going Low to LL going from resistive TON XC4003E 5.5 4.6 3.9 ns
pull-up or floating High to active Low. XC4005E 7.0 6.0 5.7 ns
XC4006E 7.5 6.7 5.7 ns
TBUF configured as open-drain or active XC4008E 8.0 7.1 6.0 ns
buffer with I = Low. XC4010E 8.5 7.3 6.2 ns
XC4013E 8.7 7.5 7.0 ns
(Note1) XC4020E 11.0 8.4 7.1 ns
XC4025E 11.0 8.4 7.1 ns
T going High to TBUF going inactive, TOFF All devices 1.8 1.5 1.3 ns
not driving LL
T going High to LL going from Low to TPUS XC4003E 20.0 14.0 14.0 ns
High, pulled up by a single resistor. XC4005E 23.0 16.0 16.0 ns
XC4006E 25.0 18.0 18.0 ns
XC4008E 27.0 20.0 20.0 ns
(Note 2) XC4010E 29.0 22.0 22.0 ns
XC4013E 32.0 26.0 26.0 ns
XC4020E 35.0 32.5 32.5 ns
XC4025E 42.0 39.1 39.1 ns
T going High to LL going from Low to TPUF XC4003E 9.0 7.0 6.0 ns
High, pulled up by two resistors. XC4005E 10.0 8.0 6.8 ns
XC4006E 11.5 9.0 7.7 ns
XC4008E 12.5 10.0 8.5 ns
(Note1) XC4010E 13.5 11.0 9.4 ns
XC4013E 15.0 13.0 11.7 ns
XC4020E 16.0 14.8 14.8 ns
XC4025E 18.0 16.5 16.5 ns
Preliminary

Note 1: These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore
the values cannot be directly compared. Use XDelay to determine the delay for each destination.
Note 2: This value includes a minimum load. The value reported by LCA2XNF -S is increased to allow for potentially heavy loading,
therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination.

4-84 September 18, 1996 (Version 1.04)

XC4000E CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Combinatorial Delays
F/G inputs to X/Y outputs TILO 2.7 2.0 1.6
F/G inputs via H’ to X/Y outputs TIHO 4.7 4.3 2.7
C inputs via SR through H’ to X/Y outputs THH0O 4.1 3.3 2.4
C inputs via H’ to X/Y outputs THH1O 3.7 3.6 2.2
C inputs via DIN through H’ to X/Y outputs THH2O 4.5 3.6 2.6
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT TOPCY 3.2 2.6 2.1
Add/Subtract input (F3) to COUT TASCY 5.5 4.4 3.7
Initialization inputs (F1, F3) to COUT TINCY 1.7 1.7 1.4
CIN through function generators to TSUM 3.8 3.3 2.6
X/Y outputs
CIN to COUT, bypass function generators TBYP 1.0 0.7 0.6
Sequential Delays
Clock K to outputs Q TCKO 3.7 2.8 2.8
Setup Time before Clock K
F/G inputs TICK 4.0 3.0 2.4
F/G inputs via H’ TIHCK 6.1 4.6 3.9
C inputs via H0 through H’ THH0CK 4.5 3.6 3.5
C inputs via H1 through H’ THH1CK 5.0 4.1 3.3
C inputs via H2 through H’ THH2CK 4.8 3.8 3.7
C inputs via DIN TDICK 3.0 2.4 2.0
C inputs via EC TECCK 4.0 3.0 2.6
C inputs via S/R, going Low (inactive) TRCK 4.2 4.0 4.0
CIN input via F’/G’ TCCK
CIN input via F’/G’ and H’ TCHCK
Preliminary

September 18, 1996 (Version 1.04) 4-85

XC4000 Series Field Programmable Gate Arrays

XC4000E CLB Switching Characteristic Guidelines (continued)

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Hold Time after Clock K
F/G inputs TCKI 0 0 0
F/G inputs via H’ TCKIH 0 0 0
C inputs via H0 through H’ TCKHH0 0 0 0
C inputs via H1 through H’ TCKHH1 0 0 0
C inputs via H2 through H’ TCKHH2 0 0 0
C inputs via DIN TCKDI 0 0 0
C inputs via EC TCKEC 0 0 0
C inputs via SR, going Low (inactive) TCKR 0 0 0
Clock
Clock High time TCH 4.5 4.0 4.0
Clock Low time TCL 4.5 4.0 4.0
Set/Reset Direct
Width (High) TRPW 5.5 4.0 4.0
Delay from C inputs via S/R, TRIO 6.5 4.0 4.0
going High to Q
Master Set/Reset (Note 1)
Width (High or Low) TMRW 13.0 11.5 11.5
Delay from Global Set/Reset net to Q TMRQ 23.0 18.7 17.4
Global Set/Reset inactive to first TMRK
active clock K edge
Toggle Frequency2 (MHz) (Note 2) FTOG 113 142 160
Preliminary

Note 1: Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Note 2: Export Control Max. flip-flop toggle rate.

4-86 September 18, 1996 (Version 1.04)

XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Size Symbol Min Max Min Max Min Max
Write Operation
Address write cycle time 16x2 TWCS 15.0 14.4 11.6
(clock K period) 32x1 TWCTS 15.0 14.4 11.6
Clock K pulse width 16x2 TWPS 7.5 1 ms 7.2 1 ms 5.8 1 ms
(active edge) 32x1 TWPTS 7.5 1 ms 7.2 1 ms 5.8 1 ms
Address setup time 16x2 TASS 2.8 2.4 2.0
before clock K 32x1 TASTS 2.8 2.4 2.0
Address hold time 16x2 TAHS 0 0 0
after clock K 32x1 TAHTS 0 0 0
DIN setup time 16x2 TDSS 3.5 3.2 2.7
before clock K 32x1 TDSTS 2.5 1.9 1.7
DIN hold time 16x2 TDHS 0 0 0
after clock K 32x1 TDHTS 0 0 0
WE setup time 16x2 TWSS 2.2 2.0 1.6
before clock K 32x1 TWSTS 2.2 2.0 1.6
WE hold time 16x2 TWHS 0 0 0
after clock K 32x1 TWHTS 0 0 0
Data valid 16x2 TWOS 10.3 8.8 7.9
after clock K 32x1 TWOTS 11.6 10.3 9.3
Preliminary

Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Note 2: Applicable Read timing specifications are identical to Level-Sensitive Read timing.

TWPS
WCLK (K)

TWSS TWHS

WE

TDSS TDHS

DATA IN

TASS TAHS

ADDRESS

TILO TILO
TWOS

DATA OUT OLD NEW

X6461

September 18, 1996 (Version 1.04) 4-87

XC4000 Series Field Programmable Gate Arrays

XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic

Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Size Symbol Min Max Min Max Min Max
Write Operation
Address write cycle time 16x1 TWCDS 15.0 14.4 11.6
(clock K period)
Clock K pulse width (active edge) 16x1 TWPDS 7.5 1 ms 7.2 1 ms 5.8 1 ms
Address setup time before clock K 16x1 TASDS 2.8 2.5 2.1
Address hold time after clock K 16x1 TAHDS 0 0 0
DIN setup time before clock K 16x1 TDSDS 2.2 1.9 1.6
DIN hold time after clock K 16x1 TDHDS 0 0 0
WE setup time before clock K 16x1 TWSDS 2.2 2.0 1.6
WE hold time after clock K 16x1 TWHDS 0.3 0 0
Data valid after clock K 16x1 TWODS 10.0 7.8 7.0
Preliminary

Note: Applicable Read timing specifications are identical to16x2 Level-Sensitive Read timing.

TWPDS
WCLK (K)

TWSDS TWHDS

WE

TDSDS TDHDS

DATA IN

TASDS TAHDS

ADDRESS

TILO TILO
TWODS

DATA OUT OLD NEW

X6474

4-88 September 18, 1996 (Version 1.04)

XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Size Symbol Min Max Min Max Min Max
Write Operation
Address write cycle time 16x2 TWC 8.0 8.0 8.0
32x1 TWCT 8.0 8.0 8.0
Write Enable pulse width 16x2 TWP 4.0 4.0 4.0
(High) 32x1 TWPT 4.0 4.0 4.0
Address setup time 16x2 TAS 2.0 2.0 2.0
before WE 32x1 TAST 2.0 2.0 2.0
Address hold time 16x2 TAH 2.5 2.0 2.0
after end of WE 32x1 TAHT 2.0 2.0 2.0
DIN setup time 16x2 TDS 4.0 2.2 0.8
before end of WE 32x1 TDST 5.0 2.2 0.8
DIN hold time 16x2 TDH 2.0 2.0 2.0
after end of WE 32x1 TDHT 2.0 2.0 2.0
Read Operation
Address read cycle time 16x2 TRC 4.5 3.1 2.6
32x1 TRCT 6.5 5.5 3.8
Data valid after address 16x2 TILO 2.7 2.0 1.6
change (no Write Enable) 32x1 TIHO 4.7 4.3 2.7
Read Operation, Clocking
Data into Flip-Flop
Address setup time 16x2 TICK 4.0 3.0 2.4
before clock K 32x1 TIHCK 6.1 4.6 3.9
Read During Write
Data valid after WE goes 16x2 TWO 10.0 6.0 4.9
active (DIN stable 32x1 TWOT 12.0 7.3 5.6
before WE)
Data valid after DIN 16x2 TDO 9.0 6.6 5.8
(DIN changes during WE) 32x1 TDOT 11.0 7.6 6.2
Read During Write, Clock-
ing Data into Flip-Flop
WE setup time 16x2 TWCK 8.0 6.0 5.1
before clock K 32x1 TWCKT 9.6 6.8 5.8
Data setup time 16x2 TDCK 7.0 5.2 4.4
before clock K 32x1 TDCKT 8.0 6.2 5.3
Preliminary

Note: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

September 18, 1996 (Version 1.04) 4-89

XC4000 Series Field Programmable Gate Arrays

XC4000E CLB Level-Sensitive RAM Timing Characteristics

T WC

ADDRESS

WRITE
TAS T WP T AH

WRITE ENABLE

T DS T DH

DATA IN REQUIRED

READ WITHOUT WRITE

T ILO

X,Y OUTPUTS VALID VALID

READ, CLOCKING DATA INTO FLIP-FLOP

T ICK T CH

CLOCK

T CKO

VALID VALID
XQ, YQ OUTPUTS
(OLD) (NEW)

READ DURING WRITE

T WP

WRITE ENABLE

T DH

DATA IN
(stable during WE)

T WO

X, Y OUTPUTS VALID VALID

DATA IN
(changing during WE) OLD NEW

T WO T DO

VALID VALID VALID

X, Y OUTPUTS
(PREVIOUS) (OLD) (NEW)

READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP

T WP

WRITE ENABLE
T WCK

T DCK

DATA IN

CLOCK

T CKO

XQ, YQ OUTPUTS

X2640

4-90 September 18, 1996 (Version 1.04)

XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method.
When there is a discrepancy between the two methods, the values listed below should be used, and the derived values must
be ignored. All values are expressed in units of nanoseconds.

Speed Grade -4 -3 -2
Description Symbol Device
Global Clock to Output TICKOF XC4003E 12.5 10.2 8.7
(fast) using OFF XC4005E 14.0 10.7 9.1
XC4006E 14.5 10.7 9.1
XC4008E 15.0 10.8 9.2
TPG OFF
.
. (Max) XC4010E 16.0 10.9 9.3
. XC4013E 16.5 11.0 9.4
.
Global Clock-to-Output Delay
. XC4020E 17.0 11.0 10.2
X3202 XC4025E 17.0 12.6 10.8
Global Clock to Output TICKO XC4003E 16.5 14.0 11.5
(slew-limited) using OFF XC4005E 18.0 14.7 12.0
XC4006E 18.5 14.7 12.0
XC4008E 19.0 14.8 12.1
. (Max) XC4010E 20.0 14.9 12.2
TPG OFF .
. XC4013E 20.5 15.0 12.8
.
Global Clock-to-Output Delay
. XC4020E 21.0 15.1 12.8
X3202
XC4025E 21.0 15.3 13.0
Input Setup Time, using IFF TPSUF XC4003E 2.5 2.3 2.3
(no delay) XC4005E 2.0 1.2 1.2
XC4006E 1.9 1.0 1.0
D XC4008E 1.4 0.6 0.6
Input (Min) XC4010E 1.0 0.2 0.2
Set - Up IFF
& TPG XC4013E 0.5 0 0
Hold
Time XC4020E 0 0 0
X3201
XC4025E 0 0 0

Input Hold Time, using IFF TPHF XC4003E 4.0 4.0 4.0
(no delay) XC4005E 4.6 4.5 4.5
XC4006E 5.0 4.7 4.7
D XC4008E 6.0 5.1 5.1
Input (Min) XC4010E 6.0 5.5 5.5
Set - Up IFF
& TPG XC4013E 7.0 6.5 5.5
Hold
Time XC4020E 7.5 6.7 5.7
X3201
XC4025E 8.0 7.0 5.9

Input Setup Time, using IFF TPSU XC4003E 8.5 7.0 6.0
(with delay) XC4005E 8.5 7.0 6.0
XC4006E 8.5 7.0 6.0
D XC4008E 8.5 7.0 6.0
Input (Min) XC4010E 8.5 7.0 6.0
Set - Up IFF
& TPG XC4013E 8.5 7.0 6.0
Hold
Time XC4020E 9.5 7.0 6.8
X3201
XC4025E 9.5 7.6 6.8

Input Hold Time, using IFF TPH XC4003E 0 0 0

(with delay) XC4005E 0 0 0
XC4006E 0 0 0
D XC4008E 0 0 0
Input (Min) XC4010E 0 0 0
Set - Up IFF
& TPG XC4013E 0 0 0
Hold
Time XC4020E 0 0 0
X3201
XC4025E 0 0 0

OFF = Output Flip-Flop IFF = Input Flip-Flop or Latch Preliminary

September 18, 1996 (Version 1.04) 4-91

XC4000 Series Field Programmable Gate Arrays

XC4000E IOB Input Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Symbol Device Min Max Min Max Min Max
Propagation Delays
(TTL Inputs)
Pad to I1, I2 TPID All devices 3.0 2.5 2.0
Pad to I1, I2 via transparent
latch, no delay TPLI All devices 4.8 3.6 3.6
with delay TPDLI XC4003E 10.4 9.3 6.9
XC4005E 10.8 9.6 7.4
XC4006E 10.8 10.2 8.1
XC4008E 10.8 10.6 8.2
XC4010E 11.0 10.8 8.3
XC4013E 11.4 11.2 9.8
XC4020E 13.8 12.4 11.5
XC4025E 13.8 13.7 12.4
(CMOS Inputs)
Pad to I1, I2 TPIDC All devices 5.5 4.1 3.7
Pad to I1, I2 via transparent
latch, no delay TPLIC All devices 8.8 6.8 6.2
with delay TPDLIC XC4003E 16.5 12.4 11.0
XC4005E 16.5 13.2 11.9
XC4006E 16.8 13.4 12.1
XC4008E 17.3 13.8 12.4
XC4010E 17.5 14.0 12.6
XC4013E 18.0 14.4 13.0
XC4020E 20.8 15.6 14.0
XC4025E 20.8 15.6 14.0
(TTL or CMOS)
Clock (IK) to I1, I2 (flip-flop) TIKRI All devices 5.6 2.8 2.8
Clock (IK) to I1, I2
(latch enable, active Low) TIKLI All devices 6.2 4.0 3.9
Hold Times (Note 1)
Pad to Clock (IK), no delay TIKPI All devices 0 0 0
with delay TIKPID All devices 0 0 0
Clock Enable (EC) to Clock (IK),
no delay TIKEC All devices 1.5 1.5 0.9
with delay TIKECD All devices 0 0 0
Preliminary

Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

4-92 September 18, 1996 (Version 1.04)

XC4000E IOB Input Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Symbol Device Min Max Min Max Min Max
Setup Times (TTL Inputs)
Pad to Clock (IK), no delay TPICK All devices 4.0 2.6 2.0
with delay TPICKD XC4003E 10.9 8.2 6.0
XC4005E 10.9 8.7 6.1
XC4006E 10.9 9.2 6.2
XC4008E 11.1 9.6 6.3
XC4010E 11.3 9.8 6.4
XC4013E 11.8 10.2 7.9
XC4020E 14.0 11.4 9.4
XC4025E 14.0 11.4 10.0
(CMOS Inputs)
Pad to Clock (IK), no delay TPICKC All devices 6.0 3.3 2.4
with delay TPICKDC XC4003E 12.0 8.8 6.9
XC4005E 12.0 9.7 8.0
XC4006E 12.3 9.9 8.1
XC4008E 12.8 10.3 8.2
XC4010E 13.0 10.5 8.3
XC4013E 13.5 10.9 10.0
XC4020E 16.0 12.1 12.1
XC4025E 16.0 12.1 12.1
(TTL or CMOS)
Clock Enable (EC) to Clock
(IK), no delay TECIK All devices 3.5 2.5 2.1
with delay TECIKD XC4003E 10.4 8.1 4.3
XC4005E 10.4 8.5 5.6
XC4006E 10.4 9.1 6.7
XC4008E 10.4 9.5 6.9
XC4010E 10.7 9.7 7.1
XC4013E 11.1 10.1 9.0
XC4020E 14.0 11.3 10.6
XC4025E 14.0 11.3 11.0
Global Set/Reset (Note 3)
Delay from GSR net TRRI 12.0 7.8 6.8
through Q to I1, I2
GSR width TMRW 13.0 11.5 11.5
GSR inactive to first active TMRI
Clock (IK) edge
Preliminary

Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator.

September 18, 1996 (Version 1.04) 4-93

XC4000 Series Field Programmable Gate Arrays

XC4000E IOB Output Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Propagation Delays
(TTL Output Levels)
Clock (OK) to Pad, fast TOKPOF 7.5 6.5 4.5
slew-rate limited TOKPOS 11.5 9.5 7.0
Output (O) to Pad, fast TOPF 8.0 5.5 4.8
slew-rate limited TOPS 12.0 8.5 7.3
3-state to Pad hi-Z TTSHZ 5.0 4.2 3.8
(slew-rate independent)
3-state to Pad active
and valid, fast TTSONF 9.7 8.1 7.3
slew-rate limited TTSONS 13.7 11.1 9.8
Propagation Delays
(CMOS Output Levels)
Clock (OK) to Pad, fast TOKPOFC 9.5 7.8 7.0
slew-rate limited TOKPOSC 13.5 11.6 10.4
Output (O) to Pad, fast TOPFC 10.0 9.7 8.7
slew-rate limited TOPSC 14.0 13.4 12.1
3-state to Pad hi-Z TTSHZC 5.2 4.3 3.9
(slew-rate independent)
3-state to Pad active
and valid, fast TTSONFC 9.1 7.6 6.8
slew-rate limited TTSONSC 13.1 11.4 10.2
Preliminary

Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

4-94 September 18, 1996 (Version 1.04)

XC4000E IOB Output Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Setup and Hold
Output (O) to clock (OK) TOOK 5.0 4.6 3.8
setup time
Output (O) to clock (OK) TOKO 0 0 0
hold time
Clock Enable (EC) to TECOK 4.8 3.5 2.7
clock (OK) setup
Clock Enable (EC) to TOKEC 1.2 1.2 0.5
clock (OK) hold
Clock
Clock High TCH 4.5 4.0 4.0
Clock Low TCL 4.5 4.0 4.0
Global Set/Reset (Note 3)
Delay from GSR net to Pad TRPO 15.0 11.8 8.7
GSR width TMRW 13.0 11.5 11.5
GSR inactive to first active TMRO
clock (OK) edge
Preliminary

Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Note 3: Timing is based on the XC4005E. For other devices see the XACT timing calculator.

September 18, 1996 (Version 1.04) 4-95

XC4000 Series Field Programmable Gate Arrays

XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade -4 -3 -2
Description Symbol Min Max Min Max Min Max
Setup and Hold
Input (TDI) to clock (TCK) TTDITCK
setup time
Input (TDI) to clock (TCK) TTCKTDI
hold time
Input (TMS) to clock (TCK) TTMSTCK
setup time
Input (TMS) to clock (TCK) TTCKTMS
hold time
Propagation Delay
Clock (TCK) to Pad (TDO) TTCKPO
Clock
Clock (TCK) High TTCKH
Clock (TCK) Low TTCKL
Power-On Reset
JTAG operation after valid TRJTAG
Vcc
Preliminary

Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Note 2: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Note 3: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

XC4000L Switching Characteristics

XC4000L timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.

XC4000EX Switching Characteristics

XC4000EX timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.

XC4000XL Switching Characteristics

XC4000XL timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.

4-96 September 18, 1996 (Version 1.04)

Device-Specific Pinout Tables XC4003E PC PQ VQ PG Bndry
Pad Name 84 100 100 120 Scan
Pin Locations for XC4003E Devices I/O P45 P43 P40 H13 160
I/O - P44 P41 J13 163
The following table may contain pinout information for I/O - P45 P42 H12 166
unsupported device/package combinations. Please see the I/O P46 P46 P43 H11 169
availability charts elsewhere in the XC4000 Series data I/O P47 P47 P44 K13 172
I/O P48 P48 P45 J12 175
sheet for availability information.
I/O P49 P49 P46 L13 178
XC4003E PC PQ VQ PG Bndry I/O P50 P50 P47 M13 181
Pad Name 84 100 100 120 Scan I/O, SGCK3 P51 P51 P48 L12 184
VCC P2 P92 P89 G3 - GND P52 P52 P49 K11 -
I/O (A8) P3 P93 P90 G1 32 DONE P53 P53 P50 L11 -
I/O (A9) P4 P94 P91 F1 35 VCC P54 P54 P51 L10 -
I/O - P95 P92 E1 38 PROGRAM P55 P55 P52 M12 -
I/O - P96 P93 F2 41 I/O (D7) P56 P56 P53 M11 187
I/O (A10) P5 P97 P94 F3 44 I/O, PGCK3 P57 P57 P54 N13 190
I/O (A11) P6 P98 P95 D1 47 I/O (D6) P58 P58 P55 M10 193
I/O (A12) P7 P99 P96 C1 50 I/O - P59 P56 N11 196
I/O (A13) P8 P100 P97 D2 53 I/O (D5) P59 P60 P57 M9 199
I/O (A14) P9 P1 P98 C2 56 I/O (CS0) P60 P61 P58 N10 202
I/O, SGCK1 (A15) P10 P2 P99 D3 59 I/O - P62 P59 L8 205
VCC P11 P3 P100 C3 - I/O - P63 P60 N9 208
GND P12 P4 P1 C4 - I/O (D4) P61 P64 P61 M8 211
I/O, PGCK1 (A16) P13 P5 P2 B2 62 I/O P62 P65 P62 N8 214
I/O (A17) P14 P6 P3 B3 65 VCC P63 P66 P63 M7 -
I/O, TDI P15 P7 P4 C5 68 GND P64 P67 P64 L7 -
I/O, TCK P16 P8 P5 B4 71 I/O (D3) P65 P68 P65 N7 217
I/O, TMS P17 P9 P6 B5 74 I/O (RS) P66 P69 P66 N6 220
I/O P18 P10 P7 A4 77 I/O - P70 P67 N5 223
I/O - - - C6 80 I/O - - - M6 226
I/O - P11 P8 A5 83 I/O (D2) P67 P71 P68 L6 229
I/O P19 P12 P9 B6 86 I/O P68 P72 P69 N4 232
I/O P20 P13 P10 A6 89 I/O (D1) P69 P73 P70 M5 235
GND P21 P14 P11 B7 - I/O (RCLK, P70 P74 P71 N3 238
VCC P22 P15 P12 C7 - RDY/BUSY)
I/O P23 P16 P13 A7 92 I/O (D0, DIN) P71 P75 P72 N2 241
I/O P24 P17 P14 A8 95 I/O, SGCK4 P72 P76 P73 M3 244
I/O - P18 P15 A9 98 (DOUT)
I/O - - - B8 101 CCLK P73 P77 P74 L4 -
I/O P25 P19 P16 C8 104 VCC P74 P78 P75 L3 -
I/O P26 P20 P17 A10 107 O, TDO P75 P79 P76 M2 0
I/O P27 P21 P18 B9 110 GND P76 P80 P77 K3 -
I/O - P22 P19 A11 113 I/O (A0, WS) P77 P81 P78 L2 2
I/O P28 P23 P20 C9 116 I/O, PGCK4 (A1) P78 P82 P79 N1 5
I/O, SCGK2 P29 P24 P21 A12 119 I/O (CS1, A2) P79 P83 P80 K2 8
O (M1) P30 P25 P22 B11 122 I/O (A3) P80 P84 P81 L1 11
GND P31 P26 P23 C10 - I/O (A4) P81 P85 P82 J2 14
I (M0) P32 P27 P24 C11 125 I/O (A5) P82 P86 P83 K1 17
VCC P33 P28 P25 D11 - I/O - P87 P84 H3 20
I (M2) P34 P29 P26 B12 126 I/O - P88 P85 J1 23
I/O, PGCK2 P35 P30 P27 C12 127 I/O (A6) P83 P89 P86 H2 26
I/O (HDC) P36 P31 P28 A13 130 I/O (A7) P84 P90 P87 H1 29
I/O - P32 P29 D12 133 GND P1 P91 P88 G2 -
I/O (LDC) P37 P33 P30 C13 136 4/2/96
I/O P38 P34 P31 E12 139
I/O P39 P35 P32 D13 142
Additional No Connect (N.C.) Connections on PG120 Package
I/O - P36 P33 F11 145 PG120 PG120 PG120 PG120 PG120
I/O - P37 P34 E13 148 A1 B10 E11 L5 N12
I/O P40 P38 P35 F12 151 A2 B13 J3 L9
I/O (INIT) P41 P39 P36 F13 154 A3 E2 J11 M1
VCC P42 P40 P37 G12 - B1 E3 K12 M4
GND P43 P41 P38 G11 - 2/28/96
I/O P44 P42 P39 G13 157

September 18, 1996 (Version 1.04) 4-97

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4005E/L Devices XC4005

PC PQ TQ PG PQ PQ Bndry
The following table may contain pinout information for E/L
84 100 144 156 160 208 Scan
unsupported device/package combinations. Please see the Pad Name
availability charts elsewhere in the XC4000 Series data I/O P26 P20 P24 A10 P26 P34 143
sheet for availability information. I/O - - P25 A11 P27 P35 146
I/O - - P26 B11 P28 P36 149
XC4005 GND - - P27 C11 P29 P37 -
PC PQ TQ PG PQ PQ Bndry
E/L I/O P27 P21 P28 B12 P32 P42 152
84 100 144 156 160 208 Scan
Pad Name
I/O - P22 P29 A13 P33 P43 155
VCC P2 P92 P128 H3 P142 P183 -
I/O - - P30 A14 P34 P44 158
I/O (A8) P3 P93 P129 H1 P143 P184 44
I/O - - P31 C12 P35 P45 161
I/O (A9) P4 P94 P130 G1 P144 P185 47
I/O P28 P23 P32 B13 P36 P46 164
I/O - P95 P131 G2 P145 P186 50
I/O, P29 P24 P33 B14 P37 P47 167
I/O - P96 P132 G3 P146 P187 53 SCGK2
I/O (A10) P5 P97 P133 F1 P147 P190 56 O (M1) P30 P25 P34 A15 P38 P48 170
I/O (A11) P6 P98 P134 F2 P148 P191 59 GND P31 P26 P35 C13 P39 P49 -
I/O - - P135 E1 P149 P192 62 I (M0) P32 P27 P36 A16 P40 P50 173
I/O - - P136 E2 P150 P193 65 VCC P33 P28 P37 C14 P41 P55 -
GND - - P137 F3 P151 P194 - I (M2) P34 P29 P38 B15 P42 P56 174
I/O (A12) P7 P99 P138 E3 P154 P199 68 I/O, P35 P30 P39 B16 P43 P57 175
I/O (A13) P8 P100 P139 C1 P155 P200 71 PGCK2
I/O - - P140 C2 P156 P201 74 I/O (HDC) P36 P31 P40 D14 P44 P58 178
I/O - - P141 D3 P157 P202 77 I/O - - P41 C15 P45 P59 181
I/O (A14) P9 P1 P142 B1 P158 P203 80 I/O - - P42 D15 P46 P60 184
I/O, P10 P2 P143 B2 P159 P204 83 I/O - P32 P43 E14 P47 P61 187
SGCK1 I/O (LDC) P37 P33 P44 C16 P48 P62 190
(A15)
GND - - P45 F14 P51 P67 -
VCC P11 P3 P144 C3 P160 P205 -
I/O - - P46 F15 P52 P68 193
GND P12 P4 P1 C4 P1 P2 -
I/O - - P47 E16 P53 P69 196
I/O, P13 P5 P2 B3 P2 P4 86
I/O P38 P34 P48 F16 P54 P70 199
PGCK1
I/O P39 P35 P49 G14 P55 P71 202
(A16)
I/O - P36 P50 G15 P56 P74 205
I/O (A17) P14 P6 P3 A1 P3 P5 89
I/O - P37 P51 G16 P57 P75 208
I/O - - P4 A2 P4 P6 92
I/O P40 P38 P52 H16 P58 P76 211
I/O - - P5 C5 P5 P7 95
I/O (INIT) P41 P39 P53 H15 P59 P77 214
I/O, TDI P15 P7 P6 B4 P6 P8 98
VCC P42 P40 P54 H14 P60 P78 -
I/O, TCK P16 P8 P7 A3 P7 P9 101
GND P43 P41 P55 J14 P61 P79 -
GND - - P8 C6 P10 P14 -
I/O P44 P42 P56 J15 P62 P80 217
I/O - - P9 B5 P11 P15 104
I/O P45 P43 P57 J16 P63 P81 220
I/O - - P10 B6 P12 P16 107
I/O - P44 P58 K16 P64 P82 223
I/O, TMS P17 P9 P11 A5 P13 P17 110
I/O - P45 P59 K15 P65 P83 226
I/O P18 P10 P12 C7 P14 P18 113
I/O P46 P46 P60 K14 P66 P86 229
I/O - - P13 B7 P15 P21 116
I/O P47 P47 P61 L16 P67 P87 232
I/O - P11 P14 A6 P16 P22 119
I/O - - P62 M16 P68 P88 235
I/O P19 P12 P15 A7 P17 P23 122
I/O - - P63 L15 P69 P89 238
I/O P20 P13 P16 A8 P18 P24 125
GND - - P64 L14 P70 P90 -
GND P21 P14 P17 C8 P19 P25 -
I/O P48 P48 P65 P16 P73 P95 241
VCC P22 P15 P18 B8 P20 P26 -
I/O P49 P49 P66 M14 P74 P96 244
I/O P23 P16 P19 C9 P21 P27 128
I/O - - P67 N15 P75 P97 247
I/O P24 P17 P20 B9 P22 P28 131
I/O - - P68 P15 P76 P98 250
I/O - P18 P21 A9 P23 P29 134
I/O P50 P50 P69 N14 P77 P99 253
I/O - - P22 B10 P24 P30 137
I/O P25 P19 P23 C10 P25 P33 140

4-98 September 18, 1996 (Version 1.04)

 XC4005 XC4005
PC PQ TQ PG PQ PQ Bndry PC PQ TQ PG PQ PQ Bndry
E/L E/L
84 100 144 156 160 208 Scan 84 100 144 156 160 208 Scan
Pad Name Pad Name
I/O, P51 P51 P70 R16 P78 P100 256 I/O P77 P81 P111 R1 P123 P161 2
SGCK3 (A0, WS)
GND P52 P52 P71 P14 P79 P101 - I/O, P78 P82 P112 P2 P124 P162 5
DONE P53 P53 P72 R15 P80 P103 - PGCK4
VCC P54 P54 P73 P13 P81 P106 - (A1)
PRO- P55 P55 P74 R14 P82 P108 - I/O - - P113 N2 P125 P163 8
GRAM I/O - - P114 M3 P126 P164 11
I/O (D7) P56 P56 P75 T16 P83 P109 259 I/O P79 P83 P115 P1 P127 P165 14
I/O, P57 P57 P76 T15 P84 P110 262 (CS1, A2)
PGCK3 I/O (A3) P80 P84 P116 N1 P128 P166 17
I/O - - P77 R13 P85 P111 265 GND - - P118 L3 P131 P171 -
I/O - - P78 P12 P86 P112 268 I/O - - P119 L2 P132 P172 20
I/O (D6) P58 P58 P79 T14 P87 P113 271 I/O - - P120 L1 P133 P173 23
I/O - P59 P80 T13 P88 P114 274 I/O (A4) P81 P85 P121 K3 P134 P174 26
GND - - P81 P11 P91 P119 - I/O (A5) P82 P86 P122 K2 P135 P175 29
I/O - - P82 R11 P92 P120 277 I/O - P87 P123 K1 P137 P178 32
I/O - - P83 T11 P93 P121 280 I/O - P88 P124 J1 P138 P179 35
I/O (D5) P59 P60 P84 T10 P94 P122 283 I/O (A6) P83 P89 P125 J2 P139 P180 38
I/O (CS0) P60 P61 P85 P10 P95 P123 286 I/O (A7) P84 P90 P126 J3 P140 P181 41
I/O - P62 P86 R10 P96 P126 289 GND P1 P91 P127 H2 P141 P182 -
I/O - P63 P87 T9 P97 P127 292 4/2/96
I/O (D4) P61 P64 P88 R9 P98 P128 295
I/O P62 P65 P89 P9 P99 P129 298
Additional No Connect (N.C.) Connections on TQ144,
VCC P63 P66 P90 R8 P100 P130 -
PG156, PQ160 & PQ208 Packages
GND P64 P67 P91 P8 P101 P131 -
I/O (D3) P65 P68 P92 T8 P102 P132 301 TQ144 PG156 PQ160 PQ208
I/O (RS) P66 P69 P93 T7 P103 P133 304 P117 A4 P8 P1
I/O - P70 P94 T6 P104 P134 307 A12 P9 P3
I/O - - P95 R7 P105 P135 310 D1 P30 P10-P13
I/O (D2) P67 P71 P96 P7 P106 P138 313 D2 P31 P19-P20
I/O P68 P72 P97 T5 P107 P139 316 D16 P49 P31-P32
E15 P50 P38-P41
I/O - - P98 R6 P108 P140 319
M1 P71 P51-P54
I/O - - P99 T4 P109 P141 322
M2 P72 P63-P66
GND - - P100 P6 P110 P142 -
M15 P89 P72-P73
I/O (D1) P69 P73 P101 T3 P113 P147 325 N16 P90 P84-P85
I/O (RCLK, P70 P74 P102 P5 P114 P148 328 R5 P111 P91-P94
RDY/ R12 P112 P102
BUSY) T12 P129 P104-P105
I/O - - P103 R4 P115 P149 331 P130 P107
I/O - - P104 R3 P116 P150 334 P136 P115-P118
I/O P71 P75 P105 P4 P117 P151 337 P152 P124-P125
(D0, DIN) P153 P136-P137
I/O, P72 P76 P106 T2 P118 P152 340 P143-P146
SGCK4 P155-P158
(DOUT) P167-P170
CCLK P73 P77 P107 R2 P119 P153 - P176-P177
VCC P74 P78 P108 P3 P120 P154 - P188-P189
O, TDO P75 P79 P109 T1 P121 P159 0 P195-P198
P206-P208
GND P76 P80 P110 N3 P122 P160 -
3/12/96

September 18, 1996 (Version 1.04) 4-99

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4006E Devices XC4006E PC TQ PG PQ PQ Bndry

The following table may contain pinout information for Pad Name 84 144 156 160 208 Scan
unsupported device/package combinations. Please see the I/O - P26 B11 P28 P36 167
availability charts elsewhere in the XC4000 Series data GND - P27 C11 P29 P37 -
sheet for availability information. I/O - - A12 P30 P40 170
I/O - - - P31 P41 173
XC4006E PC TQ PG PQ PQ Bndry I/O P27 P28 B12 P32 P42 176
Pad Name 84 144 156 160 208 Scan I/O - P29 A13 P33 P43 179
VCC P2 P128 H3 P142 P183 - I/O - P30 A14 P34 P44 182
I/O (A8) P3 P129 H1 P143 P184 50 I/O - P31 C12 P35 P45 185
I/O (A9) P4 P130 G1 P144 P185 53 I/O P28 P32 B13 P36 P46 188
I/O - P131 G2 P145 P186 56 I/O, SCGK2 P29 P33 B14 P37 P47 191
I/O - P132 G3 P146 P187 59 O (M1) P30 P34 A15 P38 P48 194
I/O (A10) P5 P133 F1 P147 P190 62 GND P31 P35 C13 P39 P49 -
I/O (A11) P6 P134 F2 P148 P191 65 I (M0) P32 P36 A16 P40 P50 197
I/O - P135 E1 P149 P192 68 VCC P33 P37 C14 P41 P55 -
I/O - P136 E2 P150 P193 71 I (M2) P34 P38 B15 P42 P56 198
GND - P137 F3 P151 P194 - I/O, PGCK2 P35 P39 B16 P43 P57 199
I/O - - D1 P152 P197 74 I/O (HDC) P36 P40 D14 P44 P58 202
I/O - - D2 P153 P198 77 I/O - P41 C15 P45 P59 205
I/O (A12) P7 P138 E3 P154 P199 80 I/O - P42 D15 P46 P60 208
I/O (A13) P8 P139 C1 P155 P200 83 I/O - P43 E14 P47 P61 211
I/O - P140 C2 P156 P201 86 I/O (LDC) P37 P44 C16 P48 P62 214
I/O - P141 D3 P157 P202 89 I/O - - E15 P49 P63 217
I/O (A14) P9 P142 B1 P158 P203 92 I/O - - D16 P50 P64 220
I/O, SGCK1 (A15) P10 P143 B2 P159 P204 95 GND - P45 F14 P51 P67 -
VCC P11 P144 C3 P160 P205 - I/O - P46 F15 P52 P68 223
GND P12 P1 C4 P1 P2 - I/O - P47 E16 P53 P69 226
I/O, PGCK1 (A16) P13 P2 B3 P2 P4 98 I/O P38 P48 F16 P54 P70 229
I/O (A17) P14 P3 A1 P3 P5 101 I/O P39 P49 G14 P55 P71 232
I/O - P4 A2 P4 P6 104 I/O - P50 G15 P56 P74 235
I/O - P5 C5 P5 P7 107 I/O - P51 G16 P57 P75 238
I/O, TDI P15 P6 B4 P6 P8 110 I/O P40 P52 H16 P58 P76 241
I/O, TCK P16 P7 A3 P7 P9 113 I/O (INIT) P41 P53 H15 P59 P77 244
I/O - - A4 P8 P10 116 VCC P42 P54 H14 P60 P78 -
I/O - - - P9 P11 119 GND P43 P55 J14 P61 P79 -
GND - P8 C6 P10 P14 - I/O P44 P56 J15 P62 P80 247
I/O - P9 B5 P11 P15 122 I/O P45 P57 J16 P63 P81 250
I/O - P10 B6 P12 P16 125 I/O - P58 K16 P64 P82 253
I/O, TMS P17 P11 A5 P13 P17 128 I/O - P59 K15 P65 P83 256
I/O P18 P12 C7 P14 P18 131 I/O P46 P60 K14 P66 P86 259
I/O - P13 B7 P15 P21 134 I/O P47 P61 L16 P67 P87 262
I/O - P14 A6 P16 P22 137 I/O - P62 M16 P68 P88 265
I/O P19 P15 A7 P17 P23 140 I/O - P63 L15 P69 P89 268
I/O P20 P16 A8 P18 P24 143 GND - P64 L14 P70 P90 -
GND P21 P17 C8 P19 P25 - I/O - - N16 P71 P93 271
VCC P22 P18 B8 P20 P26 - I/O - - M15 P72 P94 274
I/O P23 P19 C9 P21 P27 146 I/O P48 P65 P16 P73 P95 277
I/O P24 P20 B9 P22 P28 149 I/O P49 P66 M14 P74 P96 280
I/O - P21 A9 P23 P29 152 I/O - P67 N15 P75 P97 283
I/O - P22 B10 P24 P30 155 I/O - P68 P15 P76 P98 286
I/O P25 P23 C10 P25 P33 158 I/O P50 P69 N14 P77 P99 289
I/O P26 P24 A10 P26 P34 161 I/O, SGCK3 P51 P70 R16 P78 P100 292
I/O - P25 A11 P27 P35 164

4-100 September 18, 1996 (Version 1.04)

 XC4006E PC TQ PG PQ PQ Bndry XC4006E PC TQ PG PQ PQ Bndry
Pad Name 84 144 156 160 208 Scan Pad Name 84 144 156 160 208 Scan
GND P52 P71 P14 P79 P101 - I/O - P114 M3 P126 P164 11
DONE P53 P72 R15 P80 P103 - I/O (CS1, A2) P79 P115 P1 P127 P165 14
VCC P54 P73 P13 P81 P106 - I/O (A3) P80 P116 N1 P128 P166 17
PROGRAM P55 P74 R14 P82 P108 - I/O - P117 M2 P129 P167 20
I/O (D7) P56 P75 T16 P83 P109 295 I/O - - M1 P130 P168 23
I/O, PGCK3 P57 P76 T15 P84 P110 298 GND - P118 L3 P131 P171 -
I/O - P77 R13 P85 P111 301 I/O - P119 L2 P132 P172 26
I/O - P78 P12 P86 P112 304 I/O - P120 L1 P133 P173 29
I/O (D6) P58 P79 T14 P87 P113 307 I/O (A4) P81 P121 K3 P134 P174 32
I/O - P80 T13 P88 P114 310 I/O (A5) P82 P122 K2 P135 P175 35
I/O - - R12 P89 P115 313 I/O - P123 K1 P137 P178 38
I/O - - T12 P90 P116 316 I/O - P124 J1 P138 P179 41
GND - P81 P11 P91 P119 - I/O (A6) P83 P125 J2 P139 P180 44
I/O - P82 R11 P92 P120 319 I/O (A7) P84 P126 J3 P140 P181 47
I/O - P83 T11 P93 P121 322 GND P1 P127 H2 P141 P182 -
I/O (D5) P59 P84 T10 P94 P122 325 4/2/96
I/O (CS0) P60 P85 P10 P95 P123 328
I/O - P86 R10 P96 P126 331
I/O - P87 T9 P97 P127 334
I/O (D4) P61 P88 R9 P98 P128 337 Additional No Connect (N.C.) Connections on PQ160 &
I/O P62 P89 P9 P99 P129 340 PQ208 Packages
VCC P63 P90 R8 P100 P130 -
GND P64 P91 P8 P101 P131 -
PQ160 PQ208
P136 P1
I/O (D3) P65 P92 T8 P102 P132 343
P3
I/O (RS) P66 P93 T7 P103 P133 346
P12-P13
I/O - P94 T6 P104 P134 349
P19-20
I/O - P95 R7 P105 P135 352
P31-P32
I/O (D2) P67 P96 P7 P106 P138 355
P38-P39
I/O P68 P97 T5 P107 P139 358
P51-P54
I/O - P98 R6 P108 P140 361
P65-P66
I/O - P99 T4 P109 P141 364
P72-P73
GND - P100 P6 P110 P142 -
P84-P85
I/O - - R5 P111 P145 367
P91-P92
I/O - - - P112 P146 370
P102
I/O (D1) P69 P101 T3 P113 P147 373
P104-P105
I/O (RCLK, P70 P102 P5 P114 P148 376
RDY/BUSY) P107
I/O - P103 R4 P115 P149 379 P117-P118
I/O - P104 R3 P116 P150 382 P124-P125
I/O (D0, DIN) P71 P105 P4 P117 P151 385 P136-P137
I/O, SGCK4 P72 P106 T2 P118 P152 388 P143-P144
(DOUT) P155-P158
CCLK P73 P107 R2 P119 P153 - P169-P170
VCC P74 P108 P3 P120 P154 - P176-P177
O, TDO P75 P109 T1 P121 P159 0 P188-P189
GND P76 P110 N3 P122 P160 - P195-P196
I/O (A0, WS) P77 P111 R1 P123 P161 2 P206-P208
I/O, PGCK4 (A1) P78 P112 P2 P124 P162 5
2/28/96
I/O - P113 N2 P125 P163 8

September 18, 1996 (Version 1.04) 4-101

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4008E Devices XC4008E Pad Name

PC PQ PG PQ Bndry
84 160 191 208 Scan
The following table may contain pinout information for
I/O - P24 A10 P30 173
unsupported device/package combinations. Please see the
I/O - - A11 P31 176
availability charts elsewhere in the XC4000 Series data
I/O - - C11 P32 179
sheet for availability information.
I/O P25 P25 B11 P33 182
PC PQ PG PQ Bndry I/O P26 P26 A12 P34 185
XC4008E Pad Name
84 160 191 208 Scan I/O - P27 B12 P35 188
VCC P2 P142 J4 P183 - I/O - P28 A13 P36 191
I/O (A8) P3 P143 J3 P184 56 GND - P29 C12 P37 -
I/O (A9) P4 P144 J2 P185 59 I/O - P30 A15 P40 194
I/O - P145 J1 P186 62 I/O - P31 C13 P41 197
I/O - P146 H1 P187 65 I/O P27 P32 B14 P42 200
I/O - - H2 P188 68 I/O - P33 A16 P43 203
I/O - - H3 P189 71 I/O - P34 B15 P44 206
I/O (A10) P5 P147 G1 P190 74 I/O - P35 C14 P45 209
I/O (A11) P6 P148 G2 P191 77 I/O P28 P36 A17 P46 212
I/O - P149 F1 P192 80 I/O, SCGK2 P29 P37 B16 P47 215
I/O - P150 E1 P193 83 O (M1) P30 P38 C15 P48 218
GND - P151 G3 P194 - GND P31 P39 D15 P49 -
I/O - P152 C1 P197 86 I (M0) P32 P40 A18 P50 221
I/O - P153 E2 P198 89 VCC P33 P41 D16 P55 -
I/O (A12) P7 P154 F3 P199 92 I (M2) P34 P42 C16 P56 222
I/O (A13) P8 P155 D2 P200 95 I/O, PGCK2 P35 P43 B17 P57 223
I/O - P156 B1 P201 98 I/O (HDC) P36 P44 E16 P58 226
I/O - P157 E3 P202 101 I/O - P45 C17 P59 229
I/O (A14) P9 P158 C2 P203 104 I/O - P46 D17 P60 232
I/O, SGCK1 (A15) P10 P159 B2 P204 107 I/O - P47 B18 P61 235
VCC P11 P160 D3 P205 - I/O (LDC) P37 P48 E17 P62 238
GND P12 P1 D4 P2 - I/O - P49 F16 P63 241
I/O, PGCK1 (A16) P13 P2 C3 P4 110 I/O - P50 C18 P64 244
I/O (A17) P14 P3 C4 P5 113 GND - P51 G16 P67 -
I/O - P4 B3 P6 116 I/O - P52 E18 P68 247
I/O - P5 C5 P7 119 I/O - P53 F18 P69 250
I/O, TDI P15 P6 A2 P8 122 I/O P38 P54 G17 P70 253
I/O, TCK P16 P7 B4 P9 125 I/O P39 P55 G18 P71 256
I/O - P8 C6 P10 128 I/O - - H16 P72 259
I/O - P9 A3 P11 131 I/O - - H17 P73 262
GND - P10 C7 P14 - I/O - P56 H18 P74 265
I/O - P11 A4 P15 134 I/O - P57 J18 P75 268
I/O - P12 A5 P16 137 I/O P40 P58 J17 P76 271
I/O, TMS P17 P13 B7 P17 140 I/O (INIT) P41 P59 J16 P77 274
I/O P18 P14 A6 P18 143 VCC P42 P60 J15 P78 -
I/O - - C8 P19 146 GND P43 P61 K15 P79 -
I/O - - A7 P20 149 I/O P44 P62 K16 P80 277
I/O - P15 B8 P21 152 I/O P45 P63 K17 P81 280
I/O - P16 A8 P22 155 I/O - P64 K18 P82 283
I/O P19 P17 B9 P23 158 I/O - P65 L18 P83 286
I/O P20 P18 C9 P24 161 I/O - - L17 P84 289
GND P21 P19 D9 P25 - I/O - - L16 P85 292
VCC P22 P20 D10 P26 - I/O P46 P66 M18 P86 295
I/O P23 P21 C10 P27 164 I/O P47 P67 M17 P87 298
I/O P24 P22 B10 P28 167 I/O - P68 N18 P88 301
I/O - P23 A9 P29 170 I/O - P69 P18 P89 304

4-102 September 18, 1996 (Version 1.04)

 PC PQ PG PQ Bndry PC PQ PG PQ Bndry
XC4008E Pad Name XC4008E Pad Name
84 160 191 208 Scan 84 160 191 208 Scan
GND - P70 M16 P90 - I/O (D0, DIN) P71 P117 U3 P151 433
I/O - P71 T18 P93 307 I/O, SGCK4 (DOUT) P72 P118 T4 P152 436
I/O - P72 P17 P94 310 CCLK P73 P119 V1 P153 -
I/O P48 P73 N16 P95 313 VCC P74 P120 R4 P154 -
I/O P49 P74 T17 P96 316 O, TDO P75 P121 U2 P159 0
I/O - P75 R17 P97 319 GND P76 P122 R3 P160 -
I/O - P76 P16 P98 322 I/O (A0, WS) P77 P123 T3 P161 2
I/O P50 P77 U18 P99 325 I/O, PGCK4 (A1) P78 P124 U1 P162 5
I/O, SGCK3 P51 P78 T16 P100 328 I/O - P125 P3 P163 8
GND P52 P79 R16 P101 - I/O - P126 R2 P164 11
DONE P53 P80 U17 P103 - I/O (CS1, A2) P79 P127 T2 P165 14
VCC P54 P81 R15 P106 - I/O (A3) P80 P128 N3 P166 17
PROGRAM P55 P82 V18 P108 - I/O - P129 P2 P167 20
I/O (D7) P56 P83 T15 P109 331 I/O - P130 T1 P168 23
I/O, PGCK3 P57 P84 U16 P110 334 GND - P131 M3 P171 -
I/O - P85 T14 P111 337 I/O - P132 P1 P172 26
I/O - P86 U15 P112 340 I/O - P133 N1 P173 29
I/O (D6) P58 P87 V17 P113 343 I/O (A4) P81 P134 M2 P174 32
I/O - P88 V16 P114 346 I/O (A5) P82 P135 M1 P175 35
I/O - P89 T13 P115 349 I/O - - L3 P176 38
I/O - P90 U14 P116 352 I/O - P136 L2 P177 41
GND - P91 T12 P119 - I/O - P137 L1 P178 44
I/O - P92 U13 P120 355 I/O - P138 K1 P179 47
I/O - P93 V13 P121 358 I/O (A6) P83 P139 K2 P180 50
I/O (D5) P59 P94 U12 P122 361 I/O (A7) P84 P140 K3 P181 53
I/O (CS0) P60 P95 V12 P123 364 GND P1 P141 K4 P182 -
I/O - - T11 P124 367 4/2/96
I/O - - U11 P125 370
I/O - P96 V11 P126 373
Additional No Connect (N.C.) Connections on PG191 &
I/O - P97 V10 P127 376
PQ208 Packages
I/O (D4) P61 P98 U10 P128 379
I/O P62 P99 T10 P129 382 PG191 PQ208 PQ208
VCC P63 P100 R10 P130 - A14 P1 P107
GND P64 P101 R9 P131 - B5 P3 P117
I/O (D3) P65 P102 T9 P132 385 B6 P12 P118
I/O (RS) P66 P103 U9 P133 388 B13 P13 P143
I/O - P104 V9 P134 391 D1 P38 P144
I/O - P105 V8 P135 394 D18 P39 P155
I/O - - U8 P136 397 F2 P51 P156
I/O - - T8 P137 400 F17 P52 P157
I/O (D2) P67 P106 V7 P138 403 N2 P53 P158
I/O P68 P107 U7 P139 406 N17 P54 P169
I/O - P108 V6 P140 409 R1 P65 P170
I/O - P109 U6 P141 412 R18 P66 P195
GND - P110 T7 P142 - V4 P91 P196
I/O - P111 U5 P145 415 V5 P92 P206
I/O - P112 T6 P146 418 V14 P102 P207
I/O (D1) P69 P113 V3 P147 421 V15 P104 P208
I/O P70 P114 V2 P148 424 P105
(RCLK, RDY/BUSY)
I/O - P115 U4 P149 427 2/28/96
I/O - P116 T5 P150 430

September 18, 1996 (Version 1.04) 4-103

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4010E/L Devices PQ/

XC4010E/L PC PQ TQ PG BG Bndry
The following table may contain pinout information for HQ
Pad Name 84 160 176 191 225 Scan
unsupported device/package combinations. Please see the 208
availability charts elsewhere in the XC4000 Series data I/O - - P15 C8 P19 G4 164
sheet for availability information. I/O - - P16 A7 P20 G3 167
I/O - P15 P17 B8 P21 G2 170
PQ/
XC4010E/L PC PQ TQ PG BG Bndry I/O - P16 P18 A8 P22 G1 173
HQ
Pad Name 84 160 176 191 225 Scan I/O P19 P17 P19 B9 P23 G5 176
208
VCC P2 P142 P155 J4 P183 D8 - I/O P20 P18 P20 C9 P24 H3 179
I/O (A8) P3 P143 P156 J3 P184 E8 62 GND P21 P19 P21 D9 P25 H2 -
I/O (A9) P4 P144 P157 J2 P185 B7 65 VCC P22 P20 P22 D10 P26 H1 -
I/O - P145 P158 J1 P186 A7 68 I/O P23 P21 P23 C10 P27 H4 182
I/O - P146 P159 H1 P187 C7 71 I/O P24 P22 P24 B10 P28 H5 185
I/O - - P160 H2 P188 D7 74 I/O - P23 P25 A9 P29 J2 188
I/O - - P161 H3 P189 E7 77 I/O - P24 P26 A10 P30 J1 191
I/O (A10) P5 P147 P162 G1 P190 A6 80 I/O - - P27 A11 P31 J3 194
I/O (A11) P6 P148 P163 G2 P191 B6 83 I/O - - P28 C11 P32 J4 197
I/O - P149 P164 F1 P192 A5 86 I/O P25 P25 P29 B11 P33 K2 200
I/O - P150 P165 E1 P193 B5 89 I/O P26 P26 P30 A12 P34 K3 203
GND - P151 P166 G3 P194 GND* - I/O - P27 P31 B12 P35 J6 206
I/O - - - F2 P195 D6 92 I/O - P28 P32 A13 P36 L1 209
I/O - - P167 D1 P196 C5 95 GND - P29 P33 C12 P37 GND* -
I/O - P152 P168 C1 P197 A4 98 I/O - - - B13 P38 L3 212
I/O - P153 P169 E2 P198 E6 101 I/O - - - A14 P39 M1 215
I/O (A12) P7 P154 P170 F3 P199 B4 104 I/O - P30 P34 A15 P40 K5 218
I/O (A13) P8 P155 P171 D2 P200 D5 107 I/O - P31 P35 C13 P41 M2 221
I/O - P156 P172 B1 P201 B3 110 I/O P27 P32 P36 B14 P42 L4 224
I/O - P157 P173 E3 P202 F6 113 I/O - P33 P37 A16 P43 N1 227
I/O (A14) P9 P158 P174 C2 P203 A2 116 I/O - P34 P38 B15 P44 M3 230
I/O, SGCK1 P10 P159 P175 B2 P204 C3 119 I/O - P35 P39 C14 P45 N2 233
(A15) I/O P28 P36 P40 A17 P46 K6 236
VCC P11 P160 P176 D3 P205 B2 - I/O, SCGK2 P29 P37 P41 B16 P47 P1 239
GND P12 P1 P1 D4 P2 A1 - O (M1) P30 P38 P42 C15 P48 N3 242
I/O, PGCK1 P13 P2 P2 C3 P4 D4 122 GND P31 P39 P43 D15 P49 GND* -
(A16) I (M0) P32 P40 P44 A18 P50 P2 245
I/O (A17) P14 P3 P3 C4 P5 B1 125 VCC P33 P41 P45 D16 P55 R1 -
I/O - P4 P4 B3 P6 C2 128 I (M2) P34 P42 P46 C16 P56 M4 246
I/O - P5 P5 C5 P7 E5 131 I/O, PGCK2 P35 P43 P47 B17 P57 R2 247
I/O, TDI P15 P6 P6 A2 P8 D3 134 I/O (HDC) P36 P44 P48 E16 P58 P3 250
I/O, TCK P16 P7 P7 B4 P9 C1 137 I/O - P45 P49 C17 P59 L5 253
I/O - P8 P8 C6 P10 D2 140 I/O - P46 P50 D17 P60 N4 256
I/O - P9 P9 A3 P11 G6 143 I/O - P47 P51 B18 P61 R3 259
I/O - - - B5 P12 E4 146 I/O (LDC) P37 P48 P52 E17 P62 P4 262
I/O - - - B6 P13 D1 149 I/O - P49 P53 F16 P63 K7 265
GND - P10 P10 C7 P14 GND* - I/O - P50 P54 C18 P64 M5 268
I/O - P11 P11 A4 P15 F5 152 I/O - - - D18 P65 R4 271
I/O - P12 P12 A5 P16 E1 155 I/O - - - F17 P66 N5 274
I/O, TMS P17 P13 P13 B7 P17 F4 158 GND - P51 P55 G16 P67 GND* -
I/O P18 P14 P14 A6 P18 F3 161 I/O - P52 P56 E18 P68 R5 277

4-104 September 18, 1996 (Version 1.04)

 PQ/ PQ/
XC4010E/L PC PQ TQ PG BG Bndry XC4010E/L PC PQ TQ PG BG Bndry
HQ HQ
Pad Name 84 160 176 191 225 Scan Pad Name 84 160 176 191 225 Scan
208 208
I/O - P53 P57 F18 P69 M6 280 GND - P91 P99 T12 P119 GND* -
I/O P38 P54 P58 G17 P70 N6 283 I/O - P92 P100 U13 P120 K13 397
I/O P39 P55 P59 G18 P71 P6 286 I/O - P93 P101 V13 P121 K14 400
I/O - - P60 H16 P72 R6 289 I/O (D5) P59 P94 P102 U12 P122 K15 403
I/O - - P61 H17 P73 M7 292 I/O (CS0) P60 P95 P103 V12 P123 J12 406
I/O - P56 P62 H18 P74 R7 295 I/O - - P104 T11 P124 J13 409
I/O - P57 P63 J18 P75 L7 298 I/O - - P105 U11 P125 J14 412
I/O P40 P58 P64 J17 P76 N8 301 I/O - P96 P106 V11 P126 J15 415
I/O (INIT) P41 P59 P65 J16 P77 P8 304 I/O - P97 P107 V10 P127 J11 418
VCC P42 P60 P66 J15 P78 R8 - I/O (D4) P61 P98 P108 U10 P128 H13 421
GND P43 P61 P67 K15 P79 M8 - I/O P62 P99 P109 T10 P129 H14 424
I/O P44 P62 P68 K16 P80 L8 307 VCC P63 P100 P110 R10 P130 H15 -
I/O P45 P63 P69 K17 P81 P9 310 GND P64 P101 P111 R9 P131 GND* -
I/O - P64 P70 K18 P82 R9 313 I/O (D3) P65 P102 P112 T9 P132 H12 427
I/O - P65 P71 L18 P83 N9 316 I/O (RS) P66 P103 P113 U9 P133 H11 430
I/O - - P72 L17 P84 M9 319 I/O - P104 P114 V9 P134 G14 433
I/O - - P73 L16 P85 L9 322 I/O - P105 P115 V8 P135 G15 436
I/O P46 P66 P74 M18 P86 N10 325 I/O - - P116 U8 P136 G13 439
I/O P47 P67 P75 M17 P87 K9 328 I/O - - P117 T8 P137 G12 442
I/O - P68 P76 N18 P88 R11 331 I/O (D2) P67 P106 P118 V7 P138 G11 445
I/O - P69 P77 P18 P89 P11 334 I/O P68 P107 P119 U7 P139 F15 448
GND - P70 P78 M16 P90 GND* - I/O - P108 P120 V6 P140 F14 451
I/O - - - N17 P91 R12 337 I/O - P109 P121 U6 P141 F13 454
I/O - - - R18 P92 L10 340 GND - P110 P122 T7 P142 GND* -
I/O - P71 P79 T18 P93 P12 343 I/O - - - V5 P143 E13 457
I/O - P72 P80 P17 P94 M11 346 I/O - - - V4 P144 D15 460
I/O P48 P73 P81 N16 P95 R13 349 I/O - P111 P123 U5 P145 F11 463
I/O P49 P74 P82 T17 P96 N12 352 I/O - P112 P124 T6 P146 D14 466
I/O - P75 P83 R17 P97 P13 355 I/O (D1) P69 P113 P125 V3 P147 E12 469
I/O - P76 P84 P16 P98 K10 358 I/O (RCLK, P70 P114 P126 V2 P148 C15 472
I/O P50 P77 P85 U18 P99 R14 361 RDY/
I/O, SGCK3 P51 P78 P86 T16 P100 N13 364 BUSY)
GND P52 P79 P87 R16 P101 GND* - I/O - P115 P127 U4 P149 D13 475
DONE P53 P80 P88 U17 P103 P14 - I/O - P116 P128 T5 P150 C14 478
VCC P54 P81 P89 R15 P106 R15 - I/O P71 P117 P129 U3 P151 F10 481
(D0, DIN)
PROGRAM P55 P82 P90 V18 P108 M12 -
I/O, SGCK4 P72 P118 P130 T4 P152 B15 484
I/O (D7) P56 P83 P91 T15 P109 P15 367
(DOUT)
I/O, PGCK3 P57 P84 P92 U16 P110 N14 370
CCLK P73 P119 P131 V1 P153 C13 -
I/O - P85 P93 T14 P111 L11 373
VCC P74 P120 P132 R4 P154 B14 -
I/O - P86 P94 U15 P112 M13 376
O, TDO P75 P121 P133 U2 P159 A15 0
I/O (D6) P58 P87 P95 V17 P113 J10 379
GND P76 P122 P134 R3 P160 D12 -
I/O - P88 P96 V16 P114 L12 382
I/O P77 P123 P135 T3 P161 A14 2
I/O - P89 P97 T13 P115 M15 385
(A0, WS)
I/O - P90 P98 U14 P116 L13 388
I/O, PGCK4 P78 P124 P136 U1 P162 B13 5
I/O - - - V15 P117 L14 391 (A1)
I/O - - - V14 P118 K11 394 I/O - P125 P137 P3 P163 E11 8

September 18, 1996 (Version 1.04) 4-105

XC4000 Series Field Programmable Gate Arrays

PQ/ Additional No Connect (N.C.) Connections on PQ/

XC4010E/L PC PQ TQ PG BG Bndry HQ208 & BG225 Packages
HQ
Pad Name 84 160 176 191 225 Scan
208
PQ/HQ208 BG225
I/O - P126 P138 R2 P164 C12 11 P1 A3
I/O P79 P127 P139 T2 P165 A13 14 P3 B10
(CS1, A2)
P51 C4
I/O (A3) P80 P128 P140 N3 P166 B12 17
P52 C6
I/O - P129 P141 P2 P167 A12 20
P53 C10
I/O - P130 P142 T1 P168 C11 23
P54 D11
I/O - - - R1 P169 B11 26
P102 E2
I/O - - - N2 P170 E10 29
P104 E3
GND - P131 P143 M3 P171 GND* -
P105 E14
I/O - P132 P144 P1 P172 A11 32
P107 E15
I/O - P133 P145 N1 P173 D10 35
P155 F1
I/O (A4) P81 P134 P146 M2 P174 A10 38
P156 F2
I/O (A5) P82 P135 P147 M1 P175 D9 41
P157 F7
I/O - - P148 L3 P176 C9 44
P158 F9
I/O - P136 P149 L2 P177 B9 47
P206 F12
I/O - P137 P150 L1 P178 A9 50
P207 G10
I/O - P138 P151 K1 P179 E9 53
P208 J5
I/O (A6) P83 P139 P152 K2 P180 C8 56
K1
I/O (A7) P84 P140 P153 K3 P181 B8 59
K4
GND P1 P141 P154 K4 P182 A8 -
K12
4/2/96 L2
* Pads labelled GND* are internally bonded to a Ground L6
plane within the BG225 package. They have no direct con- L15
nection to any specific package pin. M10
M14
Additional Ground (GND) Connections on BG225
Package N7
N11
GND N15
F8 P5
G7 P7
G8 P10
G9 R10
H6
3/12/96
H7
H8
H9
H10
J7
J8
J9
K8

2/28/96

Note: The package pins in this table are bonded to an

internal Ground plane within the BG225 package. They
should all be externally connected to Ground.

4-106 September 18, 1996 (Version 1.04)

Pin Locations for XC4013E/L Devices PQ/ PQ/
XC4013E/L PQ PG BG Bndry
The following table may contain pinout information for HQ HQ
Pad Name 160 223 225 Scan
unsupported device/package combinations. Please see the 208 240
availability charts elsewhere in the XC4000 Series data I/O P14 P18 A6 F3 P18 191
sheet for availability information. VCC - - - VCC* P19 -
I/O - - D7 F2 P20 194
PQ/ PQ/ I/O - - D8 F1 P21 197
XC4013E/L PQ PG BG Bndry
HQ HQ I/O - P19 C8 G4 P23 200
Pad Name 160 223 225 Scan
208 240 I/O - P20 A7 G3 P24 203
VCC P142 P183 J4 D8 P212 - I/O P15 P21 B8 G2 P25 206
I/O (A8) P143 P184 J3 E8 P213 74 I/O P16 P22 A8 G1 P26 209
I/O (A9) P144 P185 J2 B7 P214 77 I/O P17 P23 B9 G5 P27 212
I/O P145 P186 J1 A7 P215 80 I/O P18 P24 C9 H3 P28 215
I/O P146 P187 H1 C7 P216 83 GND P19 P25 D9 H2 P29 -
I/O - P188 H2 D7 P217 86 VCC P20 P26 D10 H1 P30 -
I/O - P189 H3 E7 P218 89 I/O P21 P27 C10 H4 P31 218
I/O (A10) P147 P190 G1 A6 P220 92 I/O P22 P28 B10 H5 P32 221
I/O (A11) P148 P191 G2 B6 P221 95 I/O P23 P29 A9 J2 P33 224
VCC - - - VCC* P222 - I/O P24 P30 A10 J1 P34 227
I/O - - H4 C6 P223 98 I/O - P31 A11 J3 P35 230
I/O - - G4 F7 P224 101 I/O - P32 C11 J4 P36 233
I/O P149 P192 F1 A5 P225 104 I/O - - D11 J5 P38 236
I/O P150 P193 E1 B5 P226 107 I/O - - D12 K1 P39 239
GND P151 P194 G3 GND* P227 - VCC - - - VCC* P40 -
I/O - P195 F2 D6 P228 110 I/O P25 P33 B11 K2 P41 242
I/O - P196 D1 C5 P229 113 I/O P26 P34 A12 K3 P42 245
I/O P152 P197 C1 A4 P230 116 I/O P27 P35 B12 J6 P43 248
I/O P153 P198 E2 E6 P231 119 I/O P28 P36 A13 L1 P44 251
I/O (A12) P154 P199 F3 B4 P232 122 GND P29 P37 C12 GND* P45 -
I/O (A13) P155 P200 D2 D5 P233 125 I/O - - D13 L2 P46 254
I/O - - F4 A3 P234 128 I/O - - D14 K4 P47 257
I/O - - E4 C4 P235 131 I/O - P38 B13 L3 P48 260
I/O P156 P201 B1 B3 P236 134 I/O - P39 A14 M1 P49 263
I/O P157 P202 E3 F6 P237 137 I/O P30 P40 A15 K5 P50 266
I/O (A14) P158 P203 C2 A2 P238 140 I/O P31 P41 C13 M2 P51 269
I/O, SGCK1 P159 P204 B2 C3 P239 143 I/O P32 P42 B14 L4 P52 272
(A15) I/O P33 P43 A16 N1 P53 275
VCC P160 P205 D3 B2 P240 - I/O P34 P44 B15 M3 P54 278
GND P1 P2 D4 A1 P1 - I/O P35 P45 C14 N2 P55 281
I/O, PGCK1 P2 P4 C3 D4 P2 146 I/O P36 P46 A17 K6 P56 284
(A16)
I/O, SCGK2 P37 P47 B16 P1 P57 287
I/O (A17) P3 P5 C4 B1 P3 149
O (M1) P38 P48 C15 N3 P58 290
I/O P4 P6 B3 C2 P4 152
GND P39 P49 D15 GND* P59 -
I/O P5 P7 C5 E5 P5 155
I (M0) P40 P50 A18 P2 P60 293
I/O, TDI P6 P8 A2 D3 P6 158
VCC P41 P55 D16 R1 P61 -
I/O, TCK P7 P9 B4 C1 P7 161
I (M2) P42 P56 C16 M4 P62 294
I/O P8 P10 C6 D2 P8 164
I/O, PGCK2 P43 P57 B17 R2 P63 295
I/O P9 P11 A3 G6 P9 167
I/O (HDC) P44 P58 E16 P3 P64 298
I/O - P12 B5 E4 P10 170
I/O P45 P59 C17 L5 P65 301
I/O - P13 B6 D1 P11 173
I/O P46 P60 D17 N4 P66 304
I/O - - D5 E3 P12 176
I/O P47 P61 B18 R3 P67 307
I/O - - D6 E2 P13 179
I/O (LDC) P48 P62 E17 P4 P68 310
GND P10 P14 C7 GND* P14 -
I/O P49 P63 F16 K7 P69 313
I/O P11 P15 A4 F5 P15 182
I/O P50 P64 C18 M5 P70 316
I/O P12 P16 A5 E1 P16 185
I/O - P65 D18 R4 P71 319
I/O, TMS P13 P17 B7 F4 P17 188
I/O - P66 F17 N5 P72 322

September 18, 1996 (Version 1.04) 4-107

XC4000 Series Field Programmable Gate Arrays

PQ/ PQ/ PQ/ PQ/

XC4013E/L PQ PG BG Bndry XC4013E/L PQ PG BG Bndry
HQ HQ HQ HQ
Pad Name 160 223 225 Scan Pad Name 160 223 225 Scan
208 240 208 240
I/O - - E15 P5 P73 325 I/O - - R13 M14 P128 454
I/O - - F15 L6 P74 328 I/O (D6) P87 P113 V17 J10 P129 457
GND P51 P67 G16 GND* P75 - I/O P88 P114 V16 L12 P130 460
I/O P52 P68 E18 R5 P76 331 I/O P89 P115 T13 M15 P131 463
I/O P53 P69 F18 M6 P77 334 I/O P90 P116 U14 L13 P132 466
I/O P54 P70 G17 N6 P78 337 I/O - P117 V15 L14 P133 469
I/O P55 P71 G18 P6 P79 340 I/O - P118 V14 K11 P134 472
VCC - - - VCC* P80 - GND P91 P119 T12 GND* P135 -
I/O - P72 H16 R6 P81 343 I/O - - R12 L15 P136 475
I/O - P73 H17 M7 P82 346 I/O - - R11 K12 P137 478
I/O - - G15 N7 P84 349 I/O P92 P120 U13 K13 P138 481
I/O - - H15 P7 P85 352 I/O P93 P121 V13 K14 P139 484
I/O P56 P74 H18 R7 P86 355 VCC - - - VCC* P140 -
I/O P57 P75 J18 L7 P87 358 I/O (D5) P94 P122 U12 K15 P141 487
I/O P58 P76 J17 N8 P88 361 I/O (CS0) P95 P123 V12 J12 P142 490
I/O (INIT) P59 P77 J16 P8 P89 364 I/O - P124 T11 J13 P144 493
VCC P60 P78 J15 R8 P90 - I/O - P125 U11 J14 P145 496
GND P61 P79 K15 M8 P91 - I/O P96 P126 V11 J15 P146 499
I/O P62 P80 K16 L8 P92 367 I/O P97 P127 V10 J11 P147 502
I/O P63 P81 K17 P9 P93 370 I/O (D4) P98 P128 U10 H13 P148 505
I/O P64 P82 K18 R9 P94 373 I/O P99 P129 T10 H14 P149 508
I/O P65 P83 L18 N9 P95 376 VCC P100 P130 R10 H15 P150 -
I/O - P84 L17 M9 P96 379 GND P101 P131 R9 GND* P151 -
I/O - P85 L16 L9 P97 382 I/O (D3) P102 P132 T9 H12 P152 511
I/O - - L15 R10 P99 385 I/O (RS) P103 P133 U9 H11 P153 514
I/O - - M15 P10 P100 388 I/O P104 P134 V9 G14 P154 517
VCC - - - VCC* P101 - I/O P105 P135 V8 G15 P155 520
I/O P66 P86 M18 N10 P102 391 I/O - P136 U8 G13 P156 523
I/O P67 P87 M17 K9 P103 394 I/O - P137 T8 G12 P157 526
I/O P68 P88 N18 R11 P104 397 I/O (D2) P106 P138 V7 G11 P159 529
I/O P69 P89 P18 P11 P105 400 I/O P107 P139 U7 F15 P160 532
GND P70 P90 M16 GND* P106 - VCC - - - VCC* P161 -
I/O - - N15 M10 P107 403 I/O P108 P140 V6 F14 P162 535
I/O - - P15 N11 P108 406 I/O P109 P141 U6 F13 P163 538
I/O - P91 N17 R12 P109 409 I/O - - R8 G10 P164 541
I/O - P92 R18 L10 P110 412 I/O - - R7 E15 P165 544
I/O P71 P93 T18 P12 P111 415 GND P110 P142 T7 GND* P166 -
I/O P72 P94 P17 M11 P112 418 I/O - - R6 E14 P167 547
I/O P73 P95 N16 R13 P113 421 I/O - - R5 F12 P168 550
I/O P74 P96 T17 N12 P114 424 I/O - P143 V5 E13 P169 553
I/O P75 P97 R17 P13 P115 427 I/O - P144 V4 D15 P170 556
I/O P76 P98 P16 K10 P116 430 I/O P111 P145 U5 F11 P171 559
I/O P77 P99 U18 R14 P117 433 I/O P112 P146 T6 D14 P172 562
I/O, SGCK3 P78 P100 T16 N13 P118 436 I/O (D1) P113 P147 V3 E12 P173 565
GND P79 P101 R16 GND* P119 - I/O (RCLK, P114 P148 V2 C15 P174 568
DONE P80 P103 U17 P14 P120 - RDY/BUSY)
VCC P81 P106 R15 R15 P121 - I/O P115 P149 U4 D13 P175 571
PROGRAM P82 P108 V18 M12 P122 - I/O P116 P150 T5 C14 P176 574
I/O (D7) P83 P109 T15 P15 P123 439 I/O P117 P151 U3 F10 P177 577
(D0, DIN)
I/O, PGCK3 P84 P110 U16 N14 P124 442
I/O, SGCK4 P118 P152 T4 B15 P178 580
I/O P85 P111 T14 L11 P125 445
(DOUT)
I/O P86 P112 U15 M13 P126 448
CCLK P119 P153 V1 C13 P179 -
I/O - - R14 N15 P127 451
VCC P120 P154 R4 B14 P180 -

4-108 September 18, 1996 (Version 1.04)

 PQ/ PQ/ Additional Ground (GND) Connections on BG225
XC4013E/L PQ PG BG Bndry Packages
HQ HQ
Pad Name 160 223 225 Scan
208 240 BG225 BG225
O, TDO P121 P159 U2 A15 P181 0
K8 H9
GND P122 P160 R3 D12 P182 -
J7 H10
I/O P123 P161 T3 A14 P183 2
(A0, WS) J8 G7
I/O, PGCK4 P124 P162 U1 B13 P184 5 J9 G8
(A1) H6 G9
I/O P125 P163 P3 E11 P185 8 H7 F8
I/O P126 P164 R2 C12 P186 11 H8
I/O P127 P165 T2 A13 P187 14
(CS1, A2) 3/11/96
I/O (A3) P128 P166 N3 B12 P188 17
I/O - - P4 F9 P189 20
The BG225 package pins in this table are bonded to an in-
I/O - - N4 D11 P190 23
ternal Ground plane on the XC4013E/L die. They must all
I/O P129 P167 P2 A12 P191 26
be externally connected to Ground.
I/O P130 P168 T1 C11 P192 29
I/O - P169 R1 B11 P193 32 Additional No Connect (N.C.) Connections on PQ/
I/O - P170 N2 E10 P194 35 HQ208 & PQ/HQ240 Packages
GND P131 P171 M3 GND* P196 -
I/O P132 P172 P1 A11 P197 38 PQ/HQ208 PQ/HQ240
I/O P133 P173 N1 D10 P198 41 P1 P22 ‡
I/O - - M4 C10 P199 44 P3 P37 ‡
I/O - - L4 B10 P200 47 P51 P83 ‡
VCC - - - VCC* P201 - P52 P98 ‡
I/O (A4) P134 P174 M2 A10 P202 50 P53 P143 ‡
I/O (A5) P135 P175 M1 D9 P203 53 P54 P158 ‡
I/O - P176 L3 C9 P205 56 P102 P195
I/O P136 P177 L2 B9 P206 59
P104 P204 ‡
I/O P137 P178 L1 A9 P207 62
P105 P219 ‡
I/O P138 P179 K1 E9 P208 65
P107
I/O (A6) P139 P180 K2 C8 P209 68
P155
I/O (A7) P140 P181 K3 B8 P210 71
P156
GND P141 P182 K4 A8 P211 -
P157
4/2/96 P158
Pads labelled GND* are internally bonded to a Ground P206
plane within the BG225 package. They have no direct con- P207
nection to any specific package pin. P208

3/20/96
Pads labelled VCC* are internally bonded to a Vcc plane
within the BG225 package. They have no direct connection ‡ Pins marked with this symbol are reserved for Ground
to any specific package pin. connections on future revisions of the device. These pins
do not physically connect to anything on the current device
revision. However, they should be externally connected to
Ground, if possible.

September 18, 1996 (Version 1.04) 4-109

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4020E Devices XC4020E Pad Name

HQ PG HQ Bndry
208 223 240 Scan
The following table may contain pinout information for
I/O - D6 P13 209
unsupported device/package combinations. Please see the
GND P14 C7 P14 -
availability charts elsewhere in the XC4000 Series data
I/O P15 A4 P15 212
sheet for availability information.
I/O P16 A5 P16 215
HQ PG HQ Bndry I/O, TMS P17 B7 P17 218
XC4020E Pad Name
208 223 240 Scan I/O P18 A6 P18 221
VCC P183 J4 P212 - VCC - - P19 -
I/O (A8) P184 J3 P213 86 I/O - D7 P20 224
I/O (A9) P185 J2 P214 89 I/O - D8 P21 227
I/O P186 J1 P215 92 I/O - - - 230
I/O P187 H1 P216 95 I/O - - - 233
I/O P188 H2 P217 98 I/O P19 C8 P23 236
I/O P189 H3 P218 101 I/O P20 A7 P24 239
I/O (A10) P190 G1 P220 104 I/O P21 B8 P25 242
I/O (A11) P191 G2 P221 107 I/O P22 A8 P26 245
I/O - - - 110 I/O P23 B9 P27 248
I/O - - - 113 I/O P24 C9 P28 251
VCC - - P222 - GND P25 D9 P29 -
I/O - H4 P223 116 VCC P26 D10 P30 -
I/O - G4 P224 119 I/O P27 C10 P31 254
I/O P192 F1 P225 122 I/O P28 B10 P32 257
I/O P193 E1 P226 125 I/O P29 A9 P33 260
GND P194 G3 P227 - I/O P30 A10 P34 263
I/O P195 F2 P228 128 I/O P31 A11 P35 266
I/O P196 D1 P229 131 I/O P32 C11 P36 269
I/O P197 C1 P230 134 I/O - - - 272
I/O P198 E2 P231 137 I/O - - - 275
I/O (A12) P199 F3 P232 140 I/O - D11 P38 278
I/O (A13) P200 D2 P233 143 I/O - D12 P39 281
I/O - - - 146 VCC - - P40 -
I/O - - - 149 I/O P33 B11 P41 284
I/O - F4 P234 152 I/O P34 A12 P42 287
I/O - E4 P235 155 I/O P35 B12 P43 290
I/O P201 B1 P236 158 I/O P36 A13 P44 293
I/O P202 E3 P237 161 GND P37 C12 P45 -
I/O (A14) P203 C2 P238 164 I/O - D13 P46 296
I/O, SGCK1 (A15) P204 B2 P239 167 I/O - D14 P47 299
VCC P205 D3 P240 - I/O P38 B13 P48 302
GND P2 D4 P1 - I/O P39 A14 P49 305
I/O, PGCK1 (A16) P4 C3 P2 170 I/O P40 A15 P50 308
I/O (A17) P5 C4 P3 173 I/O P41 C13 P51 311
I/O P6 B3 P4 176 I/O - - - 314
I/O P7 C5 P5 179 I/O - - - 317
I/O, TDI P8 A2 P6 182 I/O P42 B14 P52 320
I/O, TCK P9 B4 P7 185 I/O P43 A16 P53 323
I/O - - - 188 I/O P44 B15 P54 326
I/O - - - 191 I/O P45 C14 P55 329
I/O P10 C6 P8 194 I/O P46 A17 P56 332
I/O P11 A3 P9 197 I/O, SCGK2 P47 B16 P57 335
I/O P12 B5 P10 200 O (M1) P48 C15 P58 338
I/O P13 B6 P11 203 GND P49 D15 P59 -
I/O - D5 P12 206 I (M0) P50 A18 P60 341

4-110 September 18, 1996 (Version 1.04)

 HQ PG HQ Bndry HQ PG HQ Bndry
XC4020E Pad Name XC4020E Pad Name
208 223 240 Scan 208 223 240 Scan
VCC P55 D16 P61 - I/O P91 N17 P109 475
I (M2) P56 C16 P62 342 I/O P92 R18 P110 478
I/O, PGCK2 P57 B17 P63 343 I/O P93 T18 P111 481
I/O (HDC) P58 E16 P64 346 I/O P94 P17 P112 484
I/O P59 C17 P65 349 I/O - - - 487
I/O P60 D17 P66 352 I/O - - - 490
I/O P61 B18 P67 355 I/O P95 N16 P113 493
I/O (LDC) P62 E17 P68 358 I/O P96 T17 P114 496
I/O - - - 361 I/O P97 R17 P115 499
I/O - - - 364 I/O P98 P16 P116 502
I/O P63 F16 P69 367 I/O P99 U18 P117 505
I/O P64 C18 P70 370 I/O, SGCK3 P100 T16 P118 508
I/O P65 D18 P71 373 GND P101 R16 P119 -
I/O P66 F17 P72 376 DONE P103 U17 P120 -
I/O - E15 P73 379 VCC P106 R15 P121 -
I/O - F15 P74 382 PROGRAM P108 V18 P122 -
GND P67 G16 P75 - I/O (D7) P109 T15 P123 511
I/O P68 E18 P76 385 I/O, PGCK3 P110 U16 P124 514
I/O P69 F18 P77 388 I/O P111 T14 P125 517
I/O P70 G17 P78 391 I/O P112 U15 P126 520
I/O P71 G18 P79 394 I/O - R14 P127 523
VCC - - P80 - I/O - R13 P128 526
I/O P72 H16 P81 397 I/O - - - 529
I/O P73 H17 P82 400 I/O - - - 532
I/O - - - 403 I/O (D6) P113 V17 P129 535
I/O - - - 406 I/O P114 V16 P130 538
I/O - G15 P84 409 I/O P115 T13 P131 541
I/O - H15 P85 412 I/O P116 U14 P132 544
I/O P74 H18 P86 415 I/O P117 V15 P133 547
I/O P75 J18 P87 418 I/O P118 V14 P134 550
I/O P76 J17 P88 421 GND P119 T12 P135 -
I/O (INIT) P77 J16 P89 424 I/O - R12 P136 553
VCC P78 J15 P90 - I/O - R11 P137 556
GND P79 K15 P91 - I/O P120 U13 P138 559
I/O P80 K16 P92 427 I/O P121 V13 P139 562
I/O P81 K17 P93 430 VCC - - P140 -
I/O P82 K18 P94 433 I/O (D5) P122 U12 P141 565
I/O P83 L18 P95 436 I/O (CS0) P123 V12 P142 568
I/O P84 L17 P96 439 I/O - - - 571
I/O P85 L16 P97 442 I/O - - - 574
I/O - - - 445 I/O P124 T11 P144 577
I/O - - - 448 I/O P125 U11 P145 580
I/O - L15 P99 451 I/O P126 V11 P146 583
I/O - M15 P100 454 I/O P127 V10 P147 586
VCC - - P101 - I/O (D4) P128 U10 P148 589
I/O P86 M18 P102 457 I/O P129 T10 P149 592
I/O P87 M17 P103 460 VCC P130 R10 P150 -
I/O P88 N18 P104 463 GND P131 R9 P151 -
I/O P89 P18 P105 466 I/O (D3) P132 T9 P152 595
GND P90 M16 P106 - I/O (RS) P133 U9 P153 598
I/O - N15 P107 469 I/O P134 V9 P154 601
I/O - P15 P108 472 I/O P135 V8 P155 604

September 18, 1996 (Version 1.04) 4-111

XC4000 Series Field Programmable Gate Arrays

HQ PG HQ Bndry HQ PG HQ Bndry
XC4020E Pad Name XC4020E Pad Name
208 223 240 Scan 208 223 240 Scan
I/O P136 U8 P156 607 I/O P173 N1 P198 47
I/O P137 T8 P157 610 I/O - M4 P199 50
I/O - - - 613 I/O - L4 P200 53
I/O - - - 616 VCC - - P201 -
I/O (D2) P138 V7 P159 619 I/O - - - 56
I/O P139 U7 P160 622 I/O - - - 59
VCC - - P161 - I/O (A4) P174 M2 P202 62
I/O P140 V6 P162 625 I/O (A5) P175 M1 P203 65
I/O P141 U6 P163 628 I/O P176 L3 P205 68
I/O - R8 P164 631 I/O P177 L2 P206 71
I/O - R7 P165 634 I/O P178 L1 P207 74
GND P142 T7 P166 - I/O P179 K1 P208 77
I/O - R6 P167 637 I/O (A6) P180 K2 P209 80
I/O - R5 P168 640 I/O (A7) P181 K3 P210 83
I/O P143 V5 P169 643 GND P182 K4 P211 -
I/O P144 V4 P170 646 4/2/96
I/O P145 U5 P171 649
I/O P146 T6 P172 652
I/O (D1) P147 V3 P173 655 Additional No Connect (N.C.) Connections on HQ208 &
I/O (RCLK, RDY/BUSY) P148 V2 P174 658 HQ240 Packages
I/O - - - 661
I/O - - - 664 HQ208 HQ240
I/O P149 U4 P175 667 P1 P22 ‡
I/O P150 T5 P176 670 P3 P37 ‡
I/O (D0, DIN) P151 U3 P177 673 P51 P83 ‡
I/O, SGCK4 (DOUT) P152 T4 P178 676 P52 P98 ‡
CCLK P153 V1 P179 - P53 P143 ‡
VCC P154 R4 P180 - P54 P158 ‡
O, TDO P159 U2 P181 0 P102 P195
GND P160 R3 P182 - P104 P204 ‡
I/O (A0, WS) P161 T3 P183 2 P105 P219 ‡
I/O, PGCK4 (A1) P162 U1 P184 5 P107
I/O P163 P3 P185 8 P155
I/O P164 R2 P186 11 P156
I/O (CS1, A2) P165 T2 P187 14 P157
I/O (A3) P166 N3 P188 17 P158
I/O - - - 20 P206
I/O - - - 23 P207
I/O - P4 P189 26 P208
I/O - N4 P190 29 3/20/96
I/O P167 P2 P191 32
I/O P168 T1 P192 35 ‡ Pins marked with this symbol are reserved for Ground
I/O P169 R1 P193 38 connections on future revisions of the device. These pins
I/O P170 N2 P194 41 do not physically connect to anything on the current device
GND P171 M3 P196 - revision. However, they should be externally connected to
I/O P172 P1 P197 44
Ground, if possible.

4-112 September 18, 1996 (Version 1.04)

Pin Locations for XC4025E, XC4028EX, & XC4025E,
HQ PG HQ PG HQ BG Bndry
/28EX/XL
XC4028XL Devices Pad Name
208 223 240 299 304 352 Scan

The following table may contain pinout information for I/O P6 B3 P4 B3 P301 D24 200
unsupported device/package combinations. Please see the I/O P7 C5 P5 E6 P300 E23 203
availability charts elsewhere in the XC4000 Series data I/O, TDI P8 A2 P6 D5 P299 C26 206
sheet for availability information. I/O, TCK P9 B4 P7 C4 P298 E24 209
I/O - - - A3 P297 F24 212
XC4025E,
HQ PG HQ PG HQ BG Bndry I/O - - - D6 P296 E25 215
/28EX/XL
208 223 240 299 304 352 Scan
Pad Name VCC - - - - - VCC* -
VCC P183 J4 P212 K1 P38 VCC* - GND - - - - - GND* -
I/O (A8) P184 J3 P213 K2 P37 D14 98 I/O P10 C6 P8 E7 P295 D26 218
I/O (A9) P185 J2 P214 K3 P36 C14 101 I/O P11 A3 P9 B4 P294 G24 221
I/O (A19) P186 J1 P215 K5 P35 A15 104 I/O P12 B5 P10 C5 P293 F25 224
I/O (A18) P187 H1 P216 K4 P34 B15 107 I/O P13 B6 P11 A4 P292 F26 227
I/O P188 H2 P217 J1 P33 C15 110 I/O - D5 P12 D7 P291 H23 230
I/O P189 H3 P218 J2 P32 D15 113 I/O - D6 P13 C6 P290 H24 233
I/O (A10) P190 G1 P220 H1 P31 A16 116 I/O - - - E8 P289 G25 236
I/O (A11) P191 G2 P221 J3 P30 B16 119 I/O - - - B5 P288 G26 239
GND - - - - - GND* - GND P14 C7 P14 A5 P287 GND* -
I/O - - - J4 P29 C16 122 I/O, FCLK1 P15 A4 P15 B6 P286 J23 242
I/O - - - J5 P28 B17 125 I/O P16 A5 P16 D8 P285 J24 245
I/O - - - H2 P27 C17 128 I/O, TMS P17 B7 P17 C7 P284 H25 248
I/O - - - G1 P26 B18 131 I/O P18 A6 P18 B7 P283 K23 251
VCC - - P222 E1 P25 VCC* - VCC - - P19 A6 P282 VCC* -
I/O - H4 P223 H3 P23 C18 134 I/O - D7 P20 C8 P280 K24 254
I/O - G4 P224 G2 P22 D17 137 I/O - D8 P21 E9 P279 J25 257
I/O P192 F1 P225 H4 P21 A20 140 I/O - - - A7 P278 L24 260
I/O P193 E1 P226 F2 P20 B19 143 I/O - - - D9 P277 K25 263
GND P194 G3 P227 F1 P19 GND* - GND‡ - - P22 - - GND* -
I/O - - - H5 P18 C19 146 I/O - - - B8 P276 L25 266
I/O - - - G3 P17 D18 149 I/O - - - A8 P275 L26 269
I/O P195 F2 P228 D1 P16 A21 152 I/O P19 C8 P23 C9 P274 M23 272
I/O P196 D1 P229 G4 P15 B20 155 I/O P20 A7 P24 B9 P273 M24 275
I/O P197 C1 P230 E2 P14 C20 158 I/O P21 B8 P25 E10 P272 M25 278
I/O P198 E2 P231 F3 P13 B21 161 I/O P22 A8 P26 A9 P271 M26 281
I/O (A12) P199 F3 P232 G5 P12 B22 164 I/O P23 B9 P27 D10 P270 N24 284
I/O (A13) P200 D2 P233 C1 P10 C21 167 I/O P24 C9 P28 C10 P269 N25 287
GND - - - - - GND* - GND P25 D9 P29 A10 P268 GND* -
VCC - - - - - VCC* - VCC P26 D10 P30 A11 P267 VCC* -
I/O - - - F4 P9 D20 170 I/O P27 C10 P31 B10 P266 N26 290
I/O - - - E3 P8 A23 173 I/O P28 B10 P32 B11 P265 P25 293
I/O - F4 P234 D2 P7 D21 176 I/O P29 A9 P33 C11 P264 P23 296
I/O - E4 P235 C2 P6 C22 179 I/O P30 A10 P34 E11 P263 P24 299
I/O P201 B1 P236 F5 P5 B24 182 I/O P31 A11 P35 D11 P262 R26 302
I/O P202 E3 P237 E4 P4 C23 185 I/O P32 C11 P36 A12 P261 R25 305
I/O (A14) P203 C2 P238 D3 P3 D22 188 I/O - - - B12 P260 R24 308
I/O, SGCK1, P204 B2 P239 C3 P2 C24 191 I/O - - - A13 P259 R23 311
GCK8 (A15)
GND‡ - - P37 - - GND* -
VCC P205 D3 P240 A2 P1 VCC* -
I/O - - - C12 P258 T26 314
GND P2 D4 P1 B1 P304 GND* -
I/O - - - D12 P257 T25 317
I/O, PGCK1, P4 C3 P2 D4 P303 D23 194
I/O - D11 P38 E12 P256 T23 320
GCK1 (A16)
I/O - D12 P39 B13 P255 V26 323
I/O (A17) P5 C4 P3 B2 P302 C25 197
VCC - - P40 A16 P253 VCC* -

September 18, 1996 (Version 1.04) 4-113

XC4000 Series Field Programmable Gate Arrays

XC4025E, XC4025E,
HQ PG HQ PG HQ BG Bndry HQ PG HQ PG HQ BG Bndry
/28EX/XL /28EX/XL
208 223 240 299 304 352 Scan 208 223 240 299 304 352 Scan
Pad Name Pad Name
I/O P33 B11 P41 A14 P252 U24 326 I/O P70 G17 P78 G19 P207 AC17 445
I/O P34 A12 P42 C13 P251 V25 329 I/O P71 G18 P79 H18 P206 AD17 448
I/O P35 B12 P43 B14 P250 V24 332 VCC - - P80 F20 P204 VCC* -
I/O, FCLK2 P36 A13 P44 D13 P249 U23 335 I/O P72 H16 P81 J16 P203 AE18 451
GND P37 C12 P45 A15 P248 GND* - I/O P73 H17 P82 G20 P202 AF18 454
I/O - - - B15 P247 Y26 338 I/O - - - J17 P201 AE17 457
I/O - - - E13 P246 W25 341 I/O - - - H19 P200 AE16 460
I/O - D13 P46 C14 P245 W24 344 GND‡ - - P83 - - GND* -
I/O - D14 P47 A17 P244 V23 347 I/O - - - H20 P199 AF16 463
I/O P38 B13 P48 D14 P243 AA26 350 I/O - - - J18 P198 AC15 466
I/O P39 A14 P49 B16 P242 Y25 353 I/O - G15 P84 J19 P197 AD15 469
I/O P40 A15 P50 C15 P241 Y24 356 I/O - H15 P85 K16 P196 AE15 472
I/O P41 C13 P51 E14 P240 AA25 359 I/O P74 H18 P86 J20 P195 AF15 475
GND - - - - - GND* - I/O P75 J18 P87 K17 P194 AD14 478
VCC - - - - - VCC* - I/O P76 J17 P88 K18 P193 AE14 481
I/O - - - A18 P239 AB25 362 I/O (INIT) P77 J16 P89 K19 P192 AF14 484
I/O - - - D15 P238 AA24 365 VCC P78 J15 P90 L20 P191 VCC* -
I/O P42 B14 P52 C16 P237 Y23 368 GND P79 K15 P91 K20 P190 GND* -
I/O P43 A16 P53 B17 P236 AC26 371 I/O P80 K16 P92 L19 P189 AE13 487
I/O P44 B15 P54 B18 P235 AA23 374 I/O P81 K17 P93 L18 P188 AC13 490
I/O P45 C14 P55 E15 P234 AB24 377 I/O P82 K18 P94 L16 P187 AD13 493
I/O P46 A17 P56 D16 P233 AD25 380 I/O P83 L18 P95 L17 P186 AF12 496
I/O, SGCK2, P47 B16 P57 C17 P232 AC24 383 I/O P84 L17 P96 M20 P185 AE12 499
GCK2 I/O P85 L16 P97 M19 P184 AD12 502
O (M1) P48 C15 P58 A20 P231 AB23 386 I/O - - - N20 P183 AC12 505
GND P49 D15 P59 A19 P230 GND* - I/O - - - M18 P182 AF11 508
I (M0) P50 A18 P60 C18 P229 AD24 389 GND‡ - - P98 - - GND* -
VCC P55 D16 P61 B20 P228 VCC* - I/O - - - M17 P181 AE11 511
I (M2) P56 C16 P62 D17 P227 AC23 390 I/O - - - M16 P180 AD11 514
I/O, PGCK2, P57 B17 P63 B19 P226 AE24 391 I/O - L15 P99 N19 P179 AF9 517
GCK3
I/O - M15 P100 P20 P178 AD10 520
I/O (HDC) P58 E16 P64 C19 P225 AD23 394
VCC - - P101 T20 P177 VCC* -
I/O P59 C17 P65 F16 P224 AC22 397
I/O P86 M18 P102 N18 P175 AE9 523
I/O P60 D17 P66 E17 P223 AF24 400
I/O P87 M17 P103 P19 P174 AD9 526
I/O P61 B18 P67 D18 P222 AD22 403
I/O P88 N18 P104 N17 P173 AC10 529
I/O (LDC) P62 E17 P68 C20 P221 AE23 406
I/O P89 P18 P105 R19 P172 AF7 532
I/O - - - F17 P220 AE22 409
GND P90 M16 P106 R20 P171 GND* -
I/O - - - G16 P219 AF23 412
I/O - - - N16 P170 AE8 535
VCC - - - - - VCC* -
I/O - - - P18 P169 AD8 538
GND - - - - - GND* -
I/O - N15 P107 U20 P168 AC9 541
I/O P63 F16 P69 D19 P218 AD20 415
I/O - P15 P108 P17 P167 AF6 544
I/O P64 C18 P70 E18 P217 AE21 418
I/O P91 N17 P109 T19 P166 AE7 547
I/O P65 D18 P71 D20 P216 AF21 421
I/O P92 R18 P110 R18 P165 AD7 550
I/O P66 F17 P72 G17 P215 AC19 424
I/O P93 T18 P111 P16 P164 AE6 553
I/O - E15 P73 F18 P214 AD19 427
I/O P94 P17 P112 V20 P163 AE5 556
I/O - F15 P74 H16 P213 AE20 430
GND - - - - - GND* -
I/O - - - E19 P212 AF20 433
VCC - - - - - VCC* -
I/O - - - F19 P211 AC18 436
I/O - - - R17 P162 AD6 559
GND P67 G16 P75 E20 P210 GND* -
I/O - - - T18 P161 AC7 562
I/O P68 E18 P76 H17 P209 AD18 439
I/O P95 N16 P113 U19 P160 AF4 565
I/O P69 F18 P77 G18 P208 AE19 442
I/O P96 T17 P114 V19 P159 AF3 568

4-114 September 18, 1996 (Version 1.04)

 XC4025E, XC4025E,
HQ PG HQ PG HQ BG Bndry HQ PG HQ PG HQ BG Bndry
/28EX/XL /28EX/XL
208 223 240 299 304 352 Scan 208 223 240 299 304 352 Scan
Pad Name Pad Name
I/O P97 R17 P115 R16 P158 AD5 571 I/O (RS) P133 U9 P153 V10 P112 N4 682
I/O P98 P16 P116 T17 P157 AE3 574 I/O P134 V9 P154 T10 P111 N3 685
I/O P99 U18 P117 U18 P156 AD4 577 I/O P135 V8 P155 U10 P110 M1 688
I/O, SGCK3, P100 T16 P118 X20 P155 AC5 580 I/O P136 U8 P156 X9 P109 M2 691
GCK4 I/O P137 T8 P157 W9 P108 M3 694
GND P101 R16 P119 W20 P154 GND* - I/O - - - X8 P107 M4 697
DONE P103 U17 P120 V18 P153 AD3 - I/O - - - V9 P106 L1 700
VCC P106 R15 P121 X19 P152 VCC* - GND‡ - - P158 - - GND* -
PROGRAM P108 V18 P122 U17 P151 AC4 - I/O - - - U9 P105 L2 703
I/O (D7) P109 T15 P123 W19 P150 AD2 583 I/O - - - T9 P104 L3 706
I/O, PGCK3, P110 U16 P124 W18 P149 AC3 586 I/O (D2) P138 V7 P159 W8 P103 J1 709
GCK5
I/O P139 U7 P160 X7 P102 K3 712
I/O P111 T14 P125 T15 P148 AB4 589
VCC - - P161 X5 P101 VCC* -
I/O P112 U15 P126 U16 P147 AD1 592
I/O P140 V6 P162 V8 P99 J2 715
I/O - R14 P127 V17 P146 AA4 595
I/O, FCLK4 P141 U6 P163 W7 P98 J3 718
I/O - R13 P128 X18 P145 AA3 598
I/O - R8 P164 U8 P97 K4 721
I/O - - - U15 P144 AB2 601
I/O - R7 P165 W6 P96 G1 724
I/O - - - T14 P143 AC1 604
GND P142 T7 P166 X6 P95 GND* -
VCC - - - - - VCC* -
I/O - - - T8 P94 H2 727
GND - - - - - GND* -
I/O - - - V7 P93 H3 730
I/O (D6) P113 V17 P129 W17 P142 Y3 607
I/O - R6 P167 X4 P92 J4 733
I/O P114 V16 P130 V16 P141 AA2 610
I/O - R5 P168 U7 P91 F1 736
I/O P115 T13 P131 X17 P140 AA1 613
I/O P143 V5 P169 W5 P90 G2 739
I/O P116 U14 P132 U14 P139 W4 616
I/O P144 V4 P170 V6 P89 G3 742
I/O P117 V15 P133 V15 P138 W3 619
I/O P145 U5 P171 T7 P88 F2 745
I/O P118 V14 P134 T13 P137 Y2 622
I/O P146 T6 P172 X3 P87 E2 748
I/O - - - W16 P136 Y1 625
GND - - - - - GND* -
I/O - - - W15 P135 V4 628
VCC - - - - - VCC* -
GND P119 T12 P135 X16 P134 GND* -
I/O (D1) P147 V3 P173 U6 P86 F3 751
I/O - R12 P136 U13 P133 V3 631
I/O (RCLK, P148 V2 P174 V5 P85 G4 754
I/O - R11 P137 V14 P132 W2 634 RDY/BUSY)
I/O, FCLK3 P120 U13 P138 W14 P131 U4 637 I/O - - - W4 P84 D2 757
I/O P121 V13 P139 V13 P130 U3 640 I/O - - - W3 P83 F4 760
VCC - - P140 X15 P129 VCC* - I/O P149 U4 P175 T6 P82 E3 763
I/O (D5) P122 U12 P141 T12 P127 V2 643 I/O P150 T5 P176 U5 P81 C2 766
I/O (CS0) P123 V12 P142 X14 P126 V1 646 I/O P151 U3 P177 V4 P80 D3 769
GND‡ - - P143 - - - - (D0, DIN)
I/O - - - U12 P125 U2 649 I/O, SGCK4, P152 T4 P178 X1 P79 E4 772
I/O - - - W13 P124 T2 652 GCK6
(DOUT)
GND - - - - - GND* -
CCLK P153 V1 P179 V3 P78 C3 -
I/O - - - X13 P123 T1 655
VCC P154 R4 P180 W1 P77 VCC* -
I/O - - - V12 P122 R4 658
O, TDO P159 U2 P181 U4 P76 D4 0
I/O P124 T11 P144 W12 P121 R3 661
GND P160 R3 P182 X2 P75 GND* -
I/O P125 U11 P145 T11 P120 R2 664
I/O (A0, WS) P161 T3 P183 W2 P74 B3 2
I/O P126 V11 P146 X12 P119 R1 667
I/O, PGCK4, P162 U1 P184 V2 P73 C4 5
I/O P127 V10 P147 U11 P118 P3 670 GCK7 (A1)
I/O (D4) P128 U10 P148 V11 P117 P2 673 I/O P163 P3 P185 R5 P72 D5 8
I/O P129 T10 P149 W11 P116 P1 676 I/O P164 R2 P186 T4 P71 A3 11
VCC P130 R10 P150 X10 P115 VCC* - I/O P165 T2 P187 U3 P70 D6 14
GND P131 R9 P151 X11 P114 GND* - (CS1, A2)
I/O (D3) P132 T9 P152 W10 P113 N2 679 I/O (A3) P166 N3 P188 V1 P69 C6 17

September 18, 1996 (Version 1.04) 4-115

XC4000 Series Field Programmable Gate Arrays

XC4025E, Additional No Connect (N.C.) Connections on HQ208

HQ PG HQ PG HQ BG Bndry
/28EX/XL
208 223 240 299 304 352 Scan
Package
Pad Name
I/O - - - R4 P68 B5 20 N.C. N.C.
I/O - - - P5 P67 A4 23 P1 P107
VCC - - - - - VCC* - P3 P155
GND - - - - - GND* - P51 P156
I/O - P4 P189 U2 P66 C7 26 P52 P157
I/O - N4 P190 T3 P65 B6 29 P53 P158
I/O P167 P2 P191 U1 P64 A6 32 P54 P206
I/O P168 T1 P192 P4 P63 D8 35 P102 P207
I/O P169 R1 P193 R3 P62 B7 38 P104 P208
I/O P170 N2 P194 N5 P61 A7 41 P105
I/O - - P195 T2 P60 D9 44 3/15/96
I/O - - - R2 P59 C9 47
GND P171 M3 P196 T1 P58 GND* -
I/O P172 P1 P197 N4 P57 B8 50 Additional Ground (GND) Connections on HQ240
I/O P173 N1 P198 P3 P56 D10 53 Package
I/O - M4 P199 P2 P55 C10 56 GND
I/O - L4 P200 N3 P54 B9 59 P204
VCC - - P201 R1 P52 VCC* - P219
I/O - - - M5 P51 A9 62
I/O - - - P1 P50 D11 65 3/21/96
I/O - - - M4 P49 B11 68 The Ground (GND) package pins in the above table should
I/O - - - N2 P48 A11 71 be externally connected to Ground if possible; however,
GND - - - - - GND* - they can be left unconnected if necessary for compatibility
I/O (A4) P174 M2 P202 N1 P47 D12 74 with other devices.
I/O (A5) P175 M1 P203 M3 P46 C12 77
I/O P176 L3 P205 M2 P45 B12 80
I/O P177 L2 P206 L5 P44 A12 83
I/O (A21) P178 L1 P207 M1 P43 C13 86 Additional No Connect (N.C.) Connections on HQ304
I/O (A20) P179 K1 P208 L4 P42 B13 89
Package
I/O (A6) P180 K2 P209 L3 P41 A13 92 N.C.
I/O (A7) P181 K3 P210 L2 P40 B14 95 P11
GND P182 K4 P211 L1 P39 GND* - P24
4/2/96 P53
P100
Pads labelled GND* are internally bonded to a Ground P128
plane within the BG352 package. They have no direct con- P176
nection to any specific package pin. P205
P254
Pads labelled VCC* are internally bonded to a Vcc plane
P281
within the BG352 package. They have no direct connection
to any specific package pin. 3/21/96

Pads labelled GND‡ should be connected to Ground if pos- Note: In XC4025 (no extension) devices in the HQ304
sible; however, they can be left unconnected if necessary package, P101 is a No Connect (N.C.) pin. P101 is Vcc in
for compatibility with other devices. XC4025E/L and XC4028EX/XL devices. Where necessary
for compatibility, this pin can be left unconnected.

4-116 September 18, 1996 (Version 1.04)

Additional No Connect, Vcc & Ground Connections on
BG352 Package
N.C. VCC GND
A18 A10 A1
A24 A17 A2
B4 B2 A5
B10 B25 A8
B23 D7 A14
C1 D13 A19
C5 D19 A22
C8 G23 A25
C11 H4 A26
D1 K1 B1
D16 K26 B26
D25 N23 E1
F23 P4 E26
J26 U1 H1
K2 U26 H26
L4 W23 N1
L23 Y4 P26
T3 AC8 W1
T4 AC14 W26
T24 AC20 AB1
U25 AE2 AB26
AB3 AE25 AE1
AC2 AF10 AE26
AC6 AF17 AF1
AC11 AF2
AC16 AF5
AC21 AF8
AC25 AF13
AD16 AF19
AD21 AF22
AD26 AF25
AE4 AF26
AE10

3/21/96

September 18, 1996 (Version 1.04) 4-117

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4036EX/XL Devices XC4036EX/XL Bndry

HQ304 PG411 BG432
The following table may contain pinout information for Pad Name Scan
unsupported device/package combinations. Please see the I/O P269 C19 T31 323
availability charts elsewhere in the XC4000 Series data GND P268 GND* GND* -
sheet for availability information. VCC P267 VCC* VCC* -
I/O P266 F20 T30 326
XC4036EX/XL Bndry
HQ304 PG411 BG432 I/O P265 B20 T29 329
Pad Name Scan
GND P304 GND* GND* - I/O P264 C21 U31 332
I/O, GCK1 (A16) P303 H8 D29 218 I/O P263 B22 U30 335
I/O (A17) P302 F6 C30 221 I/O P262 E21 U28 338
I/O P301 B4 E28 224 I/O P261 D22 U29 341
I/O P300 D4 E29 227 I/O P260 A23 V30 344
I/O, TDI P299 B2 D30 230 I/O P259 B24 V29 347
I/O, TCK P298 G9 D31 233 VCC - VCC* VCC* -
I/O - F8 E30 236 GND - GND* GND* -
I/O - C5 E31 239 I/O P258 A25 W30 350
I/O P297 A7 G28 242 I/O P257 D24 W29 353
I/O P296 A5 G29 245 I/O - B26 Y30 356
VCC - VCC* VCC* - I/O - A27 Y29 359
GND - GND* GND* - I/O P256 C27 Y28 362
I/O P295 B8 H28 248 I/O P255 F24 AA30 365
I/O P294 C9 H29 251 VCC P253 VCC* VCC* -
I/O P293 E9 G30 254 I/O P252 E25 AA29 368
I/O P292 F12 H30 257 I/O P251 E27 AB31 371
I/O P291 D10 J28 260 I/O P250 B28 AB30 374
I/O P290 B10 J29 263 I/O, FCLK2 P249 C29 AB29 377
I/O P289 F10 H31 266 GND P248 GND* GND* -
I/O P288 F14 J30 269 I/O P247 F26 AB28 380
GND P287 GND* GND* - I/O P246 D28 AC30 383
I/O, FCLK1 P286 C11 K28 272 I/O P245 B30 AC29 386
I/O P285 B12 K29 275 I/O P244 E29 AC28 389
I/O, TMS P284 E11 K30 278 I/O P243 F28 AD29 392
I/O P283 E15 K31 281 I/O P242 F30 AD28 395
VCC P282 VCC* VCC* - I/O P241 C31 AE30 398
I/O P280 F16 L29 284 I/O P240 E31 AE29 401
I/O P279 C13 L30 287 GND - GND* GND* -
I/O - B14 M29 290 VCC - VCC* VCC* -
I/O - E17 M31 293 I/O P239 B32 AF31 404
I/O P278 E13 N31 296 I/O P238 A33 AE28 407
I/O P277 A15 N28 299 I/O P237 A35 AG31 410
GND - GND* GND* - I/O P236 F32 AF28 413
VCC - VCC* VCC* - I/O - C35 AG30 416
I/O P276 B16 P30 302 I/O - B38 AG29 419
I/O P275 D16 P28 305 I/O P235 E33 AH31 422
I/O P274 D18 P29 308 I/O P234 G31 AG28 425
I/O P273 A17 R31 311 I/O P233 H32 AH30 428
I/O P272 E19 R30 314 I/O, GCK2 P232 B36 AJ30 431
I/O P271 B18 R28 317 O (M1) P231 A39 AH29 434
I/O P270 C17 R29 320 GND P230 GND* GND* -

4-118 September 18, 1996 (Version 1.04)

 XC4036EX/XL Bndry XC4036EX/XL Bndry
HQ304 PG411 BG432 HQ304 PG411 BG432
Pad Name Scan Pad Name Scan
I (M0) P229 E35 AH28 437 I/O P189 Y34 AL16 547
VCC P228 VCC* VCC* - I/O P188 AC37 AH15 550
I (M2) P227 G33 AJ28 438 I/O P187 AB38 AK15 553
I/O, GCK3 P226 D36 AK29 439 I/O P186 AD36 AJ14 556
I/O (HDC) P225 C37 AH27 442 I/O P185 AA35 AH14 559
I/O P224 F34 AK28 445 I/O P184 AE37 AK14 562
I/O P223 J33 AJ27 448 I/O P183 AB36 AL13 565
I/O P222 D38 AL28 451 I/O P182 AD38 AK13 568
I/O (LDC) P221 G35 AH26 454 VCC - VCC* VCC* -
I/O - E39 AL27 457 GND - GND* GND* -
I/O - K34 AH25 460 I/O P181 AB34 AJ13 571
I/O P220 F38 AK26 463 I/O P180 AE39 AH13 574
I/O P219 G37 AL26 466 I/O - AM36 AL12 577
VCC - VCC* VCC* - I/O - AC35 AK12 580
GND - GND* GND* - I/O P179 AG39 AH12 583
I/O P218 H38 AH24 469 I/O P178 AG37 AJ11 586
I/O P217 J37 AJ25 472 VCC P177 VCC* VCC* -
I/O P216 G39 AK25 475 I/O P175 AD34 AL10 589
I/O P215 M34 AJ24 478 I/O P174 AN39 AK10 592
I/O P214 N35 AL24 481 I/O P173 AE35 AJ10 595
I/O P213 P34 AH22 484 I/O P172 AH38 AK9 598
I/O P212 J35 AJ23 487 GND P171 GND* GND* -
I/O P211 L37 AK23 490 I/O P170 AJ37 AL8 601
GND P210 GND* GND* - I/O P169 AG35 AH10 604
I/O P209 M38 AJ22 493 I/O P168 AF34 AJ9 607
I/O P208 R35 AK22 496 I/O P167 AH36 AK8 610
I/O P207 H36 AL22 499 I/O P166 AK36 AK7 613
I/O P206 T34 AJ21 502 I/O P165 AM34 AL6 616
VCC P204 VCC* VCC* - I/O P164 AH34 AJ7 619
I/O P203 N37 AH20 505 I/O P163 AJ35 AH8 622
I/O P202 N39 AK21 508 GND - GND* GND* -
I/O - U35 AK20 511 VCC - VCC* VCC* -
I/O - R39 AJ19 514 I/O P162 AL37 AK6 625
I/O P201 M36 AL20 517 I/O P161 AT38 AL5 628
I/O P200 V34 AH18 520 I/O P160 AM38 AH7 631
GND - GND* GND* - I/O P159 AN37 AJ6 634
VCC - VCC* VCC* - I/O - AK34 AK5 637
I/O P199 R37 AK19 523 I/O - AR39 AL4 640
I/O P198 T38 AJ18 526 I/O P158 AN35 AK4 643
I/O P197 T36 AL19 529 I/O P157 AL33 AH5 646
I/O P196 V36 AK18 532 I/O P156 AV38 AK3 649
I/O P195 U37 AH17 535 I/O, GCK4 P155 AT36 AJ4 652
I/O P194 U39 AJ17 538 GND P154 GND* GND* -
I/O P193 V38 AJ16 541 DONE P153 AR35 AH4 -
I/O (INIT) P192 W37 AK16 544 VCC P152 VCC* VCC* -
VCC P191 VCC* VCC* - PROGRAM P151 AN33 AH3 -
GND P190 GND* GND* - I/O (D7) P150 AM32 AJ2 655

September 18, 1996 (Version 1.04) 4-119

XC4000 Series Field Programmable Gate Arrays

XC4036EX/XL Bndry XC4036EX/XL Bndry

HQ304 PG411 BG432 HQ304 PG411 BG432
Pad Name Scan Pad Name Scan
I/O, GCK5 P149 AP34 AG4 658 I/O P109 AT18 R3 775
I/O P148 AW39 AG3 661 I/O P108 AW17 P2 778
I/O P147 AN31 AH2 664 I/O P107 AV16 P3 781
I/O - AV36 AH1 667 I/O P106 AP18 P4 784
I/O - AR33 AF4 670 VCC - VCC* VCC* -
I/O P146 AP32 AF3 673 GND - GND* GND* -
I/O P145 AU35 AG2 676 I/O P105 AR17 N3 787
I/O P144 AW33 AE3 679 I/O P104 AT16 N4 790
I/O P143 AU33 AF2 682 I/O - AV14 M1 793
VCC - VCC* VCC* - I/O - AW13 M2 796
GND - GND* GND* - I/O (D2) P103 AR15 L2 799
I/O (D6) P142 AV32 AF1 685 I/O P102 AP16 L3 802
I/O P141 AU31 AD4 688 VCC P101 VCC* VCC* -
I/O P140 AR31 AD3 691 I/O P99 AV12 K1 805
I/O P139 AP28 AE2 694 I/O, FCLK4 P98 AR13 K2 808
I/O P138 AT32 AC3 697 I/O P97 AU11 K3 811
I/O P137 AV30 AD1 700 I/O P96 AT12 K4 814
I/O P136 AR29 AC2 703 GND P95 GND* GND* -
I/O P135 AP26 AB4 706 I/O P94 AP14 J2 817
GND P134 GND* GND* - I/O P93 AR11 J3 820
I/O P133 AU29 AB3 709 I/O P92 AV10 J4 823
I/O P132 AV28 AB2 712 I/O P91 AT8 H1 826
I/O, FCLK3 P131 AT28 AB1 715 I/O P90 AT10 H2 829
I/O P130 AR25 AA3 718 I/O P89 AP10 H3 832
VCC P129 VCC* VCC* - I/O P88 AP12 H4 835
I/O (D5) P127 AP24 AA2 721 I/O P87 AR9 G2 838
I/O (CS0) P126 AU27 Y2 724 GND - GND* GND* -
I/O - AR27 Y4 727 VCC - VCC* VCC* -
I/O - AW27 Y3 730 I/O (D1) P86 AU7 G4 841
I/O P125 AT24 W4 733 I/O (RCLK, P85 AW7 F2 844
I/O P124 AR23 W3 736 RDY/BUSY)
GND - GND* GND* - I/O - AW5 F3 847
VCC - VCC* VCC* - I/O - AV6 E1 850
I/O P123 AP22 V4 739 I/O P84 AR7 E3 853
I/O P122 AV24 V3 742 I/O P83 AV4 D1 856
I/O P121 AU23 U1 745 I/O P82 AN9 E4 859
I/O P120 AT22 U2 748 I/O P81 AW1 D2 862
I/O P119 AR21 U4 751 I/O (D0, DIN) P80 AP6 C2 865
I/O P118 AV22 U3 754 I/O, GCK6 (DOUT) P79 AU3 D3 868
I/O (D4) P117 AP20 T1 757 CCLK P78 AR5 D4 -
I/O P116 AU21 T2 760 VCC P77 VCC* VCC* -
VCC P115 VCC* VCC* - O, TDO P76 AN7 C4 0
GND P114 GND* GND* - GND P75 GND* GND* -
I/O (D3) P113 AU19 T3 763 I/O (A0, WS) P74 AT4 B3 2
I/O (RS) P112 AV20 R1 766 I/O, GCK7 (A1) P73 AV2 D5 5
I/O P111 AV18 R2 769 I/O P72 AM8 B4 8
I/O P110 AR19 R4 772 I/O P71 AL7 C5 11

4-120 September 18, 1996 (Version 1.04)

 XC4036EX/XL Bndry XC4036EX/XL Bndry
HQ304 PG411 BG432 HQ304 PG411 BG432
Pad Name Scan Pad Name Scan
I/O - AR3 B5 14 I/O (A10) P31 U3 B19 128
I/O - AR1 C6 17 I/O (A11) P30 R1 C19 131
I/O (CS1, A2) P70 AK6 A5 20 VCC - VCC* VCC* -
I/O (A3) P69 AN3 D7 23 GND - GND* GND* -
I/O P68 AM6 B6 26 I/O P29 U5 D19 134
I/O P67 AM2 A6 29 I/O P28 T4 A20 137
VCC - VCC* VCC* - I/O - P2 B20 140
GND - GND* GND* - I/O - N1 C20 143
I/O P66 AL3 D8 32 I/O P27 R5 C21 146
I/O P65 AH6 C7 35 I/O P26 M2 A22 149
I/O P64 AP2 B7 38 VCC P25 VCC* VCC* -
I/O P63 AK4 D9 41 I/O P23 L3 B22 152
I/O P62 AG5 D10 44 I/O P22 T6 C22 155
I/O P61 AF6 C9 47 I/O P21 N5 B23 158
I/O P60 AL5 B9 50 I/O P20 M4 A24 161
I/O P59 AJ3 C10 53 GND P19 GND* GND* -
GND P58 GND* GND* - I/O P18 K2 D22 164
I/O P57 AH2 B10 56 I/O P17 K4 C23 167
I/O P56 AE5 A10 59 I/O P16 P6 B24 170
I/O P55 AM4 C11 62 I/O P15 M6 C24 173
I/O P54 AD6 D12 65 I/O P14 J3 A26 176
VCC P52 VCC* VCC* - I/O P13 H2 C25 179
I/O P51 AG3 B11 68 I/O (A12) P12 H4 D24 182
I/O P50 AG1 C12 71 I/O (A13) P10 G3 B26 185
I/O - AC5 C13 74 GND - GND* GND* -
I/O - AE1 A12 77 VCC - VCC* VCC* -
I/O P49 AH4 D14 80 I/O P9 K6 A27 188
I/O P48 AB6 B13 83 I/O P8 G1 D25 191
GND - GND* GND* - I/O - E1 C26 194
VCC - VCC* VCC* - I/O - E3 B27 197
I/O (A4) P47 AD2 C14 86 I/O P7 J7 C27 200
I/O (A5) P46 AB4 A13 89 I/O P6 H6 B28 203
I/O P45 AE3 B14 92 I/O P5 C3 D27 206
I/O P44 AC1 D15 95 I/O P4 D2 B29 209
I/O (A21) P43 AD4 C15 98 I/O (A14) P3 E5 C28 212
I/O (A20) P42 AA5 B15 101 I/O, GCK8 (A15) P2 G7 D28 215
I/O (A6) P41 AA3 B16 104 VCC P1 VCC* VCC* -
I/O (A7) P40 Y6 A16 107 4/2/96
GND P39 GND* GND* -
VCC P38 VCC* VCC* - Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
I/O (A8) P37 W3 D17 110
connection to any specific package pin.
I/O (A9) P36 Y2 A17 113
I/O (A19) P35 V4 C18 116 Pads labelled VCC* are internally bonded to a Vcc plane
I/O (A18) P34 T2 D18 119 within the associated package. They have no direct con-
I/O P33 U1 B18 122 nection to any specific package pin.
I/O P32 V6 A19 125

September 18, 1996 (Version 1.04) 4-121

XC4000 Series Field Programmable Gate Arrays

Additional No Connect (N.C.) Connections on HQ304 Additional No Connect, Vcc & Ground Connections on
Package BG432 Package

N.C. N.C. N.C. N.C. VCC GND

P11 P176 A4 AG1 A1 A2
P24 P205 A8 AH6 A11 A3
P53 P254 A15 AH9 A21 A7
A28 AH19 A31 A9
P100 P281
B8 AH23 C3 A14
P128
B12 AJ5 C29 A18
3/22/96 B17 AJ8 D11 A23
B21 AJ12 D21 A25
B25 AJ15 L1 A29
Additional No Connect, Vcc & Ground Connections on
C8 AJ20 L4 A30
PG411 Package
C16 AJ26 L28 B1
N.C. N.C. VCC GND C17 AK11 L31 B2
A13 AA37 A3 A9 D6 AK17 AA1 B30
B6 AB2 A11 A19 D13 AK24 AA4 B31
B34 AC3 A21 A29 D20 AK27 AA28 C1
D23 AL15 AA31 C31
C7 AC39 A31 A37
D26 AL17 AH11 D16
C15 AF2 C39 C1
E2 AH21 G1
C23 AF38 D6 D14
F1 AJ3 G31
C25 AJ5 F36 D20 F4 AJ29 J1
C33 AK2 J1 D26 F28 AL1 J31
D8 AK38 L39 D34 F29 AL11 P1
D12 AL35 W1 F4 F30 AL21 P31
D30 AN1 AA39 J39 F31 AL31 T4
D32 AN5 AJ1 L1 G3 T28
E7 AP8 AL39 P4 M3 V1
E23 AP30 AP4 P36 M4 V31
M28 AC1
E37 AP38 AT34 W39
M30 AC31
F2 AR37 AU1 Y4
N1 AE1
F18 AT2 AW9 Y36
N2 AE31
F22 AT30 AW19 AA1 N29 AH16
G5 AU5 AW29 AF4 N30 AJ1
H34 AU9 AW37 AF36 V2 AJ31
J5 AU13 AJ39 V28 AK1
K36 AU15 AL1 W1 AK2
K38 AU17 AP36 W2 AK30
L5 AU25 AT6 W28 AK31
W31 AL2
L35 AU37 AT14
Y1 AL3
N3 AV8 AT20
Y31 AL7
P38 AV26 AT26
AC4 AL9
R3 AV34 AU39 AD2 AL14
V2 AW15 AW3 AD30 AL18
W5 AW23 AW11 AD31 AL23
W35 AW25 AW21 AE4 AL25
Y38 AW35 AW31 AF29 AL29
AF30 AL30
3/26/96
3/22/96

4-122 September 18, 1996 (Version 1.04)

Pin Locations for XC4044EX/XL Devices XC4044EX/XL
PG411 BG432 Bndry Scan
Pad Name
The following table may contain pinout information for
I/O C19 T31 359
unsupported device/package combinations. Please see the
GND GND* GND* -
availability charts elsewhere in the XC4000 Series data
VCC VCC* VCC* -
sheet for availability information.
I/O F20 T30 362
XC4044EX/XL I/O B20 T29 365
PG411 BG432 Bndry Scan
Pad Name I/O C21 U31 368
GND GND* GND* - I/O B22 U30 371
I/O, GCK1 (A16) H8 D29 242 I/O E21 U28 374
I/O (A17) F6 C30 245 I/O D22 U29 377
I/O B4 E28 248 I/O A23 V30 380
I/O D4 E29 251 I/O B24 V29 383
I/O, TDI B2 D30 254 I/O C23 V28 386
I/O, TCK G9 D31 257 I/O F22 W31 389
I/O F8 E30 260 VCC VCC* VCC* -
I/O C5 E31 263 GND GND* GND* -
I/O A7 G28 266 I/O A25 W30 392
I/O A5 G29 269 I/O D24 W29 395
VCC VCC* VCC* - I/O B26 Y30 398
GND GND* GND* - I/O A27 Y29 401
I/O C7 F30 272 I/O C27 Y28 404
I/O D8 F31 275 I/O F24 AA30 407
I/O B8 H28 278 VCC VCC* VCC* -
I/O C9 H29 281 I/O E25 AA29 410
I/O E9 G30 284 I/O E27 AB31 413
I/O F12 H30 287 I/O B28 AB30 416
I/O D10 J28 290 I/O, FCLK2 C29 AB29 419
I/O B10 J29 293 GND GND* GND* -
I/O F10 H31 296 I/O F26 AB28 422
I/O F14 J30 299 I/O D28 AC30 425
GND GND* GND* - I/O B30 AC29 428
I/O, FCLK1 C11 K28 302 I/O E29 AC28 431
I/O B12 K29 305 I/O D30 AD31 434
I/O, TMS E11 K30 308 I/O D32 AD30 437
I/O E15 K31 311 I/O F28 AD29 440
VCC VCC* VCC* - I/O F30 AD28 443
I/O F16 L29 314 I/O C31 AE30 446
I/O C13 L30 317 I/O E31 AE29 449
I/O B14 M29 320 GND GND* GND* -
I/O E17 M31 323 VCC VCC* VCC* -
I/O E13 N31 326 I/O B32 AF31 452
I/O A15 N28 329 I/O A33 AE28 455
GND GND* GND* - I/O A35 AG31 458
VCC VCC* VCC* - I/O F32 AF28 461
I/O F18 N29 332 I/O C35 AG30 464
I/O C15 N30 335 I/O B38 AG29 467
I/O B16 P30 338 I/O E33 AH31 470
I/O D16 P28 341 I/O G31 AG28 473
I/O D18 P29 344 I/O H32 AH30 476
I/O A17 R31 347 I/O, GCK2 B36 AJ30 479
I/O E19 R30 350 O (M1) A39 AH29 482
I/O B18 R28 353 GND GND* GND* -
I/O C17 R29 356 I (M0) E35 AH28 485

September 18, 1996 (Version 1.04) 4-123

XC4000 Series Field Programmable Gate Arrays

XC4044EX/XL XC4044EX/XL
PG411 BG432 Bndry Scan PG411 BG432 Bndry Scan
Pad Name Pad Name
VCC VCC* VCC* - I/O Y38 AL15 613
I (M2) G33 AJ28 486 I/O AA37 AJ15 616
I/O, GCK3 D36 AK29 487 I/O AB38 AK15 619
I/O (HDC) C37 AH27 490 I/O AD36 AJ14 622
I/O F34 AK28 493 I/O AA35 AH14 625
I/O J33 AJ27 496 I/O AE37 AK14 628
I/O D38 AL28 499 I/O AB36 AL13 631
I/O (LDC) G35 AH26 502 I/O AD38 AK13 634
I/O E39 AL27 505 VCC VCC* VCC* -
I/O K34 AH25 508 GND GND* GND* -
I/O F38 AK26 511 I/O AB34 AJ13 637
I/O G37 AL26 514 I/O AE39 AH13 640
VCC VCC* VCC* - I/O AM36 AL12 643
GND GND* GND* - I/O AC35 AK12 646
I/O H38 AH24 517 I/O AG39 AH12 649
I/O J37 AJ25 520 I/O AG37 AJ11 652
I/O G39 AK25 523 VCC VCC* VCC* -
I/O M34 AJ24 526 I/O AD34 AL10 655
I/O K36 AH23 529 I/O AN39 AK10 658
I/O K38 AK24 532 I/O AE35 AJ10 661
I/O N35 AL24 535 I/O AH38 AK9 664
I/O P34 AH22 538 GND GND* GND* -
I/O J35 AJ23 541 I/O AJ37 AL8 667
I/O L37 AK23 544 I/O AG35 AH10 670
GND GND* GND* - I/O AF34 AJ9 673
I/O M38 AJ22 547 I/O AH36 AK8 676
I/O R35 AK22 550 I/O AK38 AJ8 679
I/O H36 AL22 553 I/O AP38 AH9 682
I/O T34 AJ21 556 I/O AK36 AK7 685
VCC VCC* VCC* - I/O AM34 AL6 688
I/O N37 AH20 559 I/O AH34 AJ7 691
I/O N39 AK21 562 I/O AJ35 AH8 694
I/O U35 AK20 565 GND GND* GND* -
I/O R39 AJ19 568 VCC VCC* VCC* -
I/O M36 AL20 571 I/O AL37 AK6 697
I/O V34 AH18 574 I/O AT38 AL5 700
GND GND* GND* - I/O AM38 AH7 703
VCC VCC* VCC* - I/O AN37 AJ6 706
I/O R37 AK19 577 I/O AK34 AK5 709
I/O T38 AJ18 580 I/O AR39 AL4 712
I/O T36 AL19 583 I/O AN35 AK4 715
I/O V36 AK18 586 I/O AL33 AH5 718
I/O U37 AH17 589 I/O AV38 AK3 721
I/O U39 AJ17 592 I/O, GCK4 AT36 AJ4 724
I/O W35 AK17 595 GND GND* GND* -
I/O AC39 AL17 598 DONE AR35 AH4 -
I/O V38 AJ16 601 VCC VCC* VCC* -
I/O (INIT) W37 AK16 604 PROGRAM AN33 AH3 -
VCC VCC* VCC* - I/O (D7) AM32 AJ2 727
GND GND* GND* - I/O, GCK5 AP34 AG4 730
I/O Y34 AL16 607 I/O AW39 AG3 733
I/O AC37 AH15 610 I/O AN31 AH2 736

4-124 September 18, 1996 (Version 1.04)

 XC4044EX/XL XC4044EX/XL
PG411 BG432 Bndry Scan PG411 BG432 Bndry Scan
Pad Name Pad Name
I/O AV36 AH1 739 I/O AU17 N1 871
I/O AR33 AF4 742 I/O AW15 N2 874
I/O AP32 AF3 745 VCC VCC* VCC* -
I/O AU35 AG2 748 GND GND* GND* -
I/O AW33 AE3 751 I/O AR17 N3 877
I/O AU33 AF2 754 I/O AT16 N4 880
VCC VCC* VCC* - I/O AV14 M1 883
GND GND* GND* - I/O AW13 M2 886
I/O (D6) AV32 AF1 757 I/O (D2) AR15 L2 889
I/O AU31 AD4 760 I/O AP16 L3 892
I/O AR31 AD3 763 VCC VCC* VCC* -
I/O AP28 AE2 766 I/O AV12 K1 895
I/O AP30 AD2 769 I/O, FCLK4 AR13 K2 898
I/O AT30 AC4 772 I/O AU11 K3 901
I/O AT32 AC3 775 I/O AT12 K4 904
I/O AV30 AD1 778 GND GND* GND* -
I/O AR29 AC2 781 I/O AP14 J2 907
I/O AP26 AB4 784 I/O AR11 J3 910
GND GND* GND* - I/O AV10 J4 913
I/O AU29 AB3 787 I/O AT8 H1 916
I/O AV28 AB2 790 I/O AT10 H2 919
I/O, FCLK3 AT28 AB1 793 I/O AP10 H3 922
I/O AR25 AA3 796 I/O AP12 H4 925
VCC VCC* VCC* - I/O AR9 G2 928
I/O (D5) AP24 AA2 799 I/O AU9 G3 931
I/O (CS0) AU27 Y2 802 I/O AV8 F1 934
I/O AR27 Y4 805 GND GND* GND* -
I/O AW27 Y3 808 VCC VCC* VCC* -
I/O AT24 W4 811 I/O (D1) AU7 G4 937
I/O AR23 W3 814 I/O (RCLK, AW7 F2 940
GND GND* GND* - RDY/BUSY)
VCC VCC* VCC* - I/O AW5 F3 943
I/O AW25 W2 817 I/O AV6 E1 946
I/O AW23 V2 820 I/O AR7 E3 949
I/O AP22 V4 823 I/O AV4 D1 952
I/O AV24 V3 826 I/O AN9 E4 955
I/O AU23 U1 829 I/O AW1 D2 958
I/O AT22 U2 832 I/O (D0, DIN) AP6 C2 961
I/O AR21 U4 835 I/O, GCK6 AU3 D3 964
(DOUT)
I/O AV22 U3 838
CCLK AR5 D4 -
I/O (D4) AP20 T1 841
VCC VCC* VCC* -
I/O AU21 T2 844
O, TDO AN7 C4 0
VCC VCC* VCC* -
GND GND* GND* -
GND GND* GND* -
I/O (A0, WS) AT4 B3 2
I/O (D3) AU19 T3 847
I/O, GCK7 (A1) AV2 D5 5
I/O (RS) AV20 R1 850
I/O AM8 B4 8
I/O AV18 R2 853
I/O AL7 C5 11
I/O AR19 R4 856
I/O AR3 B5 14
I/O AT18 R3 859
I/O AR1 C6 17
I/O AW17 P2 862
I/O (CS1, A2) AK6 A5 20
I/O AV16 P3 865
I/O (A3) AN3 D7 23
I/O AP18 P4 868

September 18, 1996 (Version 1.04) 4-125

XC4000 Series Field Programmable Gate Arrays

XC4044EX/XL XC4044EX/XL
PG411 BG432 Bndry Scan PG411 BG432 Bndry Scan
Pad Name Pad Name
I/O AM6 B6 26 I/O U5 D19 152
I/O AM2 A6 29 I/O T4 A20 155
VCC VCC* VCC* - I/O P2 B20 158
GND GND* GND* - I/O N1 C20 161
I/O AL3 D8 32 I/O R5 C21 164
I/O AH6 C7 35 I/O M2 A22 167
I/O AP2 B7 38 VCC VCC* VCC* -
I/O AK4 D9 41 I/O L3 B22 170
I/O AN1 B8 44 I/O T6 C22 173
I/O AK2 A8 47 I/O N5 B23 176
I/O AG5 D10 50 I/O M4 A24 179
I/O AF6 C9 53 GND GND* GND* -
I/O AL5 B9 56 I/O K2 D22 182
I/O AJ3 C10 59 I/O K4 C23 185
GND GND* GND* - I/O P6 B24 188
I/O AH2 B10 62 I/O M6 C24 191
I/O AE5 A10 65 I/O L5 D23 194
I/O AM4 C11 68 I/O J5 B25 197
I/O AD6 D12 71 I/O J3 A26 200
VCC VCC* VCC* - I/O H2 C25 203
I/O AG3 B11 74 I/O (A12) H4 D24 206
I/O AG1 C12 77 I/O (A13) G3 B26 209
I/O AC5 C13 80 GND GND* GND* -
I/O AE1 A12 83 VCC VCC* VCC* -
I/O AH4 D14 86 I/O K6 A27 212
I/O AB6 B13 89 I/O G1 D25 215
GND GND* GND* - I/O E1 C26 218
VCC VCC* VCC* - I/O E3 B27 221
I/O (A4) AD2 C14 92 I/O J7 C27 224
I/O (A5) AB4 A13 95 I/O H6 B28 227
I/O AE3 B14 98 I/O C3 D27 230
I/O AC1 D15 101 I/O D2 B29 233
I/O (A21) AD4 C15 104 I/O (A14) E5 C28 236
I/O (A20) AA5 B15 107 I/O, GCK8 (A15) G7 D28 239
I/O AB2 A15 110 VCC VCC* VCC* -
I/O AC3 C16 113 4/2/96
I/O (A6) AA3 B16 116
I/O (A7) Y6 A16 119 Pads labelled GND* are internally bonded to a Ground
GND GND* GND* - plane within the associated package. They have no direct
VCC VCC* VCC* - connection to any specific package pin.
I/O (A8) W3 D17 122
I/O (A9) Y2 A17 125 Pads labelled VCC* are internally bonded to a Vcc plane
I/O V2 C17 128 within the associated package. They have no direct con-
I/O W5 B17 131
nection to any specific package pin.
I/O (A19) V4 C18 134
I/O (A18) T2 D18 137
I/O U1 B18 140
I/O V6 A19 143
I/O (A10) U3 B19 146
I/O (A11) R1 C19 149
VCC VCC* VCC* -
GND GND* GND* -

4-126 September 18, 1996 (Version 1.04)

Additional No Connect, Vcc & Ground Connections on Additional No Connect, Vcc & Ground Connections on
PG411 Package BG432 Package
N.C. VCC GND N.C. VCC GND
A13 A3 A9 A4 A1 A2
B6 A11 A19 A28 A11 A3
B34 A21 A29 B12 A21 A7
C25 A31 A37 B21 A31 A9
C33 C39 C1 C8 C3 A14
D12 D6 D14 D6 C29 A18
E7 F36 D20 D13 D11 A23
E23 J1 D26 D20 D21 A25
E37 L39 D34 D26 L1 A29
F2 W1 F4 E2 L4 A30
G5 AA39 J39 F4 L28 B1
H34 AJ1 L1 F28 L31 B2
L35 AL39 P4 F29 AA1 B30
N3 AP4 P36 M3 AA4 B31
P38 AT34 W39 M4 AA28 C1
R3 AU1 Y4 M28 AA31 C31
AF2 AW9 Y36 M30 AH11 D16
AF38 AW19 AA1 W1 AH21 G1
AJ5 AW29 AF4 W28 AJ3 G31
AL35 AW37 AF36 Y1 AJ29 J1
AN5 AJ39 Y31 AL1 J31
AP8 AL1 AE4 AL11 P1
AR37 AP36 AF29 AL21 P31
AT2 AT6 AF30 AL31 T4
AU5 AT14 AG1 T28
AU13 AT20 AH6 V1
AU15 AT26 AH19 V31
AU25 AU39 AJ5 AC1
AU37 AW3 AJ12 AC31
AV26 AW11 AJ20 AE1
AV34 AW21 AJ26 AE31
AW35 AW31 AK11 AH16
AK27 AJ1
3/22/96 AJ31
AK1
AK2
AK30
AK31
AL2
AL3
AL7
AL9
AL14
AL18
AL23
AL25
AL29
AL30

3/26/96

September 18, 1996 (Version 1.04) 4-127

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4052XL Devices XC4052XL Pad Name PG411 BG432 Bndry Scan
The following table may contain pinout information for GND GND* GND* -
unsupported device/package combinations. Please see the VCC VCC* VCC* -
availability charts elsewhere in the XC4000 Series data I/O F18 N29 368
sheet for availability information. I/O C15 N30 371
XC4052XL Pad Name PG411 BG432 Bndry Scan I/O B16 P30 374
GND GND* GND* - I/O D16 P28 377
I/O, GCK1 (A16) H8 D29 266 I/O D18 P29 380
I/O (A17) F6 C30 269 I/O A17 R31 383
I/O B4 E28 272 GND GND* GND* -
I/O D4 E29 275 I/O E19 R30 386
I/O, TDI B2 D30 278 I/O B18 R28 389
I/O, TCK G9 D31 281 I/O C17 R29 392
GND GND* GND* - I/O C19 T31 395
I/O E7 F28 284 GND GND* GND* -
I/O B6 F29 287 VCC VCC* VCC* -
I/O F8 E30 290 I/O F20 T30 398
I/O C5 E31 293 I/O B20 T29 401
I/O A7 G28 296 I/O C21 U31 404
I/O A5 G29 299 I/O B22 U30 407
VCC VCC* VCC* - GND GND* GND* -
GND GND* GND* - I/O E21 U28 410
I/O C7 F30 302 I/O D22 U29 413
I/O D8 F31 305 I/O A23 V30 416
I/O B8 H28 308 I/O B24 V29 419
I/O C9 H29 311 I/O C23 V28 422
I/O E9 G30 314 I/O F22 W31 425
I/O F12 H30 317 VCC VCC* VCC* -
GND GND* GND* - GND GND* GND* -
I/O D10 J28 320 I/O A25 W30 428
I/O B10 J29 323 I/O D24 W29 431
I/O F10 H31 326 I/O E23 W28 434
I/O F14 J30 329 I/O C25 Y31 437
GND GND* GND* - I/O B26 Y30 440
I/O, FCLK1 C11 K28 332 I/O A27 Y29 443
I/O B12 K29 335 GND GND* GND* -
I/O, TMS E11 K30 338 I/O C27 Y28 446
I/O E15 K31 341 I/O F24 AA30 449
VCC VCC* VCC* - VCC VCC* VCC* -
I/O F16 L29 344 I/O E25 AA29 452
I/O C13 L30 347 I/O E27 AB31 455
GND GND* GND* - I/O B28 AB30 458
I/O A13 M30 350 I/O, FCLK2 C29 AB29 461
I/O D12 M28 353 GND GND* GND* -
I/O B14 M29 356 I/O F26 AB28 464
I/O E17 M31 359 I/O D28 AC30 467
I/O E13 N31 362 I/O B30 AC29 470
I/O A15 N28 365 I/O E29 AC28 473
GND GND* GND* -

4-128 September 18, 1996 (Version 1.04)

XC4052XL Pad Name PG411 BG432 Bndry Scan XC4052XL Pad Name PG411 BG432 Bndry Scan
I/O D30 AD31 476 I/O N35 AL24 589
I/O D32 AD30 479 I/O P34 AH22 592
I/O F28 AD29 482 I/O J35 AJ23 595
I/O F30 AD28 485 I/O L37 AK23 598
I/O C31 AE30 488 GND GND* GND* -
I/O E31 AE29 491 I/O M38 AJ22 601
GND GND* GND* - I/O R35 AK22 604
VCC VCC* VCC* - I/O H36 AL22 607
I/O B32 AF31 494 I/O T34 AJ21 610
I/O A33 AE28 497 VCC VCC* VCC* -
I/O C33 AF30 500 I/O N37 AH20 613
I/O B34 AF29 503 I/O N39 AK21 616
I/O A35 AG31 506 GND GND* GND* -
I/O F32 AF28 509 I/O P38 AJ20 619
GND GND* GND* - I/O L35 AH19 622
I/O C35 AG30 512 I/O U35 AK20 625
I/O B38 AG29 515 I/O R39 AJ19 628
I/O E33 AH31 518 I/O M36 AL20 631
I/O G31 AG28 521 I/O V34 AH18 634
I/O H32 AH30 524 GND GND* GND* -
I/O, GCK2 B36 AJ30 527 VCC VCC* VCC* -
O (M1) A39 AH29 530 I/O R37 AK19 637
GND GND* GND* - I/O T38 AJ18 640
I (M0) E35 AH28 533 I/O T36 AL19 643
VCC VCC* VCC* - I/O V36 AK18 646
I (M2) G33 AJ28 534 I/O U37 AH17 649
I/O, GCK3 D36 AK29 535 I/O U39 AJ17 652
I/O (HDC) C37 AH27 538 GND GND* GND* -
I/O F34 AK28 541 I/O W35 AK17 655
I/O J33 AJ27 544 I/O AC39 AL17 658
I/O D38 AL28 547 I/O V38 AJ16 661
I/O (LDC) G35 AH26 550 I/O (INIT) W37 AK16 664
GND GND* GND* - VCC VCC* VCC* -
I/O E37 AK27 553 GND GND* GND* -
I/O H34 AJ26 556 I/O Y34 AL16 667
I/O E39 AL27 559 I/O AC37 AH15 670
I/O K34 AH25 562 I/O Y38 AL15 673
I/O F38 AK26 565 I/O AA37 AJ15 676
I/O G37 AL26 568 GND GND* GND* -
VCC VCC* VCC* - I/O AB38 AK15 679
GND GND* GND* - I/O AD36 AJ14 682
I/O H38 AH24 571 I/O AA35 AH14 685
I/O J37 AJ25 574 I/O AE37 AK14 688
I/O G39 AK25 577 I/O AB36 AL13 691
I/O M34 AJ24 580 I/O AD38 AK13 694
I/O K36 AH23 583 VCC VCC* VCC* -
I/O K38 AK24 586 GND GND* GND* 697
GND GND* GND* - I/O AB34 AJ13 700

September 18, 1996 (Version 1.04) 4-129

XC4000 Series Field Programmable Gate Arrays

XC4052XL Pad Name PG411 BG432 Bndry Scan XC4052XL Pad Name PG411 BG432 Bndry Scan
I/O AE39 AH13 703 I/O AV36 AH1 814
I/O AM36 AL12 706 I/O AR33 AF4 817
I/O AC35 AK12 709 GND GND* GND* -
I/O AL35 AJ12 712 I/O AP32 AF3 820
I/O AF38 AK11 715 I/O AU35 AG2 823
GND GND* GND* - I/O AV34 AG1 826
I/O AG39 AH12 718 I/O AW35 AE4 829
I/O AG37 AJ11 721 I/O AW33 AE3 832
VCC VCC* VCC* - I/O AU33 AF2 835
I/O AD34 AL10 724 VCC VCC* VCC* -
I/O AN39 AK10 727 GND GND* GND* -
I/O AE35 AJ10 730 I/O (D6) AV32 AF1 838
I/O AH38 AK9 733 I/O AU31 AD4 841
GND GND* GND* - I/O AR31 AD3 844
I/O AJ37 AL8 736 I/O AP28 AE2 847
I/O AG35 AH10 739 I/O AP30 AD2 850
I/O AF34 AJ9 742 I/O AT30 AC4 853
I/O AH36 AK8 745 GND GND* GND* -
GND GND* GND* - I/O AT32 AC3 856
I/O AK38 AJ8 748 I/O AV30 AD1 859
I/O AP38 AH9 751 I/O AR29 AC2 862
I/O AK36 AK7 754 I/O AP26 AB4 865
I/O AM34 AL6 757 GND GND* GND* -
I/O AH34 AJ7 760 I/O AU29 AB3 868
I/O AJ35 AH8 763 I/O AV28 AB2 871
GND GND* GND* - I/O, FCLK3 AT28 AB1 874
VCC VCC* VCC* - I/O AR25 AA3 877
I/O AL37 AK6 766 VCC VCC* VCC* -
I/O AT38 AL5 769 I/O (D5) AP24 AA2 880
I/O AM38 AH7 772 I/O (CS0) AU27 Y2 883
I/O AN37 AJ6 775 GND GND* GND* -
I/O AK34 AK5 778 I/O AR27 Y4 886
I/O AR39 AL4 781 I/O AW27 Y3 889
GND GND* GND* - I/O AU25 Y1 892
I/O AR37 AH6 784 I/O AV26 W1 895
I/O AU37 AJ5 787 I/O AT24 W4 898
I/O AN35 AK4 790 I/O AR23 W3 901
I/O AL33 AH5 793 GND GND* GND* -
I/O AV38 AK3 796 VCC VCC* VCC* -
I/O, GCK4 AT36 AJ4 799 I/O AW25 W2 904
GND GND* GND* - I/O AW23 V2 907
DONE AR35 AH4 - I/O AP22 V4 910
VCC VCC* VCC* - I/O AV24 V3 913
PROGRAM AN33 AH3 - I/O AU23 U1 916
I/O (D7) AM32 AJ2 802 I/O AT22 U2 919
I/O, GCK5 AP34 AG4 805 GND GND* GND* -
I/O AW39 AG3 808 I/O AR21 U4 922
I/O AN31 AH2 811 I/O AV22 U3 925

4-130 September 18, 1996 (Version 1.04)

XC4052XL Pad Name PG411 BG432 Bndry Scan XC4052XL Pad Name PG411 BG432 Bndry Scan
I/O (D4) AP20 T1 928 I/O AW5 F3 1036
I/O AU21 T2 931 I/O AV6 E1 1039
VCC VCC* VCC* - I/O AU5 F4 1042
GND GND* GND* - I/O AP8 E2 1045
I/O (D3) AU19 T3 934 GND GND* GND* -
I/O (RS) AV20 R1 937 I/O AR7 E3 1048
I/O AV18 R2 940 I/O AV4 D1 1051
I/O AR19 R4 943 I/O AN9 E4 1054
GND GND* GND* - I/O AW1 D2 1057
I/O AT18 R3 946 I/O (D0, DIN) AP6 C2 1060
I/O AW17 P2 949 I/O, GCK6 (DOUT) AU3 D3 1063
I/O AV16 P3 952 CCLK AR5 D4 -
I/O AP18 P4 955 VCC VCC* VCC* -
I/O AU17 N1 958 O, TDO AN7 C4 0
I/O AW15 N2 961 GND GND* GND* -
VCC VCC* VCC* - I/O (A0, WS) AT4 B3 2
GND GND* GND* - I/O, GCK7 (A1) AV2 D5 5
I/O AR17 N3 964 I/O AM8 B4 8
I/O AT16 N4 967 I/O AL7 C5 11
I/O AV14 M1 970 I/O AT2 A4 14
I/O AW13 M2 973 I/O AN5 D6 17
I/O AU15 M3 976 GND GND* GND* -
I/O AU13 M4 979 I/O AR3 B5 20
GND GND* GND* - I/O AR1 C6 23
I/O (D2) AR15 L2 982 I/O (CS1, A2) AK6 A5 26
I/O AP16 L3 985 I/O (A3) AN3 D7 29
VCC VCC* VCC* - I/O AM6 B6 32
I/O AV12 K1 988 I/O AM2 A6 35
I/O, FCLK4 AR13 K2 991 VCC VCC* VCC* -
I/O AU11 K3 994 GND GND* GND* -
I/O AT12 K4 997 I/O AL3 D8 38
GND GND* GND* - I/O AH6 C7 41
I/O AP14 J2 1000 I/O AP2 B7 44
I/O AR11 J3 1003 I/O AK4 D9 47
I/O AV10 J4 1006 I/O AN1 B8 50
I/O AT8 H1 1009 I/O AK2 A8 53
GND GND* GND* - GND GND* GND* -
I/O AT10 H2 1012 I/O AG5 D10 56
I/O AP10 H3 1015 I/O AF6 C9 59
I/O AP12 H4 1018 I/O AL5 B9 62
I/O AR9 G2 1021 I/O AJ3 C10 65
I/O AU9 G3 1024 GND GND* GND* -
I/O AV8 F1 1027 I/O AH2 B10 68
GND GND* GND* - I/O AE5 A10 71
VCC VCC* VCC* - I/O AM4 C11 74
I/O (D1) AU7 G4 1030 I/O AD6 D12 77
I/O (RCLK, AW7 F2 1033 VCC VCC* VCC* -
RDY/BUSY) I/O AG3 B11 80

September 18, 1996 (Version 1.04) 4-131

XC4000 Series Field Programmable Gate Arrays

XC4052XL Pad Name PG411 BG432 Bndry Scan XC4052XL Pad Name PG411 BG432 Bndry Scan
I/O AG1 C12 83 I/O N5 B23 194
GND GND* GND* - I/O M4 A24 197
I/O AF2 D13 86 GND GND* GND* -
I/O AJ5 B12 89 I/O K2 D22 200
I/O AC5 C13 92 I/O K4 C23 203
I/O AE1 A12 95 I/O P6 B24 206
I/O AH4 D14 98 I/O M6 C24 209
I/O AB6 B13 101 GND GND* GND* -
GND GND* GND* - I/O L5 D23 212
VCC VCC* VCC* - I/O J5 B25 215
I/O (A4) AD2 C14 104 I/O J3 A26 218
I/O (A5) AB4 A13 107 I/O H2 C25 221
I/O AE3 B14 110 I/O (A12) H4 D24 224
I/O AC1 D15 113 I/O (A13) G3 B26 227
I/O (A21) AD4 C15 116 GND GND* GND* -
I/O (A20) AA5 B15 119 VCC VCC* VCC* -
GND GND* GND* - I/O K6 A27 230
I/O AB2 A15 122 I/O G1 D25 233
I/O AC3 C16 125 I/O E1 C26 236
I/O (A6) AA3 B16 128 I/O E3 B27 239
I/O (A7) Y6 A16 131 I/O F2 A28 242
GND GND* GND* - I/O G5 D26 245
VCC VCC* VCC* - GND GND* GND* -
I/O (A8) W3 D17 134 I/O J7 C27 248
I/O (A9) Y2 A17 137 I/O H6 B28 251
I/O V2 C17 140 I/O C3 D27 254
I/O W5 B17 143 I/O D2 B29 257
GND GND* GND* - I/O (A14) E5 C28 260
I/O (A19) V4 C18 146 I/O, GCK8 (A15) G7 D28 263
I/O (A18) T2 D18 149 VCC VCC* VCC* -
I/O U1 B18 152 8/23/96
I/O V6 A19 155
I/O (A10) U3 B19 158 Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
I/O (A11) R1 C19 161
connection to any specific package pin.
VCC VCC* VCC* -
GND GND* GND* - Pads labelled VCC* are internally bonded to a Vcc plane
I/O U5 D19 164 within the associated package. They have no direct con-
I/O T4 A20 167 nection to any specific package pin.
I/O P2 B20 170
I/O N1 C20 173
I/O R3 B21 176
I/O N3 D20 179
GND GND* GND* -
I/O R5 C21 182
I/O M2 A22 185
VCC VCC* VCC* -
I/O L3 B22 188
I/O T6 C22 191

4-132 September 18, 1996 (Version 1.04)

Additional Vcc & Ground Connections on PG411 Additional No Connect, Vcc & Ground Connections on
Package BG432 Package
VCC GND N.C. VCC GND
A3 A9 C8 A1 A2
A11 A19 A11 A3
A21 A29 A21 A7
A31 A37 A31 A9
C39 C1 C3 A14
D6 D14 C29 A18
F36 D20 D11 A23
J1 D26 D21 A25
L39 D34 L1 A29
W1 F4 L4 A30
AA39 J39 L28 B1
AJ1 L1 L31 B2
AL39 P4 AA1 B30
AP4 P36 AA4 B31
AT34 W39 AA28 C1
AU1 Y4 AA31 C31
AW9 Y36 AH11 D16
AW19 AA1 AH21 G1
AW29 AF4 AJ3 G31
AW37 AF36 AJ29 J1
AJ39 AL1 J31
AL1 AL11 P1
AP36 AL21 P31
AT6 AL31 T4
AT14 T28
AT20 V1
AT26 V31
AU39 AC1
AW3 AC31
AW11 AE1
AW21 AE31
AW31 AH16
AJ1
8/23/96
AJ31
AK1
AK2
AK30
AK31
AL2
AL3
AL7
AL9
AL14
AL18
AL23
AL25
AL29
AL30

3/22/96

September 18, 1996 (Version 1.04) 4-133

XC4000 Series Field Programmable Gate Arrays

Package-Specific Pinout Tables

PC84 Package Pinouts Pin XC4003E
XC4005E
XC4006E XC4008E
XC4010E
XC4005L XC4010L
The following table may contain pinout information for P43 GND GND GND GND GND
unsupported device/package combinations. Please see the P44 I/O I/O I/O I/O I/O
availability charts elsewhere in the XC4000 Series data P45 I/O I/O I/O I/O I/O
sheet for availability information. P46 I/O I/O I/O I/O I/O
XC4005E XC4010E P47 I/O I/O I/O I/O I/O
Pin XC4003E XC4006E XC4008E P48 I/O I/O I/O I/O I/O
XC4005L XC4010L
P1 GND GND GND GND GND P49 I/O I/O I/O I/O I/O
P2 VCC VCC VCC VCC VCC P50 I/O I/O I/O I/O I/O
P3 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) P51 I/O, I/O, I/O, I/O, I/O,
P4 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) SGCK3 SGCK3 SGCK3 SGCK3 SGCK3
P5 I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A10) P52 GND GND GND GND GND
P6 I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A11) P53 DONE DONE DONE DONE DONE
P7 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12) P54 VCC VCC VCC VCC VCC
P8 I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A13) P55 PRO- PRO- PRO- PRO- PRO-
GRAM GRAM GRAM GRAM GRAM
P9 I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14)
P56 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7)
P10 I/O, I/O, I/O, I/O, I/O,
SGCK1 SGCK1 SGCK1 SGCK1 SGCK1 P57 I/O, I/O, I/O, I/O, I/O,
(A15) (A15) (A15) (A15) (A15) PGCK3 PGCK3 PGCK3 PGCK3 PGCK3
P11 VCC VCC VCC VCC VCC P58 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6)
P12 GND GND GND GND GND P59 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5)
P13 I/O, I/O, I/O, I/O, I/O, P60 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0)
PGCK1 PGCK1 PGCK1 PGCK1 PGCK1 P61 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4)
(A16) (A16) (A16) (A16) (A16) P62 I/O I/O I/O I/O I/O
P14 I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O (A17) P63 VCC VCC VCC VCC VCC
P15 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI P64 GND GND GND GND GND
P16 I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TCK P65 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3)
P17 I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O, TMS P66 I/O (RS) I/O (RS) I/O (RS) I/O (RS) I/O (RS)
P18 I/O I/O I/O I/O I/O P67 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2)
P19 I/O I/O I/O I/O I/O P68 I/O I/O I/O I/O I/O
P20 I/O I/O I/O I/O I/O P69 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1)
P21 GND GND GND GND GND P70 I/O (RCLK, I/O (RCLK, I/O (RCLK, I/O (RCLK, I/O (RCLK,
P22 VCC VCC VCC VCC VCC RDY/ RDY/ RDY/ RDY/ RDY/
P23 I/O I/O I/O I/O I/O BUSY) BUSY) BUSY) BUSY) BUSY)
P24 I/O I/O I/O I/O I/O P71 I/O I/O I/O I/O I/O
(D0, DIN) (D0, DIN) (D0, DIN) (D0, DIN) (D0, DIN)
P25 I/O I/O I/O I/O I/O
P72 I/O, I/O, I/O, I/O, I/O,
P26 I/O I/O I/O I/O I/O SGCK4 SGCK4 SGCK4 SGCK4 SGCK4
P27 I/O I/O I/O I/O I/O (DOUT) (DOUT) (DOUT) (DOUT) (DOUT)
P28 I/O I/O I/O I/O I/O P73 CCLK CCLK CCLK CCLK CCLK
P29 I/O, I/O, I/O, I/O, I/O, P74 VCC VCC VCC VCC VCC
SCGK2 SCGK2 SCGK2 SCGK2 SCGK2 P75 O, TDO O, TDO O, TDO O, TDO O, TDO
P30 O (M1) O (M1) O (M1) O (M1) O (M1) P76 GND GND GND GND GND
P31 GND GND GND GND GND P77 I/O I/O I/O I/O I/O
P32 I (M0) I (M0) I (M0) I (M0) I (M0) (A0, WS) (A0, WS) (A0, WS) (A0, WS) (A0, WS)
P33 VCC VCC VCC VCC VCC P78 I/O, I/O, I/O, I/O, I/O,
P34 I (M2) I (M2) I (M2) I (M2) I (M2) PGCK4 PGCK4 PGCK4 PGCK4 PGCK4
P35 I/O, I/O, I/O, I/O, I/O, (A1) (A1) (A1) (A1) (A1)
PGCK2 PGCK2 PGCK2 PGCK2 PGCK2 P79 I/O I/O I/O I/O I/O
P36 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) (CS1, A2) (CS1, A2) (CS1, A2) (CS1, A2) (CS1, A2)
P37 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) P80 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3)
P38 I/O I/O I/O I/O I/O P81 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4)
P39 I/O I/O I/O I/O I/O P82 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5)
P40 I/O I/O I/O I/O I/O P83 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6)
P41 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) P84 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7)
P42 VCC VCC VCC VCC VCC 2/28/96

4-134 September 18, 1996 (Version 1.04)

PQ100 Package Pinouts PQ100 Pin XC4003E XC4005E
P50 I/O I/O
The following table may contain pinout information for
P51 I/O, SGCK3 I/O, SGCK3
unsupported device/package combinations. Please see the
P52 GND GND
availability charts elsewhere in the XC4000 Series data
P53 DONE DONE
sheet for availability information.
P54 VCC VCC
PQ100 Pin XC4003E XC4005E P55 PROGRAM PROGRAM
P1 I/O (A14) I/O (A14) P56 I/O (D7) I/O (D7)
P2 I/O, SGCK1 (A15) I/O, SGCK1 (A15) P57 I/O, PGCK3 I/O, PGCK3
P3 VCC VCC P58 I/O (D6) I/O (D6)
P4 GND GND P59 I/O I/O
P5 I/O, PGCK1 (A16) I/O, PGCK1 (A16) P60 I/O (D5) I/O (D5)
P6 I/O (A17) I/O (A17) P61 I/O (CS0) I/O (CS0)
P7 I/O, TDI I/O, TDI P62 I/O I/O
P8 I/O, TCK I/O, TCK P63 I/O I/O
P9 I/O, TMS I/O, TMS P64 I/O (D4) I/O (D4)
P10 I/O I/O P65 I/O I/O
P11 I/O I/O P66 VCC VCC
P12 I/O I/O P67 GND GND
P13 I/O I/O P68 I/O (D3) I/O (D3)
P14 GND GND P69 I/O (RS) I/O (RS)
P15 VCC VCC P70 I/O I/O
P16 I/O I/O P71 I/O (D2) I/O (D2)
P17 I/O I/O P72 I/O I/O
P18 I/O I/O P73 I/O (D1) I/O (D1)
P19 I/O I/O P74 I/O (RCLK, I/O (RCLK,
P20 I/O I/O RDY/BUSY) RDY/BUSY)
P21 I/O I/O P75 I/O (D0, DIN) I/O (D0, DIN)
P22 I/O I/O P76 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT)
P23 I/O I/O P77 CCLK CCLK
P24 I/O, SCGK2 I/O, SCGK2 P78 VCC VCC
P25 O (M1) O (M1) P79 O, TDO O, TDO
P26 GND GND P80 GND GND
P27 I (M0) I (M0) P81 I/O (A0, WS) I/O (A0, WS)
P28 VCC VCC P82 I/O, PGCK4 (A1) I/O, PGCK4 (A1)
P29 I (M2) I (M2) P83 I/O (CS1, A2) I/O (CS1, A2)
P30 I/O, PGCK2 I/O, PGCK2 P84 I/O (A3) I/O (A3)
P31 I/O (HDC) I/O (HDC) P85 I/O (A4) I/O (A4)
P32 I/O I/O P86 I/O (A5) I/O (A5)
P33 I/O (LDC) I/O (LDC) P87 I/O I/O
P34 I/O I/O P88 I/O I/O
P35 I/O I/O P89 I/O (A6) I/O (A6)
P36 I/O I/O P90 I/O (A7) I/O (A7)
P37 I/O I/O P91 GND GND
P38 I/O I/O P92 VCC VCC
P39 I/O (INIT) I/O (INIT) P93 I/O (A8) I/O (A8)
P40 VCC VCC P94 I/O (A9) I/O (A9)
P41 GND GND P95 I/O I/O
P42 I/O I/O P96 I/O I/O
P43 I/O I/O P97 I/O (A10) I/O (A10)
P44 I/O I/O P98 I/O (A11) I/O (A11)
P45 I/O I/O P99 I/O (A12) I/O (A12)
P46 I/O I/O P100 I/O (A13) I/O (A13)
P47 I/O I/O 2/28/96
P48 I/O I/O
P49 I/O I/O

September 18, 1996 (Version 1.04) 4-135

XC4000 Series Field Programmable Gate Arrays

VQ100 Package Pinouts VQ100 Pin XC4003E

P49 GND
The following table may contain pinout information for
P50 DONE
unsupported device/package combinations. Please see the
P51 VCC
availability charts elsewhere in the XC4000 Series data
sheet for availability information. P52 PROGRAM
P53 I/O (D7)
VQ100 Pin XC4003E P54 I/O, PGCK3
P1 GND P55 I/O (D6)
P2 I/O, PGCK1 (A16) P56 I/O
P3 I/O (A17) P57 I/O (D5)
P4 I/O, TDI P58 I/O (CS0)
P5 I/O, TCK P59 I/O
P6 I/O, TMS P60 I/O
P7 I/O P61 I/O (D4)
P8 I/O P62 I/O
P9 I/O P63 VCC
P10 I/O P64 GND
P11 GND P65 I/O (D3)
P12 VCC P66 I/O (RS)
P13 I/O P67 I/O
P14 I/O P68 I/O (D2)
P15 I/O P69 I/O
P16 I/O P70 I/O (D1)
P17 I/O P71 I/O (RCLK, RDY/BUSY)
P18 I/O P72 I/O (D0, DIN)
P19 I/O P73 I/O, SGCK4 (DOUT)
P20 I/O P74 CCLK
P21 I/O, SCGK2 P75 VCC
P22 O (M1) P76 O, TDO
P23 GND P77 GND
P24 I (M0) P78 I/O (A0, WS)
P25 VCC P79 I/O, PGCK4 (A1)
P26 I (M2) P80 I/O (CS1, A2)
P27 I/O, PGCK2 P81 I/O (A3)
P28 I/O (HDC) P82 I/O (A4)
P29 I/O P83 I/O (A5)
P30 I/O (LDC) P84 I/O
P31 I/O P85 I/O
P32 I/O P86 I/O (A6)
P33 I/O P87 I/O (A7)
P34 I/O P88 GND
P35 I/O P89 VCC
P36 I/O (INIT) P90 I/O (A8)
P37 VCC P91 I/O (A9)
P38 GND P92 I/O
P39 I/O P93 I/O
P40 I/O P94 I/O (A10)
P41 I/O P95 I/O (A11)
P42 I/O P96 I/O (A12)
P43 I/O P97 I/O (A13)
P44 I/O P98 I/O (A14)
P45 I/O P99 I/O, SGCK1 (A15)
P46 I/O P100 VCC
P47 I/O
2/28/96
P48 I/O, SGCK3

4-136 September 18, 1996 (Version 1.04)

PG120 Package Pinouts PG120 Pin XC4003E
The following table may contain pinout information for K3 GND
unsupported device/package combinations. Please see the K2 I/O (CS1, A2)
availability charts elsewhere in the XC4000 Series data K1 I/O (A5)
sheet for availability information. J13 I/O
PG120 Pin XC4003E J12 I/O
N13 I/O, PGCK3 J11 N.C.
N12 N.C. J3 N.C.
N11 I/O J2 I/O (A4)
N10 I/O (CS0) J1 I/O
N9 I/O H13 I/O
N8 I/O H12 I/O
N7 I/O (D3) H11 I/O
N6 I/O (RS) H3 I/O
N5 I/O H2 I/O (A6)
N4 I/O H1 I/O (A7)
N3 I/O (RCLK, RDY/BUSY) G13 I/O
N2 I/O (D0, DIN) G12 VCC
N1 I/O, PGCK4 (A1) G11 GND
M13 I/O G3 VCC
M12 PROGRAM G2 GND
M11 I/O (D7) G1 I/O (A8)
M10 I/O (D6) F13 I/O (INIT)
M9 I/O (D5) F12 I/O
M8 I/O (D4) F11 I/O
M7 VCC F3 I/O (A10)
M6 I/O F2 I/O
M5 I/O (D1) F1 I/O (A9)
M4 N.C. E13 I/O
M3 I/O, SGCK4 (DOUT) E12 I/O
M2 O, TDO E11 N.C.
M1 N.C. E3 N.C.
L13 I/O E2 N.C.
L12 I/O, SGCK3 E1 I/O
L11 DONE D13 I/O
L10 VCC D12 I/O
L9 N.C. D11 VCC
L8 I/O D3 I/O, SGCK1 (A15)
L7 GND D2 I/O (A13)
L6 I/O (D2) D1 I/O (A11)
L5 N.C. C13 I/O (LDC)
L4 CCLK C12 I/O, PGCK2
L3 VCC C11 I (M0)
L2 I/O (A0, WS) C10 GND
L1 I/O (A3) C9 I/O
K13 I/O C8 I/O
K12 N.C. C7 VCC
K11 GND C6 I/O
C5 I/O, TDI

September 18, 1996 (Version 1.04) 4-137

XC4000 Series Field Programmable Gate Arrays

PG120 Pin XC4003E PG120 Pin XC4003E

C4 GND A12 I/O, SCGK2
C3 VCC A11 I/O
C2 I/O (A14) A10 I/O
C1 I/O (A12) A9 I/O
B13 N.C. A8 I/O
B12 I (M2) A7 I/O
B11 O (M1) A6 I/O
B10 N.C. A5 I/O
B9 I/O A4 I/O
B8 I/O A3 N.C.
B7 GND A2 N.C.
B6 I/O A1 N.C.
B5 I/O, TMS 3/13/96
B4 I/O, TCK
B3 I/O (A17) Note: Viewed from the bottom side, the package pins start
B2 I/O, PGCK1 (A16) at the top row and go from the left edge to the right edge.
B1 N.C. Viewed from the top side, the pins start at the top row and
A13 I/O (HDC) go from the right edge to the left edge.

4-138 September 18, 1996 (Version 1.04)

TQ144 Package Pinouts TQ144 Pin XC4005E XC4006E
The following table may contain pinout information for P43 I/O I/O
unsupported device/package combinations. Please see the P44 I/O (LDC) I/O (LDC)
availability charts elsewhere in the XC4000 Series data P45 GND GND
sheet for availability information. P46 I/O I/O
TQ144 Pin XC4005E XC4006E P47 I/O I/O
P1 GND GND P48 I/O I/O
P2 I/O, PGCK1 (A16) I/O, PGCK1 (A16) P49 I/O I/O
P3 I/O (A17) I/O (A17) P50 I/O I/O
P4 I/O I/O P51 I/O I/O
P5 I/O I/O P52 I/O I/O
P6 I/O, TDI I/O, TDI P53 I/O (INIT) I/O (INIT)
P7 I/O, TCK I/O, TCK P54 VCC VCC
P8 GND GND P55 GND GND
P9 I/O I/O P56 I/O I/O
P10 I/O I/O P57 I/O I/O
P11 I/O, TMS I/O, TMS P58 I/O I/O
P12 I/O I/O P59 I/O I/O
P13 I/O I/O P60 I/O I/O
P14 I/O I/O P61 I/O I/O
P15 I/O I/O P62 I/O I/O
P16 I/O I/O P63 I/O I/O
P17 GND GND P64 GND GND
P18 VCC VCC P65 I/O I/O
P19 I/O I/O P66 I/O I/O
P20 I/O I/O P67 I/O I/O
P21 I/O I/O P68 I/O I/O
P22 I/O I/O P69 I/O I/O
P23 I/O I/O P70 I/O, SGCK3 I/O, SGCK3
P24 I/O I/O P71 GND GND
P25 I/O I/O P72 DONE DONE
P26 I/O I/O P73 VCC VCC
P27 GND GND P74 PROGRAM PROGRAM
P28 I/O I/O P75 I/O (D7) I/O (D7)
P29 I/O I/O P76 I/O, PGCK3 I/O, PGCK3
P30 I/O I/O P77 I/O I/O
P31 I/O I/O P78 I/O I/O
P32 I/O I/O P79 I/O (D6) I/O (D6)
P33 I/O, SCGK2 I/O, SCGK2 P80 I/O I/O
P34 O (M1) O (M1) P81 GND GND
P35 GND GND P82 I/O I/O
P36 I (M0) I (M0) P83 I/O I/O
P37 VCC VCC P84 I/O (D5) I/O (D5)
P38 I (M2) I (M2) P85 I/O (CS0) I/O (CS0)
P39 I/O, PGCK2 I/O, PGCK2 P86 I/O I/O
P40 I/O (HDC) I/O (HDC) P87 I/O I/O
P41 I/O I/O P88 I/O (D4) I/O (D4)
P42 I/O I/O P89 I/O I/O
P90 VCC VCC

September 18, 1996 (Version 1.04) 4-139

XC4000 Series Field Programmable Gate Arrays

TQ144 Pin XC4005E XC4006E TQ144 Pin XC4005E XC4006E

P91 GND GND P120 I/O I/O
P92 I/O (D3) I/O (D3) P121 I/O (A4) I/O (A4)
P93 I/O (RS) I/O (RS) P122 I/O (A5) I/O (A5)
P94 I/O I/O P123 I/O I/O
P95 I/O I/O P124 I/O I/O
P96 I/O (D2) I/O (D2) P125 I/O (A6) I/O (A6)
P97 I/O I/O P126 I/O (A7) I/O (A7)
P98 I/O I/O P127 GND GND
P99 I/O I/O P128 VCC VCC
P100 GND GND P129 I/O (A8) I/O (A8)
P101 I/O (D1) I/O (D1) P130 I/O (A9) I/O (A9)
P102 I/O (RCLK, I/O (RCLK, P131 I/O I/O
RDY/BUSY) RDY/BUSY) P132 I/O I/O
P103 I/O I/O P133 I/O (A10) I/O (A10)
P104 I/O I/O P134 I/O (A11) I/O (A11)
P105 I/O (D0, DIN) I/O (D0, DIN) P135 I/O I/O
P106 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT) P136 I/O I/O
P107 CCLK CCLK P137 GND GND
P108 VCC VCC P138 I/O (A12) I/O (A12)
P109 O, TDO O, TDO P139 I/O (A13) I/O (A13)
P110 GND GND P140 I/O I/O
P111 I/O (A0, WS) I/O (A0, WS) P141 I/O I/O
P112 I/O, PGCK4 (A1) I/O, PGCK4 (A1) P142 I/O (A14) I/O (A14)
P113 I/O I/O P143 I/O, SGCK1 (A15) I/O, SGCK1 (A15)
P114 I/O I/O P144 VCC VCC
P115 I/O (CS1, A2) I/O (CS1, A2)
2/28/96
P116 I/O (A3) I/O (A3)
P117 N.C. I/O Note: Shaded pins should be taken into account when
P118 GND GND designing PC boards, in case of future replacement by dif-
P119 I/O I/O ferent devices.

4-140 September 18, 1996 (Version 1.04)

PG156 Package Pinouts PG156 Pin XC4005E XC4006E
The following table may contain pinout information for P11 GND GND
unsupported device/package combinations. Please see the P12 I/O I/O
availability charts elsewhere in the XC4000 Series data P13 VCC VCC
sheet for availability information. P14 GND GND
PG156 Pin XC4005E XC4006E P15 I/O I/O
T1 O, TDO O, TDO P16 I/O I/O
T2 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT) N1 I/O (A3) I/O (A3)
T3 I/O (D1) I/O (D1) N2 I/O I/O
T4 I/O I/O N3 GND GND
T5 I/O I/O N14 I/O I/O
T6 I/O I/O N15 I/O I/O
T7 I/O (RS) I/O (RS) N16 N.C. I/O
T8 I/O (D3) I/O (D3) M1 N.C. I/O
T9 I/O I/O M2 N.C. I/O
T10 I/O (D5) I/O (D5) M3 I/O I/O
T11 I/O I/O M14 I/O I/O
T12 N.C. I/O M15 N.C. I/O
T13 I/O I/O M16 I/O I/O
T14 I/O (D6) I/O (D6) L1 I/O I/O
T15 I/O, PGCK3 I/O, PGCK3 L2 I/O I/O
T16 I/O (D7) I/O (D7) L3 GND GND
R1 I/O (A0, WS) I/O (A0, WS) L14 GND GND
R2 CCLK CCLK L15 I/O I/O
R3 I/O I/O L16 I/O I/O
R4 I/O I/O K1 I/O I/O
R5 N.C. I/O K2 I/O (A5) I/O (A5)
R6 I/O I/O K3 I/O (A4) I/O (A4)
R7 I/O I/O K14 I/O I/O
R8 VCC VCC K15 I/O I/O
R9 I/O (D4) I/O (D4) K16 I/O I/O
R10 I/O I/O J1 I/O I/O
R11 I/O I/O J2 I/O (A6) I/O (A6)
R12 N.C. I/O J3 I/O (A7) I/O (A7)
R13 I/O I/O J14 GND GND
R14 PROGRAM PROGRAM J15 I/O I/O
R15 DONE DONE J16 I/O I/O
R16 I/O, SGCK3 I/O, SGCK3 H1 I/O (A8) I/O (A8)
P1 I/O (CS1, A2) I/O (CS1, A2) H2 GND GND
P2 I/O, PGCK4 (A1) I/O, PGCK4 (A1) H3 VCC VCC
P3 VCC VCC H14 VCC VCC
P4 I/O (D0, DIN) I/O (D0, DIN) H15 I/O (INIT) I/O (INIT)
P5 I/O (RCLK, I/O (RCLK, H16 I/O I/O
RDY/BUSY) RDY/BUSY) G1 I/O (A9) I/O (A9)
P6 GND GND G2 I/O I/O
P7 I/O (D2) I/O (D2) G3 I/O I/O
P8 GND GND G14 I/O I/O
P9 I/O I/O G15 I/O I/O
P10 I/O (CS0) I/O (CS0) G16 I/O I/O

September 18, 1996 (Version 1.04) 4-141

XC4000 Series Field Programmable Gate Arrays

PG156 Pin XC4005E XC4006E PG156 Pin XC4005E XC4006E

F1 I/O (A10) I/O (A10) B5 I/O I/O
F2 I/O (A11) I/O (A11) B6 I/O I/O
F3 GND GND B7 I/O I/O
F14 GND GND B8 VCC VCC
F15 I/O I/O B9 I/O I/O
F16 I/O I/O B10 I/O I/O
E1 I/O I/O B11 I/O I/O
E2 I/O I/O B12 I/O I/O
E3 I/O (A12) I/O (A12) B13 I/O I/O
E14 I/O I/O B14 I/O, SCGK2 I/O, SCGK2
E15 N.C. I/O B15 I (M2) I (M2)
E16 I/O I/O B16 I/O, PGCK2 I/O, PGCK2
D1 N.C. I/O A1 I/O (A17) I/O (A17)
D2 N.C. I/O A2 I/O I/O
D3 I/O I/O A3 I/O, TCK I/O, TCK
D14 I/O (HDC) I/O (HDC) A4 N.C. I/O
D15 I/O I/O A5 I/O, TMS I/O, TMS
D16 N.C. I/O A6 I/O I/O
C1 I/O (A13) I/O (A13) A7 I/O I/O
C2 I/O I/O A8 I/O I/O
C3 VCC VCC A9 I/O I/O
C4 GND GND A10 I/O I/O
C5 I/O I/O A11 I/O I/O
C6 GND GND A12 N.C. I/O
C7 I/O I/O A13 I/O I/O
C8 GND GND A14 I/O I/O
C9 I/O I/O A15 O (M1) O (M1)
C10 I/O I/O A16 I (M0) I (M0)
C11 GND GND 2/28/96
C12 I/O I/O
C13 GND GND Note: Shaded pins should be taken into account when
C14 VCC VCC designing PC boards, in case of future replacement by dif-
C15 I/O I/O ferent devices.
C16 I/O (LDC) I/O (LDC) Note: Viewed from the bottom side, the package pins start
B1 I/O (A14) I/O (A14) at the top row and go from the left edge to the right edge.
B2 I/O, SGCK1 (A15) I/O, SGCK1 (A15) Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.
B3 I/O, PGCK1 (A16) I/O, PGCK1 (A16)
B4 I/O, TDI I/O, TDI

4-142 September 18, 1996 (Version 1.04)

PQ160 Package Pinouts PQ
160 XC4005E XC4006E XC4008E XC4010E XC4013E
The following table may contain pinout information for Pin
unsupported device/package combinations. Please see the P43 I/O, I/O, I/O, I/O, I/O,
availability charts elsewhere in the XC4000 Series data PGCK2 PGCK2 PGCK2 PGCK2 PGCK2
sheet for availability information. P44 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
P45 I/O I/O I/O I/O I/O
PQ
160 XC4005E XC4006E XC4008E XC4010E XC4013E P46 I/O I/O I/O I/O I/O
Pin P47 I/O I/O I/O I/O I/O
P1 GND GND GND GND GND P48 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC)
P2 I/O, I/O, I/O, I/O, I/O, P49 N.C. I/O I/O I/O I/O
PGCK1 PGCK1 PGCK1 PGCK1 PGCK1 P50 N.C. I/O I/O I/O I/O
(A16) (A16) (A16) (A16) (A16)
P51 GND GND GND GND GND
P3 I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O (A17)
P52 I/O I/O I/O I/O I/O
P4 I/O I/O I/O I/O I/O
P53 I/O I/O I/O I/O I/O
P5 I/O I/O I/O I/O I/O
P54 I/O I/O I/O I/O I/O
P6 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI
P55 I/O I/O I/O I/O I/O
P7 I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TCK
P56 I/O I/O I/O I/O I/O
P8 N.C. I/O I/O I/O I/O
P57 I/O I/O I/O I/O I/O
P9 N.C. I/O I/O I/O I/O
P58 I/O I/O I/O I/O I/O
P10 GND GND GND GND GND
P59 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT)
P11 I/O I/O I/O I/O I/O
P60 VCC VCC VCC VCC VCC
P12 I/O I/O I/O I/O I/O
P61 GND GND GND GND GND
P13 I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O, TMS
P62 I/O I/O I/O I/O I/O
P14 I/O I/O I/O I/O I/O
P63 I/O I/O I/O I/O I/O
P15 I/O I/O I/O I/O I/O
P64 I/O I/O I/O I/O I/O
P16 I/O I/O I/O I/O I/O
P65 I/O I/O I/O I/O I/O
P17 I/O I/O I/O I/O I/O
P66 I/O I/O I/O I/O I/O
P18 I/O I/O I/O I/O I/O
P67 I/O I/O I/O I/O I/O
P19 GND GND GND GND GND
P68 I/O I/O I/O I/O I/O
P20 VCC VCC VCC VCC VCC
P69 I/O I/O I/O I/O I/O
P21 I/O I/O I/O I/O I/O
P70 GND GND GND GND GND
P22 I/O I/O I/O I/O I/O
P71 N.C. I/O I/O I/O I/O
P23 I/O I/O I/O I/O I/O
P72 N.C. I/O I/O I/O I/O
P24 I/O I/O I/O I/O I/O
P73 I/O I/O I/O I/O I/O
P25 I/O I/O I/O I/O I/O
P74 I/O I/O I/O I/O I/O
P26 I/O I/O I/O I/O I/O
P75 I/O I/O I/O I/O I/O
P27 I/O I/O I/O I/O I/O
P76 I/O I/O I/O I/O I/O
P28 I/O I/O I/O I/O I/O
P77 I/O I/O I/O I/O I/O
P29 GND GND GND GND GND
P78 I/O, I/O, I/O, I/O, I/O,
P30 N.C. I/O I/O I/O I/O SGCK3 SGCK3 SGCK3 SGCK3 SGCK3
P31 N.C. I/O I/O I/O I/O P79 GND GND GND GND GND
P32 I/O I/O I/O I/O I/O P80 DONE DONE DONE DONE DONE
P33 I/O I/O I/O I/O I/O P81 VCC VCC VCC VCC VCC
P34 I/O I/O I/O I/O I/O P82 PRO- PRO- PRO- PRO- PRO-
P35 I/O I/O I/O I/O I/O GRAM GRAM GRAM GRAM GRAM
P36 I/O I/O I/O I/O I/O P83 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7)
P37 I/O, I/O, I/O, I/O, I/O, P84 I/O, I/O, I/O, I/O, I/O,
SCGK2 SCGK2 SCGK2 SCGK2 SCGK2 PGCK3 PGCK3 PGCK3 PGCK3 PGCK3
P38 O (M1) O (M1) O (M1) O (M1) O (M1) P85 I/O I/O I/O I/O I/O
P39 GND GND GND GND GND P86 I/O I/O I/O I/O I/O
P40 I (M0) I (M0) I (M0) I (M0) I (M0) P87 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6)
P41 VCC VCC VCC VCC VCC P88 I/O I/O I/O I/O I/O
P42 I (M2) I (M2) I (M2) I (M2) I (M2) P89 N.C. I/O I/O I/O I/O
P90 N.C. I/O I/O I/O I/O

September 18, 1996 (Version 1.04) 4-143

XC4000 Series Field Programmable Gate Arrays

PQ PQ
160 XC4005E XC4006E XC4008E XC4010E XC4013E 160 XC4005E XC4006E XC4008E XC4010E XC4013E
Pin Pin
P91 GND GND GND GND GND P127 I/O I/O I/O I/O I/O
P92 I/O I/O I/O I/O I/O (CS1, A2) (CS1, A2) (CS1, A2) (CS1, A2) (CS1, A2)
P93 I/O I/O I/O I/O I/O P128 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3)
P94 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) P129 N.C. I/O I/O I/O I/O
P95 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) P130 N.C. I/O I/O I/O I/O
P96 I/O I/O I/O I/O I/O P131 GND GND GND GND GND
P97 I/O I/O I/O I/O I/O P132 I/O I/O I/O I/O I/O
P98 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) P133 I/O I/O I/O I/O I/O
P99 I/O I/O I/O I/O I/O P134 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4)
P100 VCC VCC VCC VCC VCC P135 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5)
P101 GND GND GND GND GND P136 N.C. N.C. I/O I/O I/O
P102 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) P137 I/O I/O I/O I/O I/O
P103 I/O (RS) I/O (RS) I/O (RS) I/O (RS) I/O (RS) P138 I/O I/O I/O I/O I/O
P104 I/O I/O I/O I/O I/O P139 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6)
P105 I/O I/O I/O I/O I/O P140 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7)
P106 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) P141 GND GND GND GND GND
P107 I/O I/O I/O I/O I/O P142 VCC VCC VCC VCC VCC
P108 I/O I/O I/O I/O I/O P143 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8)
P109 I/O I/O I/O I/O I/O P144 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9)
P110 GND GND GND GND GND P145 I/O I/O I/O I/O I/O
P111 N.C. I/O I/O I/O I/O P146 I/O I/O I/O I/O I/O
P112 N.C. I/O I/O I/O I/O P147 I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A10)
P113 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) P148 I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A11)
P114 I/O (RCLK, I/O (RCLK, I/O (RCLK, I/O (RCLK, I/O (RCLK, P149 I/O I/O I/O I/O I/O
RDY/ RDY/ RDY/ RDY/ RDY/ P150 I/O I/O I/O I/O I/O
BUSY) BUSY) BUSY) BUSY) BUSY) P151 GND GND GND GND GND
P115 I/O I/O I/O I/O I/O P152 N.C. I/O I/O I/O I/O
P116 I/O I/O I/O I/O I/O P153 N.C. I/O I/O I/O I/O
P117 I/O I/O I/O I/O I/O P154 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12)
(D0, DIN) (D0, DIN) (D0, DIN) (D0, DIN) (D0, DIN)
P155 I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A13)
P118 I/O, I/O, I/O, I/O, I/O,
SGCK4 SGCK4 SGCK4 SGCK4 SGCK4 P156 I/O I/O I/O I/O I/O
(DOUT) (DOUT) (DOUT) (DOUT) (DOUT) P157 I/O I/O I/O I/O I/O
P119 CCLK CCLK CCLK CCLK CCLK P158 I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14)
P120 VCC VCC VCC VCC VCC P159 I/O, I/O, I/O, I/O, I/O,
P121 O, TDO O, TDO O, TDO O, TDO O, TDO SGCK1 SGCK1 SGCK1 SGCK1 SGCK1
(A15) (A15) (A15) (A15) (A15)
P122 GND GND GND GND GND
P160 VCC VCC VCC VCC VCC
P123 I/O I/O I/O I/O I/O
(A0, WS) (A0, WS) (A0, WS) (A0, WS) (A0, WS) 2/28/96
P124 I/O, I/O, I/O, I/O, I/O,
PGCK4 PGCK4 PGCK4 PGCK4 PGCK4 Note: Shaded pins should be taken into account when
(A1) (A1) (A1) (A1) (A1)
designing PC boards, in case of future replacement by dif-
P125 I/O I/O I/O I/O I/O
ferent devices.
P126 I/O I/O I/O I/O I/O

4-144 September 18, 1996 (Version 1.04)

TQ176 Package Pinouts TQ176 Pin XC4010L
The following table may contain pinout information for P43 GND
unsupported device/package combinations. Please see the P44 I (M0)
availability charts elsewhere in the XC4000 Series data P45 VCC
sheet for availability information. P46 I (M2)
TQ176 Pin XC4010L P47 I/O, PGCK2
P1 GND P48 I/O (HDC)
P2 I/O, PGCK1 (A16) P49 I/O
P3 I/O (A17) P50 I/O
P4 I/O P51 I/O
P5 I/O P52 I/O (LDC)
P6 I/O, TDI P53 I/O
P7 I/O, TCK P54 I/O
P8 I/O P55 GND
P9 I/O P56 I/O
P10 GND P57 I/O
P11 I/O P58 I/O
P12 I/O P59 I/O
P13 I/O, TMS P60 I/O
P14 I/O P61 I/O
P15 I/O P62 I/O
P16 I/O P63 I/O
P17 I/O P64 I/O
P18 I/O P65 I/O (INIT)
P19 I/O P66 VCC
P20 I/O P67 GND
P21 GND P68 I/O
P22 VCC P69 I/O
P23 I/O P70 I/O
P24 I/O P71 I/O
P25 I/O P72 I/O
P26 I/O P73 I/O
P27 I/O P74 I/O
P28 I/O P75 I/O
P29 I/O P76 I/O
P30 I/O P77 I/O
P31 I/O P78 GND
P32 I/O P79 I/O
P33 GND P80 I/O
P34 I/O P81 I/O
P35 I/O P82 I/O
P36 I/O P83 I/O
P37 I/O P84 I/O
P38 I/O P85 I/O
P39 I/O P86 I/O, SGCK3
P40 I/O P87 GND
P41 I/O, SCGK2 P88 DONE
P42 O (M1) P89 VCC
P90 PROGRAM

September 18, 1996 (Version 1.04) 4-145

XC4000 Series Field Programmable Gate Arrays

TQ176 Pin XC4010L TQ176 Pin XC4010L

P91 I/O (D7) P139 I/O (CS1, A2)
P92 I/O, PGCK3 P140 I/O (A3)
P93 I/O P141 I/O
P94 I/O P142 I/O
P95 I/O (D6) P143 GND
P96 I/O P144 I/O
P97 I/O P145 I/O
P98 I/O P146 I/O (A4)
P99 GND P147 I/O (A5)
P100 I/O P148 I/O
P101 I/O P149 I/O
P102 I/O (D5) P150 I/O
P103 I/O (CS0) P151 I/O
P104 I/O P152 I/O (A6)
P105 I/O P153 I/O (A7)
P106 I/O P154 GND
P107 I/O P155 VCC
P108 I/O (D4) P156 I/O (A8)
P109 I/O P157 I/O (A9)
P110 VCC P158 I/O
P111 GND P159 I/O
P112 I/O (D3) P160 I/O
P113 I/O (RS) P161 I/O
P114 I/O P162 I/O (A10)
P115 I/O P163 I/O (A11)
P116 I/O P164 I/O
P117 I/O P165 I/O
P118 I/O (D2) P166 GND
P119 I/O P167 I/O
P120 I/O P168 I/O
P121 I/O P169 I/O
P122 GND P170 I/O (A12)
P123 I/O P171 I/O (A13)
P124 I/O P172 I/O
P125 I/O (D1) P173 I/O
P126 I/O (RCLK, RDY/BUSY) P174 I/O (A14)
P127 I/O P175 I/O, SGCK1 (A15)
P128 I/O P176 VCC
P129 I/O (D0, DIN) 3/15/96
P130 I/O, SGCK4 (DOUT)
P131 CCLK
P132 VCC
P133 O, TDO PG191 Package Pinouts (see PG223)
P134 GND
The PG191 package pinout has been combined with the
P135 I/O (A0, WS) PG223 in a single table, because of their physical compat-
P136 I/O, PGCK4 (A1) ibility. The PG191 has the same dimensions as the PG223,
P137 I/O but has 32 fewer pins on the inner ring.
P138 I/O

4-146 September 18, 1996 (Version 1.04)

PQ208, HQ208 Package Pinouts PQ XC XC XC XC XC XC XC
208 4005 4006 4008 4010 4013 4020 4028
The following table may contain pinout information for Pin E/L E E E/L E/L E EX/XL
unsupported device/package combinations. Please see the P41 N.C. I/O I/O I/O I/O I/O I/O
availability charts elsewhere in the XC4000 Series data P42 I/O I/O I/O I/O I/O I/O I/O
sheet for availability information. P43 I/O I/O I/O I/O I/O I/O I/O
PQ XC XC XC XC XC XC XC P44 I/O I/O I/O I/O I/O I/O I/O
208 4005 4006 4008 4010 4013 4020 4028 P45 I/O I/O I/O I/O I/O I/O I/O
Pin E/L E E E/L E/L E EX/XL P46 I/O I/O I/O I/O I/O I/O I/O
P1 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P47 I/O, I/O, I/O, I/O, I/O, I/O, I/O,
P2 GND GND GND GND GND GND GND SGCK2 SGCK2 SGCK2 SGCK2 SGCK2 SGCK2 GCK2
P3 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P48 O (M1) O (M1) O (M1) O (M1) O (M1) O (M1) O (M1)
P4 I/O, I/O, I/O, I/O, I/O, I/O, I/O, P49 GND GND GND GND GND GND GND
PGCK1 PGCK1 PGCK1 PGCK1 PGCK1 PGCK1 GCK1 P50 I (M0) I (M0) I (M0) I (M0) I (M0) I (M0) I (M0)
(A16) (A16) (A16) (A16) (A16) (A16) (A16)
P51 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P5 I/O I/O I/O I/O I/O I/O I/O
(A17) (A17) (A17) (A17) (A17) (A17) (A17) P52 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P6 I/O I/O I/O I/O I/O I/O I/O P53 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P7 I/O I/O I/O I/O I/O I/O I/O P54 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P8 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI P55 VCC VCC VCC VCC VCC VCC VCC
P9 I/O, I/O, I/O, I/O, I/O, I/O, I/O, P56 I (M2) I (M2) I (M2) I (M2) I (M2) I (M2) I (M2)
TCK TCK TCK TCK TCK TCK TCK P57 I/O, I/O, I/O, I/O, I/O, I/O, I/O,
P10 N.C. I/O I/O I/O I/O I/O I/O PGCK2 PGCK2 PGCK2 PGCK2 PGCK2 PGCK2 GCK3
P11 N.C. I/O I/O I/O I/O I/O I/O P58 I/O I/O I/O I/O I/O I/O I/O
(HDC) (HDC) (HDC) (HDC) (HDC) (HDC) (HDC)
P12 N.C. N.C. N.C. I/O I/O I/O I/O
P59 I/O I/O I/O I/O I/O I/O I/O
P13 N.C. N.C. N.C. I/O I/O I/O I/O
P60 I/O I/O I/O I/O I/O I/O I/O
P14 GND GND GND GND GND GND GND
P61 I/O I/O I/O I/O I/O I/O I/O
P15 I/O I/O I/O I/O I/O I/O I/O,
FCLK1 P62 I/O I/O I/O I/O I/O I/O I/O
(LDC) (LDC) (LDC) (LDC) (LDC) (LDC) (LDC)
P16 I/O I/O I/O I/O I/O I/O I/O
P63 N.C. I/O I/O I/O I/O I/O I/O
P17 I/O, I/O, I/O, I/O, I/O, I/O, I/O,
TMS TMS TMS TMS TMS TMS TMS P64 N.C. I/O I/O I/O I/O I/O I/O
P18 I/O I/O I/O I/O I/O I/O I/O P65 N.C. N.C. N.C. I/O I/O I/O I/O
P19 N.C. N.C. I/O I/O I/O I/O I/O P66 N.C. N.C. N.C. I/O I/O I/O I/O
P20 N.C. N.C. I/O I/O I/O I/O I/O P67 GND GND GND GND GND GND GND
P21 I/O I/O I/O I/O I/O I/O I/O P68 I/O I/O I/O I/O I/O I/O I/O
P22 I/O I/O I/O I/O I/O I/O I/O P69 I/O I/O I/O I/O I/O I/O I/O
P23 I/O I/O I/O I/O I/O I/O I/O P70 I/O I/O I/O I/O I/O I/O I/O
P24 I/O I/O I/O I/O I/O I/O I/O P71 I/O I/O I/O I/O I/O I/O I/O
P25 GND GND GND GND GND GND GND P72 N.C. N.C. I/O I/O I/O I/O I/O
P26 VCC VCC VCC VCC VCC VCC VCC P73 N.C. N.C. I/O I/O I/O I/O I/O
P27 I/O I/O I/O I/O I/O I/O I/O P74 I/O I/O I/O I/O I/O I/O I/O
P28 I/O I/O I/O I/O I/O I/O I/O P75 I/O I/O I/O I/O I/O I/O I/O
P29 I/O I/O I/O I/O I/O I/O I/O P76 I/O I/O I/O I/O I/O I/O I/O
P30 I/O I/O I/O I/O I/O I/O I/O P77 I/O I/O I/O I/O I/O I/O I/O
(INIT) (INIT) (INIT) (INIT) (INIT) (INIT) (INIT)
P31 N.C. N.C. I/O I/O I/O I/O I/O
P78 VCC VCC VCC VCC VCC VCC VCC
P32 N.C. N.C. I/O I/O I/O I/O I/O
P79 GND GND GND GND GND GND GND
P33 I/O I/O I/O I/O I/O I/O I/O
P80 I/O I/O I/O I/O I/O I/O I/O
P34 I/O I/O I/O I/O I/O I/O I/O
P81 I/O I/O I/O I/O I/O I/O I/O
P35 I/O I/O I/O I/O I/O I/O I/O
P82 I/O I/O I/O I/O I/O I/O I/O
P36 I/O I/O I/O I/O I/O I/O I/O,
FCLK2 P83 I/O I/O I/O I/O I/O I/O I/O
P37 GND GND GND GND GND GND GND P84 N.C. N.C. I/O I/O I/O I/O I/O
P38 N.C. N.C. N.C. I/O I/O I/O I/O P85 N.C. N.C. I/O I/O I/O I/O I/O
P39 N.C. N.C. N.C. I/O I/O I/O I/O P86 I/O I/O I/O I/O I/O I/O I/O
P40 N.C. I/O I/O I/O I/O I/O I/O P87 I/O I/O I/O I/O I/O I/O I/O

September 18, 1996 (Version 1.04) 4-147

XC4000 Series Field Programmable Gate Arrays

PQ XC XC XC XC XC XC XC PQ XC XC XC XC XC XC XC
208 4005 4006 4008 4010 4013 4020 4028 208 4005 4006 4008 4010 4013 4020 4028
Pin E/L E E E/L E/L E EX/XL Pin E/L E E E/L E/L E EX/XL
P88 I/O I/O I/O I/O I/O I/O I/O P134 I/O I/O I/O I/O I/O I/O I/O
P89 I/O I/O I/O I/O I/O I/O I/O P135 I/O I/O I/O I/O I/O I/O I/O
P90 GND GND GND GND GND GND GND P136 N.C. N.C. I/O I/O I/O I/O I/O
P91 N.C. N.C. N.C. I/O I/O I/O I/O P137 N.C. N.C. I/O I/O I/O I/O I/O
P92 N.C. N.C. N.C. I/O I/O I/O I/O P138 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2)
P93 N.C. I/O I/O I/O I/O I/O I/O P139 I/O I/O I/O I/O I/O I/O I/O
P94 N.C. I/O I/O I/O I/O I/O I/O P140 I/O I/O I/O I/O I/O I/O I/O
P95 I/O I/O I/O I/O I/O I/O I/O P141 I/O I/O I/O I/O I/O I/O I/O,
P96 I/O I/O I/O I/O I/O I/O I/O FCLK4
P97 I/O I/O I/O I/O I/O I/O I/O P142 GND GND GND GND GND GND GND
P98 I/O I/O I/O I/O I/O I/O I/O P143 N.C. N.C. N.C. I/O I/O I/O I/O
P99 I/O I/O I/O I/O I/O I/O I/O P144 N.C. N.C. N.C. I/O I/O I/O I/O
P100 I/O, I/O, I/O, I/O, I/O, I/O, I/O, P145 N.C. I/O I/O I/O I/O I/O I/O
SGCK3 SGCK3 SGCK3 SGCK3 SGCK3 SGCK3 GCK4 P146 N.C. I/O I/O I/O I/O I/O I/O
P101 GND GND GND GND GND GND GND P147 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1)
P102 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P148 I/O I/O I/O I/O I/O I/O I/O
P103 DONE DONE DONE DONE DONE DONE DONE (RCLK, (RCLK, (RCLK, (RCLK, (RCLK, (RCLK, (RCLK,
RDY/ RDY/ RDY/ RDY/ RDY/ RDY/ RDY/
P104 N.C. N.C. N.C. N.C. N.C. N.C. N.C. BUSY) BUSY) BUSY) BUSY) BUSY) BUSY) BUSY)
P105 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P149 I/O I/O I/O I/O I/O I/O I/O
P106 VCC VCC VCC VCC VCC VCC VCC P150 I/O I/O I/O I/O I/O I/O I/O
P107 N.C. N.C. N.C. N.C. N.C. N.C. N.C. P151 I/O I/O I/O I/O I/O I/O I/O
P108 PRO- PRO- PRO- PRO- PRO- PRO- PRO- (D0, (D0, (D0, (D0, (D0, (D0, (D0,
GRAM GRAM GRAM GRAM GRAM GRAM GRAM DIN) DIN) DIN) DIN) DIN) DIN) DIN)
P109 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7) P152 I/O, I/O, I/O, I/O, I/O, I/O, I/O,
P110 I/O, I/O, I/O, I/O, I/O, I/O, I/O, SGCK SGCK4 SGCK4 SGCK4 SGCK4 SGCK4 GCK6
PGCK3 PGCK3 PGCK3 PGCK3 PGCK3 PGCK3 GCK5 (DOUT) (DOUT) (DOUT) (DOUT) (DOUT) (DOUT) (DOUT)
P111 I/O I/O I/O I/O I/O I/O I/O P153 CCLK CCLK CCLK CCLK CCLK CCLK CCLK
P112 I/O I/O I/O I/O I/O I/O I/O P154 VCC VCC VCC VCC VCC VCC VCC
P113 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6) P155 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P114 I/O I/O I/O I/O I/O I/O I/O P156 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P115 N.C. I/O I/O I/O I/O I/O I/O P157 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P116 N.C. I/O I/O I/O I/O I/O I/O P158 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P117 N.C. N.C. N.C. I/O I/O I/O I/O P159 O, TDO O, TDO O, TDO O, TDO O, TDO O, TDO O, TDO
P118 N.C. N.C. N.C. I/O I/O I/O I/O P160 GND GND GND GND GND GND GND
P119 GND GND GND GND GND GND GND P161 I/O I/O I/O I/O I/O I/O I/O
(A0, (A0, (A0, (A0, (A0, (A0, (A0,
P120 I/O I/O I/O I/O I/O I/O I/O,
WS) WS) WS) WS) WS) WS) WS)
FCLK3
P162 I/O, I/O, I/O, I/O, I/O, I/O, I/O,
P121 I/O I/O I/O I/O I/O I/O I/O PGCK4 PGCK4 PGCK4 PGCK4 PGCK4 PGCK4 GCK7
P122 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5) (A1) (A1) (A1) (A1) (A1) (A1) (A1)
P123 I/O I/O I/O I/O I/O I/O I/O P163 I/O I/O I/O I/O I/O I/O I/O
(CS0) (CS0) (CS0) (CS0) (CS0) (CS0) (CS0) P164 I/O I/O I/O I/O I/O I/O I/O
P124 N.C. N.C. I/O I/O I/O I/O I/O
P165 I/O I/O I/O I/O I/O I/O I/O
P125 N.C. N.C. I/O I/O I/O I/O I/O (CS1, (CS1, (CS1, (CS1, (CS1, (CS1, (CS1,
P126 I/O I/O I/O I/O I/O I/O I/O A2) A2) A2) A2) A2) A2) A2)
P127 I/O I/O I/O I/O I/O I/O I/O P166 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3)
P128 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4) P167 N.C. I/O I/O I/O I/O I/O I/O
P129 I/O I/O I/O I/O I/O I/O I/O P168 N.C. I/O I/O I/O I/O I/O I/O
P130 VCC VCC VCC VCC VCC VCC VCC P169 N.C. N.C. N.C. I/O I/O I/O I/O
P131 GND GND GND GND GND GND GND P170 N.C. N.C. N.C. I/O I/O I/O I/O
P132 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3) P171 GND GND GND GND GND GND GND
P133 I/O I/O I/O I/O I/O I/O I/O P172 I/O I/O I/O I/O I/O I/O I/O
(RS) (RS) (RS) (RS) (RS) (RS) (RS) P173 I/O I/O I/O I/O I/O I/O I/O

4-148 September 18, 1996 (Version 1.04)

PQ XC XC XC XC XC XC XC PQ XC XC XC XC XC XC XC
208 4005 4006 4008 4010 4013 4020 4028 208 4005 4006 4008 4010 4013 4020 4028
Pin E/L E E E/L E/L E EX/XL Pin E/L E E E/L E/L E EX/XL
P174 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) P194 GND GND GND GND GND GND GND
P175 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) P195 N.C. N.C. N.C. I/O I/O I/O I/O
P176 N.C. N.C. I/O I/O I/O I/O I/O P196 N.C. N.C. N.C. I/O I/O I/O I/O
P177 N.C. N.C. I/O I/O I/O I/O I/O P197 N.C. I/O I/O I/O I/O I/O I/O
P178 I/O I/O I/O I/O I/O I/O I/O P198 N.C. I/O I/O I/O I/O I/O I/O
(A21) P199 I/O I/O I/O I/O I/O I/O I/O
P179 I/O I/O I/O I/O I/O I/O I/O (A12) (A12) (A12) (A12) (A12) (A12) (A12)
(A20) P200 I/O I/O I/O I/O I/O I/O I/O
P180 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6) (A13) (A13) (A13) (A13) (A13) (A13) (A13)
P181 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7) P201 I/O I/O I/O I/O I/O I/O I/O
P182 GND GND GND GND GND GND GND P202 I/O I/O I/O I/O I/O I/O I/O
P183 VCC VCC VCC VCC VCC VCC VCC P203 I/O I/O I/O I/O I/O I/O I/O
P184 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) (A14) (A14) (A14) (A14) (A14) (A14) (A14)
P185 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) P204 I/O, I/O, I/O, I/O, I/O, I/O, I/O,
SGCK1 SGCK1 SGCK1 SGCK1 SGCK1 SGCK1 GCK8
P186 I/O I/O I/O I/O I/O I/O I/O (A15) (A15) (A15) (A15) (A15) (A15) (A15)
(A19)
P205 VCC VCC VCC VCC VCC VCC VCC
P187 I/O I/O I/O I/O I/O I/O I/O
(A18) P206 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P188 N.C. N.C. I/O I/O I/O I/O I/O P207 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P189 N.C. N.C. I/O I/O I/O I/O I/O P208 N.C. N.C. N.C. N.C. N.C. N.C. N.C.
P190 I/O I/O I/O I/O I/O I/O I/O 3/13/96
(A10) (A10) (A10) (A10) (A10) (A10) (A10)
P191 I/O I/O I/O I/O I/O I/O I/O Note: Shaded pins should be taken into account when de-
(A11) (A11) (A11) (A11) (A11) (A11) (A11) signing PC boards, in case of future replacement by differ-
P192 I/O I/O I/O I/O I/O I/O I/O ent devices.
P193 I/O I/O I/O I/O I/O I/O I/O

September 18, 1996 (Version 1.04) 4-149

XC4000 Series Field Programmable Gate Arrays

PG223 and PG191 Package Pinouts PG PG

XC4008E XC4010E XC4013E XC4020E XC4025E
223 191
These two packages have been combined into a single PG191 PG191 PG223 PG223 PG223
Pin Pin
table because of their physical compatibility. The PG191 U18 U18 I/O I/O I/O I/O I/O
has the same dimensions as the PG223, but has 32 fewer T1 T1 I/O I/O I/O I/O I/O
pins on the inner ring. T2 T2 I/O I/O I/O I/O I/O
The following table may contain pinout information for (CS1,A2) (CS1,A2) (CS1,A2) (CS1,A2) (CS1,A2)
unsupported device/package combinations. Please see the T3 T3 I/O I/O I/O I/O I/O
(A0, WS) (A0, WS) (A0, WS) (A0, WS) (A0, WS)
availability charts elsewhere in the XC4000 Series data
T4 T4 I/O, I/O, I/O, I/O, I/O,
sheet for availability information.
SGCK4 SGCK4 SGCK4 SGCK4 SGCK4
PG PG (DOUT) (DOUT) (DOUT) (DOUT) (DOUT)
XC4008E XC4010E XC4013E XC4020E XC4025E T5 T5 I/O I/O I/O I/O I/O
223 191
PG191 PG191 PG223 PG223 PG223
Pin Pin T6 T6 I/O I/O I/O I/O I/O
V1 V1 CCLK CCLK CCLK CCLK CCLK T7 T7 GND GND GND GND GND
V2 V2 I/O I/O I/O I/O I/O T8 T8 I/O I/O I/O I/O I/O
(RCLK, (RCLK, (RCLK, (RCLK, (RCLK,
T9 T9 I/O (D3) I/O (D3) I/O (D3) I/O (D3) I/O (D3)
RDY/ RDY/ RDY/ RDY/ RDY/
BUSY) BUSY) BUSY) BUSY) BUSY) T10 T10 I/O I/O I/O I/O I/O
V3 V3 I/O (D1) I/O (D1) I/O (D1) I/O (D1) I/O (D1) T11 T11 I/O I/O I/O I/O I/O
V4 V4 N.C. I/O I/O I/O I/O T12 T12 GND GND GND GND GND
V5 V5 N.C. I/O I/O I/O I/O T13 T13 I/O I/O I/O I/O I/O
V6 V6 I/O I/O I/O I/O I/O T14 T14 I/O I/O I/O I/O I/O
V7 V7 I/O (D2) I/O (D2) I/O (D2) I/O (D2) I/O (D2) T15 T15 I/O (D7) I/O (D7) I/O (D7) I/O (D7) I/O (D7)
V8 V8 I/O I/O I/O I/O I/O T16 T16 I/O, I/O, I/O, I/O, I/O,
SGCK3 SGCK3 SGCK3 SGCK3 SGCK3
V9 V9 I/O I/O I/O I/O I/O
T17 T17 I/O I/O I/O I/O I/O
V10 V10 I/O I/O I/O I/O I/O
T18 T18 I/O I/O I/O I/O I/O
V11 V11 I/O I/O I/O I/O I/O
R1 R1 N.C. I/O I/O I/O I/O
V12 V12 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0)
R2 R2 I/O I/O I/O I/O I/O
V13 V13 I/O I/O I/O I/O I/O
R3 R3 GND GND GND GND GND
V14 V14 N.C. I/O I/O I/O I/O
R4 R4 VCC VCC VCC VCC VCC
V15 V15 N.C. I/O I/O I/O I/O
R5 I/O I/O I/O
V16 V16 I/O I/O I/O I/O I/O
R6 I/O I/O I/O
V17 V17 I/O (D6) I/O (D6) I/O (D6) I/O (D6) I/O (D6)
R7 I/O I/O I/O
V18 V18 PRO- PRO- PRO- PRO- PRO-
GRAM GRAM GRAM GRAM GRAM R8 I/O I/O I/O
U1 U1 I/O, I/O, I/O, I/O, I/O, R9 R9 GND GND GND GND GND
PGCK4 PGCK4 PGCK4 PGCK4 PGCK4 R10 R10 VCC VCC VCC VCC VCC
(A1) (A1) (A1) (A1) (A1) R11 I/O I/O I/O
U2 U2 O, TDO O, TDO O, TDO O, TDO O, TDO R12 I/O I/O I/O
U3 U3 I/O I/O I/O I/O I/O R13 I/O I/O I/O
(D0, DIN) (D0, DIN) (D0, DIN) (D0, DIN) (D0, DIN)
R14 I/O I/O I/O
U4 U4 I/O I/O I/O I/O I/O
R15 R15 VCC VCC VCC VCC VCC
U5 U5 I/O I/O I/O I/O I/O
R16 R16 GND GND GND GND GND
U6 U6 I/O I/O I/O I/O I/O
R17 R17 I/O I/O I/O I/O I/O
U7 U7 I/O I/O I/O I/O I/O
R18 R18 N.C. I/O I/O I/O I/O
U8 U8 I/O I/O I/O I/O I/O
P1 P1 I/O I/O I/O I/O I/O
U9 U9 I/O (RS) I/O (RS) I/O (RS) I/O (RS) I/O (RS)
P2 P2 I/O I/O I/O I/O I/O
U10 U10 I/O (D4) I/O (D4) I/O (D4) I/O (D4) I/O (D4)
P3 P3 I/O I/O I/O I/O I/O
U11 U11 I/O I/O I/O I/O I/O
P4 I/O I/O I/O
U12 U12 I/O (D5) I/O (D5) I/O (D5) I/O (D5) I/O (D5)
P15 I/O I/O I/O
U13 U13 I/O I/O I/O I/O I/O
P16 P16 I/O I/O I/O I/O I/O
U14 U14 I/O I/O I/O I/O I/O
P17 P17 I/O I/O I/O I/O I/O
U15 U15 I/O I/O I/O I/O I/O
P18 P18 I/O I/O I/O I/O I/O
U16 U16 I/O, I/O, I/O, I/O, I/O,
PGCK3 PGCK3 PGCK3 PGCK3 PGCK3 N1 N1 I/O I/O I/O I/O I/O
U17 U17 DONE DONE DONE DONE DONE N2 N2 N.C. I/O I/O I/O I/O

4-150 September 18, 1996 (Version 1.04)

PG PG PG PG
XC4008E XC4010E XC4013E XC4020E XC4025E XC4008E XC4010E XC4013E XC4020E XC4025E
223 191 223 191
PG191 PG191 PG223 PG223 PG223 PG191 PG191 PG223 PG223 PG223
Pin Pin Pin Pin
N3 N3 I/O (A3) I/O (A3) I/O (A3) I/O (A3) I/O (A3) G16 G16 GND GND GND GND GND
N4 I/O I/O I/O G17 G17 I/O I/O I/O I/O I/O
N15 I/O I/O I/O G18 G18 I/O I/O I/O I/O I/O
N16 N16 I/O I/O I/O I/O I/O F1 F1 I/O I/O I/O I/O I/O
N17 N17 N.C. I/O I/O I/O I/O F2 F2 N.C. I/O I/O I/O I/O
N18 N18 I/O I/O I/O I/O I/O F3 F3 I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12)
M1 M1 I/O (A5) I/O (A5) I/O (A5) I/O (A5) I/O (A5) F4 I/O I/O I/O
M2 M2 I/O (A4) I/O (A4) I/O (A4) I/O (A4) I/O (A4) F15 I/O I/O I/O
M3 M3 GND GND GND GND GND F16 F16 I/O I/O I/O I/O I/O
M4 I/O I/O I/O F17 F17 N.C. I/O I/O I/O I/O
M15 I/O I/O I/O F18 F18 I/O I/O I/O I/O I/O
M16 M16 GND GND GND GND GND E1 E1 I/O I/O I/O I/O I/O
M17 M17 I/O I/O I/O I/O I/O E2 E2 I/O I/O I/O I/O I/O
M18 M18 I/O I/O I/O I/O I/O E3 E3 I/O I/O I/O I/O I/O
L1 L1 I/O I/O I/O I/O I/O E4 I/O I/O I/O
L2 L2 I/O I/O I/O I/O I/O E15 I/O I/O I/O
L3 L3 I/O I/O I/O I/O I/O E16 E16 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
L4 I/O I/O I/O E17 E17 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC)
L15 I/O I/O I/O E18 E18 I/O I/O I/O I/O I/O
L16 L16 I/O I/O I/O I/O I/O D1 D1 N.C. I/O I/O I/O I/O
L17 L17 I/O I/O I/O I/O I/O D2 D2 I/O (A13) I/O (A13) I/O (A13) I/O (A13) I/O (A13)
L18 L18 I/O I/O I/O I/O I/O D3 D3 VCC VCC VCC VCC VCC
K1 K1 I/O I/O I/O I/O I/O D4 D4 GND GND GND GND GND
K2 K2 I/O (A6) I/O (A6) I/O (A6) I/O (A6) I/O (A6) D5 I/O I/O I/O
K3 K3 I/O (A7) I/O (A7) I/O (A7) I/O (A7) I/O (A7) D6 I/O I/O I/O
K4 K4 GND GND GND GND GND D7 I/O I/O I/O
K15 K15 GND GND GND GND GND D8 I/O I/O I/O
K16 K16 I/O I/O I/O I/O I/O D9 D9 GND GND GND GND GND
K17 K17 I/O I/O I/O I/O I/O D10 D10 VCC VCC VCC VCC VCC
K18 K18 I/O I/O I/O I/O I/O D11 I/O I/O I/O
J1 J1 I/O I/O I/O I/O I/O D12 I/O I/O I/O
J2 J2 I/O (A9) I/O (A9) I/O (A9) I/O (A9) I/O (A9) D13 I/O I/O I/O
J3 J3 I/O (A8) I/O (A8) I/O (A8) I/O (A8) I/O (A8) D14 I/O I/O I/O
J4 J4 VCC VCC VCC VCC VCC D15 D15 GND GND GND GND GND
J15 J15 VCC VCC VCC VCC VCC D16 D16 VCC VCC VCC VCC VCC
J16 J16 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) D17 D17 I/O I/O I/O I/O I/O
J17 J17 I/O I/O I/O I/O I/O D18 D18 N.C. I/O I/O I/O I/O
J18 J18 I/O I/O I/O I/O I/O C1 C1 I/O I/O I/O I/O I/O
H1 H1 I/O I/O I/O I/O I/O C2 C2 I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14)
H2 H2 I/O I/O I/O I/O I/O C3 C3 I/O, I/O, I/O, I/O, I/O,
H3 H3 I/O I/O I/O I/O I/O PGCK1 PGCK1 PGCK1 PGCK1 PGCK1
(A16) (A16) (A16) (A16) (A16)
H4 I/O I/O I/O
C4 C4 I/O (A17) I/O (A17) I/O (A17) I/O (A17) I/O (A17)
H15 I/O I/O I/O
C5 C5 I/O I/O I/O I/O I/O
H16 H16 I/O I/O I/O I/O I/O
C6 C6 I/O I/O I/O I/O I/O
H17 H17 I/O I/O I/O I/O I/O
C7 C7 GND GND GND GND GND
H18 H18 I/O I/O I/O I/O I/O
C8 C8 I/O I/O I/O I/O I/O
G1 G1 I/O (A10) I/O (A10) I/O (A10) I/O (A10) I/O (A10)
C9 C9 I/O I/O I/O I/O I/O
G2 G2 I/O (A11) I/O (A11) I/O (A11) I/O (A11) I/O (A11)
C10 C10 I/O I/O I/O I/O I/O
G3 G3 GND GND GND GND GND
C11 C11 I/O I/O I/O I/O I/O
G4 I/O I/O I/O
C12 C12 GND GND GND GND GND
G15 I/O I/O I/O

September 18, 1996 (Version 1.04) 4-151

XC4000 Series Field Programmable Gate Arrays

PG PG PG PG
XC4008E XC4010E XC4013E XC4020E XC4025E XC4008E XC4010E XC4013E XC4020E XC4025E
223 191 223 191
PG191 PG191 PG223 PG223 PG223 PG191 PG191 PG223 PG223 PG223
Pin Pin Pin Pin
C13 C13 I/O I/O I/O I/O I/O A2 A2 I/O, TDI I/O, TDI I/O, TDI I/O, TDI I/O, TDI
C14 C14 I/O I/O I/O I/O I/O A3 A3 I/O I/O I/O I/O I/O
C15 C15 O (M1) O (M1) O (M1) O (M1) O (M1) A4 A4 I/O I/O I/O I/O I/O
C16 C16 I (M2) I (M2) I (M2) I (M2) I (M2) A5 A5 I/O I/O I/O I/O I/O
C17 C17 I/O I/O I/O I/O I/O A6 A6 I/O I/O I/O I/O I/O
C18 C18 I/O I/O I/O I/O I/O A7 A7 I/O I/O I/O I/O I/O
B1 B1 I/O I/O I/O I/O I/O A8 A8 I/O I/O I/O I/O I/O
B2 B2 I/O, I/O, I/O, I/O, I/O, A9 A9 I/O I/O I/O I/O I/O
SGCK1 SGCK1 SGCK1 SGCK1 SGCK1 A10 A10 I/O I/O I/O I/O I/O
(A15) (A15) (A15) (A15) (A15)
A11 A11 I/O I/O I/O I/O I/O
B3 B3 I/O I/O I/O I/O I/O
A12 A12 I/O I/O I/O I/O I/O
B4 B4 I/O, TCK I/O, TCK I/O, TCK I/O, TCK I/O, TCK
A13 A13 I/O I/O I/O I/O I/O
B5 B5 N.C. I/O I/O I/O I/O
A14 A14 N.C. I/O I/O I/O I/O
B6 B6 N.C. I/O I/O I/O I/O
A15 A15 I/O I/O I/O I/O I/O
B7 B7 I/O, TMS I/O, TMS I/O, TMS I/O, TMS I/O, TMS
A16 A16 I/O I/O I/O I/O I/O
B8 B8 I/O I/O I/O I/O I/O
A17 A17 I/O I/O I/O I/O I/O
B9 B9 I/O I/O I/O I/O I/O
A18 A18 I (M0) I (M0) I (M0) I (M0) I (M0)
B10 B10 I/O I/O I/O I/O I/O
B11 B11 I/O I/O I/O I/O I/O 2/28/96
B12 B12 I/O I/O I/O I/O I/O
B13 B13 N.C. I/O I/O I/O I/O Note: Shaded pins should be taken into account when
B14 B14 I/O I/O I/O I/O I/O designing PC boards, in case of future replacement by dif-
B15 B15 I/O I/O I/O I/O I/O ferent devices.
B16 B16 I/O, I/O, I/O, I/O, I/O, Note: Viewed from the bottom side, the package pins start
SCGK2 SCGK2 SCGK2 SCGK2 SCGK2 at the top row and go from the left edge to the right edge.
B17 B17 I/O, I/O, I/O, I/O, I/O, Viewed from the top side, the pins start at the top row and
PGCK2 PGCK2 PGCK2 PGCK2 PGCK2
go from the right edge to the left edge.
B18 B18 I/O I/O I/O I/O I/O

4-152 September 18, 1996 (Version 1.04)

BG225 Package Pinouts BG225 Pin XC4010E XC4013E/L
M10 N.C. I/O
The following table may contain pinout information for M11 I/O I/O
unsupported device/package combinations. Please see the M12 PROGRAM PROGRAM
availability charts elsewhere in the XC4000 Series data M13 I/O I/O
sheet for availability information. M14 N.C. I/O
M15 I/O I/O
BG225 Pin XC4010E XC4013E/L
L1 I/O I/O
R1 VCC VCC
L2 N.C. I/O
R2 I/O, PGCK2 I/O, PGCK2
L3 I/O I/O
R3 I/O I/O
L4 I/O I/O
R4 I/O I/O
L5 I/O I/O
R5 I/O I/O
L6 N.C. I/O
R6 I/O I/O
L7 I/O I/O
R7 I/O I/O
L8 I/O I/O
R8 VCC VCC
L9 I/O I/O
R9 I/O I/O
L10 I/O I/O
R10 N.C. I/O
L11 I/O I/O
R11 I/O I/O
L12 I/O I/O
R12 I/O I/O
L13 I/O I/O
R13 I/O I/O
L14 I/O I/O
R14 I/O I/O
L15 N.C. I/O
R15 VCC VCC
K1 N.C. I/O
P1 I/O, SCGK2 I/O, SCGK2
K2 I/O I/O
P2 I (M0) I (M0)
K3 I/O I/O
P3 I/O (HDC) I/O (HDC)
K4 N.C. I/O
P4 I/O (LDC) I/O (LDC)
K5 I/O I/O
P5 N.C. I/O
K6 I/O I/O
P6 I/O I/O
K7 I/O I/O
P7 N.C. I/O
K8 GND GND
P8 I/O (INIT) I/O (INIT)
K9 I/O I/O
P9 I/O I/O
K10 I/O I/O
P10 N.C. I/O
K11 I/O I/O
P11 I/O I/O
K12 N.C. I/O
P12 I/O I/O
K13 I/O I/O
P13 I/O I/O
K14 I/O I/O
P14 DONE DONE
K15 I/O (D5) I/O (D5)
P15 I/O (D7) I/O (D7)
J1 I/O I/O
N1 I/O I/O
J2 I/O I/O
N2 I/O I/O
J3 I/O I/O
N3 O (M1) O (M1)
J4 I/O I/O
N4 I/O I/O
J5 N.C. I/O
N5 I/O I/O
J6 I/O I/O
N6 I/O I/O
J7 GND GND
N7 N.C. I/O
J8 GND GND
N8 I/O I/O
J9 GND GND
N9 I/O I/O
J10 I/O (D6) I/O (D6)
N10 I/O I/O
J11 I/O I/O
N11 N.C. I/O
J12 I/O (CS0) I/O (CS0)
N12 I/O I/O
J13 I/O I/O
N13 I/O, SGCK3 I/O, SGCK3
J14 I/O I/O
N14 I/O, PGCK3 I/O, PGCK3
J15 I/O I/O
N15 N.C. I/O
H1 VCC VCC
M1 I/O I/O
H2 GND GND
M2 I/O I/O
H3 I/O I/O
M3 I/O I/O
H4 I/O I/O
M4 I (M2) I (M2)
H5 I/O I/O
M5 I/O I/O
H6 GND GND
M6 I/O I/O
H7 GND GND
M7 I/O I/O
H8 GND GND
M8 GND GND
H9 GND GND
M9 I/O I/O
H10 GND GND

September 18, 1996 (Version 1.04) 4-153

XC4000 Series Field Programmable Gate Arrays

BG225 Pin XC4010E XC4013E/L BG225 Pin XC4010E XC4013E/L

H11 I/O (RS) I/O (RS) D12 GND GND
H12 I/O (D3) I/O (D3) D13 I/O I/O
H13 I/O (D4) I/O (D4) D14 I/O I/O
H14 I/O I/O D15 I/O I/O
H15 VCC VCC C1 I/O, TCK I/O, TCK
G1 I/O I/O C2 I/O I/O
G2 I/O I/O C3 I/O, SGCK1 (A15) I/O, SGCK1 (A15)
G3 I/O I/O C4 N.C. I/O
G4 I/O I/O C5 I/O I/O
G5 I/O I/O C6 N.C. I/O
G6 I/O I/O C7 I/O I/O
G7 GND GND C8 I/O (A6) I/O (A6)
G8 GND GND C9 I/O I/O
G9 GND GND C10 N.C. I/O
G10 N.C. I/O C11 I/O I/O
G11 I/O (D2) I/O (D2) C12 I/O I/O
G12 I/O I/O C13 CCLK CCLK
G13 I/O I/O C14 I/O I/O
G14 I/O I/O C15 I/O (RCLK, I/O (RCLK,
G15 I/O I/O RDY/BUSY) RDY/BUSY)
F1 N.C. I/O B1 I/O (A17) I/O (A17)
F2 N.C. I/O B2 VCC VCC
F3 I/O I/O B3 I/O I/O
F4 I/O, TMS I/O, TMS B4 I/O (A12) I/O (A12)
F5 I/O I/O B5 I/O I/O
F6 I/O I/O B6 I/O (A11) I/O (A11)
F7 N.C. I/O B7 I/O (A9) I/O (A9)
F8 GND GND B8 I/O (A7) I/O (A7)
F9 N.C. I/O B9 I/O I/O
F10 I/O (D0, DIN) I/O (D0, DIN) B10 N.C. I/O
F11 I/O I/O B11 I/O I/O
F12 N.C. I/O B12 I/O (A3) I/O (A3)
F13 I/O I/O B13 I/O, PGCK4 (A1) I/O, PGCK4 (A1)
F14 I/O I/O B14 VCC VCC
F15 I/O I/O B15 I/O, SGCK4 (DOUT) I/O, SGCK4 (DOUT)
E1 I/O I/O A1 GND GND
E2 N.C. I/O A2 I/O (A14) I/O (A14)
E3 N.C. I/O A3 N.C. I/O
E4 I/O I/O A4 I/O I/O
E5 I/O I/O A5 I/O I/O
E6 I/O I/O A6 I/O (A10) I/O (A10)
E7 I/O I/O A7 I/O I/O
E8 I/O (A8) I/O (A8) A8 GND GND
E9 I/O I/O A9 I/O I/O
E10 I/O I/O A10 I/O (A4) I/O (A4)
E11 I/O I/O A11 I/O I/O
E12 I/O (D1) I/O (D1) A12 I/O I/O
E13 I/O I/O A13 I/O (CS1, A2) I/O (CS1, A2)
E14 N.C. I/O A14 I/O (A0, WS) I/O (A0, WS)
E15 N.C. I/O A15 O, TDO O, TDO
D1 I/O I/O 2/28/96
D2 I/O I/O
D3 I/O, TDI I/O, TDI
D4 I/O, PGCK1 (A16) I/O, PGCK1 (A16)
Note: Shaded pins should be taken into account when
D5 I/O (A13) I/O (A13) designing PC boards, in case of future replacement by dif-
D6 I/O I/O ferent devices.
D7 I/O I/O Note: Viewed from the bottom side, the package pins start
D8 VCC VCC
at the top row and go from the left edge to the right edge.
D9 I/O (A5) I/O (A5)
Viewed from the top side, the pins start at the top row and
D10 I/O I/O
D11 N.C. I/O
go from the right edge to the left edge.

4-154 September 18, 1996 (Version 1.04)

PQ240, HQ240 Package Pinouts PQ240/ XC4013E XC4028EX
XC4020E XC4025E
The following table may contain pinout information for HQ240 Pin XC4013L XC4028XL
unsupported device/package combinations. Please see the P41 I/O I/O I/O I/O
availability charts elsewhere in the XC4000 Series data P42 I/O I/O I/O I/O
sheet for availability information. P43 I/O I/O I/O I/O
P44 I/O I/O I/O I/O, FCLK2
PQ240/ XC4013E XC4028EX
XC4020E XC4025E P45 GND GND GND GND
HQ240 Pin XC4013L XC4028XL
P1 GND GND GND GND P46 I/O I/O I/O I/O
P2 I/O, I/O, I/O, I/O, P47 I/O I/O I/O I/O
PGCK1 PGCK1 PGCK1 GCK1 P48 I/O I/O I/O I/O
(A16) (A16) (A16) (A16) P49 I/O I/O I/O I/O
P3 I/O (A17) I/O (A17) I/O (A17) I/O (A17) P50 I/O I/O I/O I/O
P4 I/O I/O I/O I/O P51 I/O I/O I/O I/O
P5 I/O I/O I/O I/O P52 I/O I/O I/O I/O
P6 I/O, TDI I/O, TDI I/O, TDI I/O, TDI P53 I/O I/O I/O I/O
P7 I/O, TCK I/O, TCK I/O, TCK I/O, TCK P54 I/O I/O I/O I/O
P8 I/O I/O I/O I/O P55 I/O I/O I/O I/O
P9 I/O I/O I/O I/O P56 I/O I/O I/O I/O
P10 I/O I/O I/O I/O P57 I/O, I/O, I/O, I/O,
P11 I/O I/O I/O I/O SGCK2 SGCK2 SGCK2 GCK2
P12 I/O I/O I/O I/O P58 O (M1) O (M1) O (M1) O (M1)
P13 I/O I/O I/O I/O P59 GND GND GND GND
P14 GND GND GND GND P60 I (M0) I (M0) I (M0) I (M0)
P15 I/O I/O I/O I/O, FCLK1 P61 VCC VCC VCC VCC
P16 I/O I/O I/O I/O P62 I (M2) I (M2) I (M2) I (M2)
P17 I/O, TMS I/O, TMS I/O, TMS I/O, TMS P63 I/O, I/O, I/O, I/O,
P18 I/O I/O I/O I/O PGCK2 PGCK2 PGCK2 GCK3
P19 VCC VCC VCC VCC P64 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
P20 I/O I/O I/O I/O P65 I/O I/O I/O I/O
P21 I/O I/O I/O I/O P66 I/O I/O I/O I/O
P22 N.C.‡ N.C.‡ N.C.‡ GND‡ P67 I/O I/O I/O I/O
P23 I/O I/O I/O I/O P68 I/O (LDC) I/O (LDC) I/O (LDC) I/O (LDC)
P24 I/O I/O I/O I/O P69 I/O I/O I/O I/O
P25 I/O I/O I/O I/O P70 I/O I/O I/O I/O
P26 I/O I/O I/O I/O P71 I/O I/O I/O I/O
P27 I/O I/O I/O I/O P72 I/O I/O I/O I/O
P28 I/O I/O I/O I/O P73 I/O I/O I/O I/O
P29 GND GND GND GND P74 I/O I/O I/O I/O
P30 VCC VCC VCC VCC P75 GND GND GND GND
P31 I/O I/O I/O I/O P76 I/O I/O I/O I/O
P32 I/O I/O I/O I/O P77 I/O I/O I/O I/O
P33 I/O I/O I/O I/O P78 I/O I/O I/O I/O
P34 I/O I/O I/O I/O P79 I/O I/O I/O I/O
P35 I/O I/O I/O I/O P80 VCC VCC VCC VCC
P36 I/O I/O I/O I/O P81 I/O I/O I/O I/O
P37 N.C.‡ N.C.‡ N.C.‡ GND‡ P82 I/O I/O I/O I/O
P38 I/O I/O I/O I/O P83 N.C.‡ N.C.‡ N.C.‡ GND‡
P39 I/O I/O I/O I/O P84 I/O I/O I/O I/O
P40 VCC VCC VCC VCC P85 I/O I/O I/O I/O

September 18, 1996 (Version 1.04) 4-155

XC4000 Series Field Programmable Gate Arrays

PQ240/ XC4013E XC4028EX PQ240/ XC4013E XC4028EX

XC4020E XC4025E XC4020E XC4025E
HQ240 Pin XC4013L XC4028XL HQ240 Pin XC4013L XC4028XL
P86 I/O I/O I/O I/O P130 I/O I/O I/O I/O
P87 I/O I/O I/O I/O P131 I/O I/O I/O I/O
P88 I/O I/O I/O I/O P132 I/O I/O I/O I/O
P89 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) P133 I/O I/O I/O I/O
P90 VCC VCC VCC VCC P134 I/O I/O I/O I/O
P91 GND GND GND GND P135 GND GND GND GND
P92 I/O I/O I/O I/O P136 I/O I/O I/O I/O
P93 I/O I/O I/O I/O P137 I/O I/O I/O I/O
P94 I/O I/O I/O I/O P138 I/O I/O I/O I/O, FCLK3
P95 I/O I/O I/O I/O P139 I/O I/O I/O I/O
P96 I/O I/O I/O I/O P140 VCC VCC VCC VCC
P97 I/O I/O I/O I/O P141 I/O (D5) I/O (D5) I/O (D5) I/O (D5)
P98 N.C.‡ N.C.‡ N.C.‡ GND‡ P142 I/O (CS0) I/O (CS0) I/O (CS0) I/O (CS0)
P99 I/O I/O I/O I/O P143 N.C.‡ N.C.‡ N.C.‡ GND‡
P100 I/O I/O I/O I/O P144 I/O I/O I/O I/O
P101 VCC VCC VCC VCC P145 I/O I/O I/O I/O
P102 I/O I/O I/O I/O P146 I/O I/O I/O I/O
P103 I/O I/O I/O I/O P147 I/O I/O I/O I/O
P104 I/O I/O I/O I/O P148 I/O (D4) I/O (D4) I/O (D4) I/O (D4)
P105 I/O I/O I/O I/O P149 I/O I/O I/O I/O
P106 GND GND GND GND P150 VCC VCC VCC VCC
P107 I/O I/O I/O I/O P151 GND GND GND GND
P108 I/O I/O I/O I/O P152 I/O (D3) I/O (D3) I/O (D3) I/O (D3)
P109 I/O I/O I/O I/O P153 I/O (RS) I/O (RS) I/O (RS) I/O (RS)
P110 I/O I/O I/O I/O P154 I/O I/O I/O I/O
P111 I/O I/O I/O I/O P155 I/O I/O I/O I/O
P112 I/O I/O I/O I/O P156 I/O I/O I/O I/O
P113 I/O I/O I/O I/O P157 I/O I/O I/O I/O
P114 I/O I/O I/O I/O P158 N.C.‡ N.C.‡ N.C.‡ GND‡
P115 I/O I/O I/O I/O P159 I/O (D2) I/O (D2) I/O (D2) I/O (D2)
P116 I/O I/O I/O I/O P160 I/O I/O I/O I/O
P117 I/O I/O I/O I/O P161 VCC VCC VCC VCC
P118 I/O, I/O, I/O, I/O, P162 I/O I/O I/O I/O
SGCK3 SGCK3 SGCK3 GCK4 P163 I/O I/O I/O I/O, FCLK4
P119 GND GND GND GND P164 I/O I/O I/O I/O
P120 DONE DONE DONE DONE P165 I/O I/O I/O I/O
P121 VCC VCC VCC VCC P166 GND GND GND GND
P122 PRO- PRO- PRO- PRO- P167 I/O I/O I/O I/O
GRAM GRAM GRAM GRAM P168 I/O I/O I/O I/O
P123 I/O (D7) I/O (D7) I/O (D7) I/O (D7) P169 I/O I/O I/O I/O
P124 I/O, I/O, I/O, I/O, P170 I/O I/O I/O I/O
PGCK3 PGCK3 PGCK3 GCK5
P171 I/O I/O I/O I/O
P125 I/O I/O I/O I/O
P172 I/O I/O I/O I/O
P126 I/O I/O I/O I/O
P173 I/O (D1) I/O (D1) I/O (D1) I/O (D1)
P127 I/O I/O I/O I/O
P128 I/O I/O I/O I/O
P129 I/O (D6) I/O (D6) I/O (D6) I/O (D6)

4-156 September 18, 1996 (Version 1.04)

 PQ240/ XC4013E XC4028EX PQ240/ XC4013E XC4028EX
XC4020E XC4025E XC4020E XC4025E
HQ240 Pin XC4013L XC4028XL HQ240 Pin XC4013L XC4028XL
P174 I/O I/O I/O I/O P210 I/O (A7) I/O (A7) I/O (A7) I/O (A7)
(RCLK, (RCLK, (RCLK, (RCLK, P211 GND GND GND GND
RDY/ RDY/ RDY/ RDY/ P212 VCC VCC VCC VCC
BUSY) BUSY) BUSY) BUSY)
P213 I/O (A8) I/O (A8) I/O (A8) I/O (A8)
P175 I/O I/O I/O I/O
P214 I/O (A9) I/O (A9) I/O (A9) I/O (A9)
P176 I/O I/O I/O I/O
P215 I/O I/O I/O I/O (A19)
P177 I/O I/O I/O I/O
P216 I/O I/O I/O I/O (A18)
(D0, DIN) (D0, DIN) (D0, DIN) (D0, DIN)
P217 I/O I/O I/O I/O
P178 I/O, I/O, I/O, I/O,
SGCK4 SGCK4 SGCK4 GCK6 P218 I/O I/O I/O I/O
(DOUT) (DOUT) (DOUT) (DOUT) P219 N.C.‡ N.C.‡ N.C.‡ GND‡
P179 CCLK CCLK CCLK CCLK P220 I/O (A10) I/O (A10) I/O (A10) I/O (A10)
P180 VCC VCC VCC VCC P221 I/O (A11) I/O (A11) I/O (A11) I/O (A11)
P181 O, TDO O, TDO O, TDO O, TDO P222 VCC VCC VCC VCC
P182 GND GND GND GND P223 I/O I/O I/O I/O
P183 I/O I/O I/O I/O P224 I/O I/O I/O I/O
(A0, WS) (A0, WS) (A0, WS) (A0, WS) P225 I/O I/O I/O I/O
P184 I/O, I/O, I/O, I/O, P226 I/O I/O I/O I/O
PGCK4 PGCK4 PGCK4 GCK7 P227 GND GND GND GND
(A1) (A1) (A1) (A1) P228 I/O I/O I/O I/O
P185 I/O I/O I/O I/O P229 I/O I/O I/O I/O
P186 I/O I/O I/O I/O P230 I/O I/O I/O I/O
P187 I/O (CS1, I/O (CS1, I/O (CS1, I/O (CS1, P231 I/O I/O I/O I/O
A2) A2) A2) A2) P232 I/O (A12) I/O (A12) I/O (A12) I/O (A12)
P188 I/O (A3) I/O (A3) I/O (A3) I/O (A3) P233 I/O (A13) I/O (A13) I/O (A13) I/O (A13)
P189 I/O I/O I/O I/O P234 I/O I/O I/O I/O
P190 I/O I/O I/O I/O P235 I/O I/O I/O I/O
P191 I/O I/O I/O I/O P236 I/O I/O I/O I/O
P192 I/O I/O I/O I/O P237 I/O I/O I/O I/O
P193 I/O I/O I/O I/O P238 I/O (A14) I/O (A14) I/O (A14) I/O (A14)
P194 I/O I/O I/O I/O P239 I/O, I/O, I/O, I/O,
P195 N.C. N.C. I/O I/O SGCK1 SGCK1 SGCK1 GCK8
P196 GND GND GND GND (A15) (A15) (A15) (A15)
P197 I/O I/O I/O I/O P240 VCC VCC VCC VCC
P198 I/O I/O I/O I/O 3/11/96
P199 I/O I/O I/O I/O
P200 I/O I/O I/O I/O ‡ Pins labelled GND‡ should be connected to Ground if
possible; however, they can be left unconnected if neces-
P201 VCC VCC VCC VCC
sary for compatibility with other devices. Pins labelled
P202 I/O (A4) I/O (A4) I/O (A4) I/O (A4)
N.C.‡ are reserved for Ground connections on future revi-
P203 I/O (A5) I/O (A5) I/O (A5) I/O (A5) sions of the device. These pins do not physically connect
P204 N.C.‡ N.C.‡ N.C.‡ GND‡ to anything on the current device revision. However, they
P205 I/O I/O I/O I/O should be externally connected to Ground if possible.
P206 I/O I/O I/O I/O
P207 I/O I/O I/O I/O (A21) Note: Shaded pins should be taken into account when de-
signing PC boards, in case of future replacement by differ-
P208 I/O I/O I/O I/O (A20)
ent devices.
P209 I/O (A6) I/O (A6) I/O (A6) I/O (A6)

September 18, 1996 (Version 1.04) 4-157

XC4000 Series Field Programmable Gate Arrays

PG299 Package Pinouts PG299 Pin XC4025E XC4028EX/XL

V8 I/O I/O
The following table may contain pinout information for
V9 I/O I/O
unsupported device/package combinations. Please see the
availability charts elsewhere in the XC4000 Series data V10 I/O (RS) I/O (RS)
sheet for availability information. V11 I/O (D4) I/O (D4)
V12 I/O I/O
PG299 Pin XC4025E XC4028EX/XL V13 I/O I/O
X1 I/O, SGCK4 (DOUT) I/O, GCK6 (DOUT) V14 I/O I/O
X2 GND GND V15 I/O I/O
X3 I/O I/O V16 I/O I/O
X4 I/O I/O V17 I/O I/O
X5 VCC VCC V18 DONE DONE
X6 GND GND V19 I/O I/O
X7 I/O I/O V20 I/O I/O
X8 I/O I/O U1 I/O I/O
X9 I/O I/O U2 I/O I/O
X10 VCC VCC U3 I/O (CS1, A2) I/O (CS1, A2)
X11 GND GND U4 O, TDO O, TDO
X12 I/O I/O U5 I/O I/O
X13 I/O I/O U6 I/O (D1) I/O (D1)
X14 I/O (CS0) I/O (CS0) U7 I/O I/O
X15 VCC VCC U8 I/O I/O
X16 GND GND U9 I/O I/O
X17 I/O I/O U10 I/O I/O
X18 I/O I/O U11 I/O I/O
X19 VCC VCC U12 I/O I/O
X20 I/O, SGCK3 I/O, GCK4 U13 I/O I/O
W1 VCC VCC U14 I/O I/O
W2 I/O (A0, WS) I/O (A0, WS) U15 I/O I/O
W3 I/O I/O U16 I/O I/O
W4 I/O I/O U17 PROGRAM PROGRAM
W5 I/O I/O U18 I/O I/O
W6 I/O I/O U19 I/O I/O
W7 I/O I/O, FCLK4 U20 I/O I/O
W8 I/O (D2) I/O (D2) T1 GND GND
W9 I/O I/O T2 I/O I/O
W10 I/O (D3) I/O (D3) T3 I/O I/O
W11 I/O I/O T4 I/O I/O
W12 I/O I/O T5 GND GND
W13 I/O I/O T6 I/O I/O
W14 I/O I/O, FCLK3 T7 I/O I/O
W15 I/O I/O T8 I/O I/O
W16 I/O I/O T9 I/O I/O
W17 I/O (D6) I/O (D6) T10 I/O I/O
W18 I/O, PGCK3 I/O, GCK5 T11 I/O I/O
W19 I/O (D7) I/O (D7) T12 I/O (D5) I/O (D5)
W20 GND GND T13 I/O I/O
V1 I/O (A3) I/O (A3) T14 I/O I/O
V2 I/O, PGCK4 (A1) I/O, GCK7 (A1) T15 I/O I/O
V3 CCLK CCLK T16 VCC VCC
V4 I/O (D0, DIN) I/O (D0, DIN) T17 I/O I/O
V5 I/O (RCLK, I/O (RCLK, T18 I/O I/O
RDY/BUSY) RDY/BUSY)
T19 I/O I/O
V6 I/O I/O
T20 VCC VCC
V7 I/O I/O

4-158 September 18, 1996 (Version 1.04)

 PG299 Pin XC4025E XC4028EX/XL PG299 Pin XC4025E XC4028EX/XL
R1 VCC VCC K4 I/O I/O (A18)
R2 I/O I/O K5 I/O I/O (A19)
R3 I/O I/O K16 I/O I/O
R4 I/O I/O K17 I/O I/O
R5 I/O I/O K18 I/O I/O
R16 I/O I/O K19 I/O (INIT) I/O (INIT)
R17 I/O I/O K20 GND GND
R18 I/O I/O J1 I/O I/O
R19 I/O I/O J2 I/O I/O
R20 GND GND J3 I/O (A11) I/O (A11)
P1 I/O I/O J4 I/O I/O
P2 I/O I/O J5 I/O I/O
P3 I/O I/O J16 I/O I/O
P4 I/O I/O J17 I/O I/O
P5 I/O I/O J18 I/O I/O
P16 I/O I/O J19 I/O I/O
P17 I/O I/O J20 I/O I/O
P18 I/O I/O H1 I/O (A10) I/O (A10)
P19 I/O I/O H2 I/O I/O
P20 I/O I/O H3 I/O I/O
N1 I/O (A4) I/O (A4) H4 I/O I/O
N2 I/O I/O H5 I/O I/O
N3 I/O I/O H16 I/O I/O
N4 I/O I/O H17 I/O I/O
N5 I/O I/O H18 I/O I/O
N16 I/O I/O H19 I/O I/O
N17 I/O I/O H20 I/O I/O
N18 I/O I/O G1 I/O I/O
N19 I/O I/O G2 I/O I/O
N20 I/O I/O G3 I/O I/O
M1 I/O I/O (A21) G4 I/O I/O
M2 I/O I/O G5 I/O (A12) I/O (A12)
M3 I/O (A5) I/O (A5) G16 I/O I/O
M4 I/O I/O G17 I/O I/O
M5 I/O I/O G18 I/O I/O
M16 I/O I/O G19 I/O I/O
M17 I/O I/O G20 I/O I/O
M18 I/O I/O F1 GND GND
M19 I/O I/O F2 I/O I/O
M20 I/O I/O F3 I/O I/O
L1 GND GND F4 I/O I/O
L2 I/O (A7) I/O (A7) F5 I/O I/O
L3 I/O (A6) I/O (A6) F16 I/O I/O
L4 I/O I/O (A20) F17 I/O I/O
L5 I/O I/O F18 I/O I/O
L16 I/O I/O F19 I/O I/O
L17 I/O I/O F20 VCC VCC
L18 I/O I/O E1 VCC VCC
L19 I/O I/O E2 I/O I/O
L20 VCC VCC E3 I/O I/O
K1 VCC VCC E4 I/O I/O
K2 I/O (A8) I/O (A8) E5 VCC VCC
K3 I/O (A9) I/O (A9) E6 I/O I/O

September 18, 1996 (Version 1.04) 4-159

XC4000 Series Field Programmable Gate Arrays

PG299 Pin XC4025E XC4028EX/XL PG299 Pin XC4025E XC4028EX/XL

E7 I/O I/O C20 I/O (LDC) I/O (LDC)
E8 I/O I/O B1 GND GND
E9 I/O I/O B2 I/O (A17) I/O (A17)
E10 I/O I/O B3 I/O I/O
E11 I/O I/O B4 I/O I/O
E12 I/O I/O B5 I/O I/O
E13 I/O I/O B6 I/O I/O, FCLK1
E14 I/O I/O B7 I/O I/O
E15 I/O I/O B8 I/O I/O
E16 GND GND B9 I/O I/O
E17 I/O I/O B10 I/O I/O
E18 I/O I/O B11 I/O I/O
E19 I/O I/O B12 I/O I/O
E20 GND GND B13 I/O I/O
D1 I/O I/O B14 I/O I/O
D2 I/O I/O B15 I/O I/O
D3 I/O (A14) I/O (A14) B16 I/O I/O
D4 I/O, PGCK1 (A16) I/O, GCK1 (A16) B17 I/O I/O
D5 I/O, TDI I/O, TDI B18 I/O I/O
D6 I/O I/O B19 I/O, PGCK2 I/O, GCK3
D7 I/O I/O B20 VCC VCC
D8 I/O I/O A2 VCC VCC
D9 I/O I/O A3 I/O I/O
D10 I/O I/O A4 I/O I/O
D11 I/O I/O A5 GND GND
D12 I/O I/O A6 VCC VCC
D13 I/O I/O, FCLK2 A7 I/O I/O
D14 I/O I/O A8 I/O I/O
D15 I/O I/O A9 I/O I/O
D16 I/O I/O A10 GND GND
D17 I (M2) I (M2) A11 VCC VCC
D18 I/O I/O A12 I/O I/O
D19 I/O I/O A13 I/O I/O
D20 I/O I/O A14 I/O I/O
C1 I/O (A13) I/O (A13) A15 GND GND
C2 I/O I/O A16 VCC VCC
C3 I/O, SGCK1 (A15) I/O, GCK8 (A15) A17 I/O I/O
C4 I/O, TCK I/O, TCK A18 I/O I/O
C5 I/O I/O A19 GND GND
C6 I/O I/O A20 O (M1) O (M1)
C7 I/O, TMS I/O, TMS
3/18/96
C8 I/O I/O
C9 I/O I/O Note: Shaded pins should be taken into account when de-
C10 I/O I/O signing PC boards, in case of future replacement by differ-
C11 I/O I/O ent devices.
C12 I/O I/O Note: Viewed from the bottom side, the package pins start
C13 I/O I/O at the top row and go from the left edge to the right edge.
C14 I/O I/O Viewed from the top side, the pins start at the top row and
C15 I/O I/O go from the right edge to the left edge.
C16 I/O I/O
C17 I/O, SGCK2 I/O, GCK2
C18 I (M0) I (M0)
C19 I/O (HDC) I/O (HDC)

4-160 September 18, 1996 (Version 1.04)

HQ304 Package Pinouts HQ304
XC4025E
XC4028EX XC4036EX
Pin XC4028XL XC4036XL
The following table may contain pinout information for
P47 I/O (A4) I/O (A4) I/O (A4)
unsupported device/package combinations. Please see the
P48 I/O I/O I/O
availability charts elsewhere in the XC4000 Series data
P49 I/O I/O I/O
sheet for availability information.
P50 I/O I/O I/O
HQ304 XC4028EX XC4036EX P51 I/O I/O I/O
XC4025E
Pin XC4028XL XC4036XL P52 VCC VCC VCC
P1 VCC VCC VCC P53 N.C. N.C. N.C.
P2 I/O, SGCK1 (A15) I/O, GCK8 I/O, GCK8 P54 I/O I/O I/O
(A15) (A15) P55 I/O I/O I/O
P3 I/O (A14) I/O (A14) I/O (A14) P56 I/O I/O I/O
P4 I/O I/O I/O P57 I/O I/O I/O
P5 I/O I/O I/O P58 GND GND GND
P6 I/O I/O I/O P59 I/O I/O I/O
P7 I/O I/O I/O P60 I/O I/O I/O
P8 I/O I/O I/O P61 I/O I/O I/O
P9 I/O I/O I/O P62 I/O I/O I/O
P10 I/O (A13) I/O (A13) I/O (A13) P63 I/O I/O I/O
P11 N.C. N.C. N.C. P64 I/O I/O I/O
P12 I/O (A12) I/O (A12) I/O (A12) P65 I/O I/O I/O
P13 I/O I/O I/O P66 I/O I/O I/O
P14 I/O I/O I/O P67 I/O I/O I/O
P15 I/O I/O I/O P68 I/O I/O I/O
P16 I/O I/O I/O P69 I/O (A3) I/O (A3) I/O (A3)
P17 I/O I/O I/O P70 I/O (CS1, A2) I/O (CS1, A2) I/O (CS1, A2)
P18 I/O I/O I/O P71 I/O I/O I/O
P19 GND GND GND P72 I/O I/O I/O
P20 I/O I/O I/O P73 I/O, PGCK4 (A1) I/O, GCK7 (A1) I/O, GCK7 (A1)
P21 I/O I/O I/O P74 I/O (A0, WS) I/O (A0, WS) I/O (A0, WS)
P22 I/O I/O I/O P75 GND GND GND
P23 I/O I/O I/O P76 O, TDO O, TDO O, TDO
P24 N.C. N.C. N.C. P77 VCC VCC VCC
P25 VCC VCC VCC P78 CCLK CCLK CCLK
P26 I/O I/O I/O P79 I/O, SGCK4 I/O, GCK6 I/O, GCK6
P27 I/O I/O I/O (DOUT) (DOUT) (DOUT)
P28 I/O I/O I/O P80 I/O (D0, DIN) I/O (D0, DIN) I/O (D0, DIN)
P29 I/O I/O I/O P81 I/O I/O I/O
P30 I/O (A11) I/O (A11) I/O (A11) P82 I/O I/O I/O
P31 I/O (A10) I/O (A10) I/O (A10) P83 I/O I/O I/O
P32 I/O I/O I/O P84 I/O I/O I/O
P33 I/O I/O I/O P85 I/O (RCLK, I/O (RCLK, I/O (RCLK,
P34 I/O I/O (A18) I/O (A18) RDY/BUSY) RDY/BUSY) RDY/BUSY)
P35 I/O I/O (A19) I/O (A19) P86 I/O (D1) I/O (D1) I/O (D1)
P36 I/O (A9) I/O (A9) I/O (A9) P87 I/O I/O I/O
P37 I/O (A8) I/O (A8) I/O (A8) P88 I/O I/O I/O
P38 VCC VCC VCC P89 I/O I/O I/O
P39 GND GND GND P90 I/O I/O I/O
P40 I/O (A7) I/O (A7) I/O (A7) P91 I/O I/O I/O
P41 I/O (A6) I/O (A6) I/O (A6) P92 I/O I/O I/O
P42 I/O I/O (A20) I/O (A20) P93 I/O I/O I/O
P43 I/O I/O (A21) I/O (A21) P94 I/O I/O I/O
P44 I/O I/O I/O P95 GND GND GND
P45 I/O I/O I/O P96 I/O I/O I/O
P46 I/O (A5) I/O (A5) I/O (A5) P97 I/O I/O I/O
P98 I/O I/O, FCLK4 I/O, FCLK4

September 18, 1996 (Version 1.04) 4-161

XC4000 Series Field Programmable Gate Arrays

HQ304 XC4028EX XC4036EX HQ304 XC4028EX XC4036EX

XC4025E XC4025E
Pin XC4028XL XC4036XL Pin XC4028XL XC4036XL
P99 I/O I/O I/O P152 VCC VCC VCC
P100 N.C. N.C. N.C. P153 DONE DONE DONE
P101 VCC VCC VCC P154 GND GND GND
P102 I/O I/O I/O P155 I/O, SGCK3 I/O, GCK4 I/O, GCK4
P103 I/O (D2) I/O (D2) I/O (D2) P156 I/O I/O I/O
P104 I/O I/O I/O P157 I/O I/O I/O
P105 I/O I/O I/O P158 I/O I/O I/O
P106 I/O I/O I/O P159 I/O I/O I/O
P107 I/O I/O I/O P160 I/O I/O I/O
P108 I/O I/O I/O P161 I/O I/O I/O
P109 I/O I/O I/O P162 I/O I/O I/O
P110 I/O I/O I/O P163 I/O I/O I/O
P111 I/O I/O I/O P164 I/O I/O I/O
P112 I/O (RS) I/O (RS) I/O (RS) P165 I/O I/O I/O
P113 I/O (D3) I/O (D3) I/O (D3) P166 I/O I/O I/O
P114 GND GND GND P167 I/O I/O I/O
P115 VCC VCC VCC P168 I/O I/O I/O
P116 I/O I/O I/O P169 I/O I/O I/O
P117 I/O (D4) I/O (D4) I/O (D4) P170 I/O I/O I/O
P118 I/O I/O I/O P171 GND GND GND
P119 I/O I/O I/O P172 I/O I/O I/O
P120 I/O I/O I/O P173 I/O I/O I/O
P121 I/O I/O I/O P174 I/O I/O I/O
P122 I/O I/O I/O P175 I/O I/O I/O
P123 I/O I/O I/O P176 N.C. N.C. N.C.
P124 I/O I/O I/O P177 VCC VCC VCC
P125 I/O I/O I/O P178 I/O I/O I/O
P126 I/O (CS0) I/O (CS0) I/O (CS0) P179 I/O I/O I/O
P127 I/O (D5) I/O (D5) I/O (D5) P180 I/O I/O I/O
P128 N.C. N.C. N.C. P181 I/O I/O I/O
P129 VCC VCC VCC P182 I/O I/O I/O
P130 I/O I/O I/O P183 I/O I/O I/O
P131 I/O I/O, FCLK3 I/O, FCLK3 P184 I/O I/O I/O
P132 I/O I/O I/O P185 I/O I/O I/O
P133 I/O I/O I/O P186 I/O I/O I/O
P134 GND GND GND P187 I/O I/O I/O
P135 I/O I/O I/O P188 I/O I/O I/O
P136 I/O I/O I/O P189 I/O I/O I/O
P137 I/O I/O I/O P190 GND GND GND
P138 I/O I/O I/O P191 VCC VCC VCC
P139 I/O I/O I/O P192 I/O (INIT) I/O (INIT) I/O (INIT)
P140 I/O I/O I/O P193 I/O I/O I/O
P141 I/O I/O I/O P194 I/O I/O I/O
P142 I/O (D6) I/O (D6) I/O (D6) P195 I/O I/O I/O
P143 I/O I/O I/O P196 I/O I/O I/O
P144 I/O I/O I/O P197 I/O I/O I/O
P145 I/O I/O I/O P198 I/O I/O I/O
P146 I/O I/O I/O P199 I/O I/O I/O
P147 I/O I/O I/O P200 I/O I/O I/O
P148 I/O I/O I/O P201 I/O I/O I/O
P149 I/O, PGCK3 I/O, GCK5 I/O, GCK5 P202 I/O I/O I/O
P150 I/O (D7) I/O (D7) I/O (D7) P203 I/O I/O I/O
P151 PROGRAM PROGRAM PROGRAM P204 VCC VCC VCC

4-162 September 18, 1996 (Version 1.04)

HQ304 XC4028EX XC4036EX HQ304 XC4028EX XC4036EX
XC4025E XC4025E
Pin XC4028XL XC4036XL Pin XC4028XL XC4036XL
P205 N.C. N.C. N.C. P258 I/O I/O I/O
P206 I/O I/O I/O P259 I/O I/O I/O
P207 I/O I/O I/O P260 I/O I/O I/O
P208 I/O I/O I/O P261 I/O I/O I/O
P209 I/O I/O I/O P262 I/O I/O I/O
P210 GND GND GND P263 I/O I/O I/O
P211 I/O I/O I/O P264 I/O I/O I/O
P212 I/O I/O I/O P265 I/O I/O I/O
P213 I/O I/O I/O P266 I/O I/O I/O
P214 I/O I/O I/O P267 VCC VCC VCC
P215 I/O I/O I/O P268 GND GND GND
P216 I/O I/O I/O P269 I/O I/O I/O
P217 I/O I/O I/O P270 I/O I/O I/O
P218 I/O I/O I/O P271 I/O I/O I/O
P219 I/O I/O I/O P272 I/O I/O I/O
P220 I/O I/O I/O P273 I/O I/O I/O
P221 I/O (LDC) I/O (LDC) I/O (LDC) P274 I/O I/O I/O
P222 I/O I/O I/O P275 I/O I/O I/O
P223 I/O I/O I/O P276 I/O I/O I/O
P224 I/O I/O I/O P277 I/O I/O I/O
P225 I/O (HDC) I/O (HDC) I/O (HDC) P278 I/O I/O I/O
P226 I/O, PGCK2 I/O, GCK3 I/O, GCK3 P279 I/O I/O I/O
P227 I (M2) I (M2) I (M2) P280 I/O I/O I/O
P228 VCC VCC VCC P281 N.C. N.C. N.C.
P229 I (M0) I (M0) I (M0) P282 VCC VCC VCC
P230 GND GND GND P283 I/O I/O I/O
P231 O (M1) O (M1) O (M1) P284 I/O, TMS I/O, TMS I/O, TMS
P232 I/O, SGCK2 I/O, GCK2 I/O, GCK2 P285 I/O I/O I/O
P233 I/O I/O I/O P286 I/O I/O, FCLK1 I/O, FCLK1
P234 I/O I/O I/O P287 GND GND GND
P235 I/O I/O I/O P288 I/O I/O I/O
P236 I/O I/O I/O P289 I/O I/O I/O
P237 I/O I/O I/O P290 I/O I/O I/O
P238 I/O I/O I/O P291 I/O I/O I/O
P239 I/O I/O I/O P292 I/O I/O I/O
P240 I/O I/O I/O P293 I/O I/O I/O
P241 I/O I/O I/O P294 I/O I/O I/O
P242 I/O I/O I/O P295 I/O I/O I/O
P243 I/O I/O I/O P296 I/O I/O I/O
P244 I/O I/O I/O P297 I/O I/O I/O
P245 I/O I/O I/O P298 I/O, TCK I/O, TCK I/O, TCK
P246 I/O I/O I/O P299 I/O, TDI I/O, TDI I/O, TDI
P247 I/O I/O I/O P300 I/O I/O I/O
P248 GND GND GND P301 I/O I/O I/O
P249 I/O I/O, FCLK2 I/O, FCLK2 P302 I/O (A17) I/O (A17) I/O (A17)
P250 I/O I/O I/O P303 I/O, PGCK1 I/O, GCK1 I/O, GCK1
P251 I/O I/O I/O (A16) (A16) (A16)
P252 I/O I/O I/O P304 GND GND GND
P253 VCC VCC VCC 3/20/96
P254 N.C. N.C. N.C.
P255 I/O I/O I/O Note: Shaded pins should be taken into account when de-
P256 I/O I/O I/O signing PC boards, in case of future replacement by differ-
P257 I/O I/O I/O ent devices.

September 18, 1996 (Version 1.04) 4-163

XC4000 Series Field Programmable Gate Arrays

BG352 Package Pinouts BG352 Pin XC4028EX/XL

AD3 DONE
The following table may contain pinout information for AD4 I/O
unsupported device/package combinations. Please see the AD5 I/O
availability charts elsewhere in the XC4000 Series data AD6 I/O
sheet for availability information. AD7 I/O
AD8 I/O
BG352 Pin XC4028EX/XL
AD9 I/O
AF1 GND
AD10 I/O
AF2 GND
AD11 I/O
AF3 I/O
AD12 I/O
AF4 I/O
AD13 I/O
AF5 GND
AD14 I/O
AF6 I/O
AD15 I/O
AF7 I/O
AD16 N.C.
AF8 GND
AD17 I/O
AF9 I/O
AD18 I/O
AF10 VCC
AD19 I/O
AF11 I/O
AD20 I/O
AF12 I/O
AD21 N.C.
AF13 GND
AD22 I/O
AF14 I/O (INIT)
AD23 I/O (HDC)
AF15 I/O
AD24 I (M0)
AF16 I/O
AD25 I/O
AF17 VCC
AD26 N.C.
AF18 I/O
AC1 I/O
AF19 GND
AC2 N.C.
AF20 I/O
AC3 I/O, GCK5
AF21 I/O
AC4 PROGRAM
AF22 GND
AC5 I/O, GCK4
AF23 I/O
AC6 N.C.
AF24 I/O
AC7 I/O
AF25 GND
AC8 VCC
AF26 GND
AC9 I/O
AE1 GND
AC10 I/O
AE2 VCC
AC11 N.C.
AE3 I/O
AC12 I/O
AE4 N.C.
AC13 I/O
AE5 I/O
AC14 VCC
AE6 I/O
AC15 I/O
AE7 I/O
AC16 N.C.
AE8 I/O
AC17 I/O
AE9 I/O
AC18 I/O
AE10 N.C.
AC19 I/O
AE11 I/O
AC20 VCC
AE12 I/O
AC21 N.C.
AE13 I/O
AC22 I/O
AE14 I/O
AC23 I (M2)
AE15 I/O
AC24 I/O, GCK2
AE16 I/O
AC25 N.C.
AE17 I/O
AC26 I/O
AE18 I/O
AB1 GND
AE19 I/O
AB2 I/O
AE20 I/O
AB3 N.C.
AE21 I/O
AB4 I/O
AE22 I/O
AB23 O (M1)
AE23 I/O (LDC)
AB24 I/O
AE24 I/O, GCK3
AB25 I/O
AE25 VCC
AB26 GND
AE26 GND
AA1 I/O
AD1 I/O
AA2 I/O
AD2 I/O (D7)
AA3 I/O

4-164 September 18, 1996 (Version 1.04)

 BG352 Pin XC4028EX/XL BG352 Pin XC4028EX/XL
AA4 I/O N1 GND
AA23 I/O N2 I/O (D3)
AA24 I/O N3 I/O
AA25 I/O N4 I/O (RS)
AA26 I/O N23 VCC
Y1 I/O N24 I/O
Y2 I/O N25 I/O
Y3 I/O (D6) N26 I/O
Y4 VCC M1 I/O
Y23 I/O M2 I/O
Y24 I/O M3 I/O
Y25 I/O M4 I/O
Y26 I/O M23 I/O
W1 GND M24 I/O
W2 I/O M25 I/O
W3 I/O M26 I/O
W4 I/O L1 I/O
W23 VCC L2 I/O
W24 I/O L3 I/O
W25 I/O L4 N.C.
W26 GND L23 N.C.
V1 I/O (CS0) L24 I/O
V2 I/O (D5) L25 I/O
V3 I/O L26 I/O
V4 I/O K1 VCC
V23 I/O K2 N.C.
V24 I/O K3 I/O
V25 I/O K4 I/O
V26 I/O K23 I/O
U1 VCC K24 I/O
U2 I/O K25 I/O
U3 I/O K26 VCC
U4 I/O, FCLK3 J1 I/O (D2)
U23 I/O, FCLK2 J2 I/O
U24 I/O J3 I/O, FCLK4
U25 N.C. J4 I/O
U26 VCC J23 I/O, FCLK1
T1 I/O J24 I/O
T2 I/O J25 I/O
T3 N.C. J26 N.C.
T4 N.C. H1 GND
T23 I/O H2 I/O
T24 N.C. H3 I/O
T25 I/O H4 VCC
T26 I/O H23 I/O
R1 I/O H24 I/O
R2 I/O H25 I/O, TMS
R3 I/O H26 GND
R4 I/O G1 I/O
R23 I/O G2 I/O
R24 I/O G3 I/O
R25 I/O G4 I/O (RCLK, RDY/BUSY)
R26 I/O G23 VCC
P1 I/O G24 I/O
P2 I/O (D4) G25 I/O
P3 I/O G26 I/O
P4 VCC F1 I/O
P23 I/O F2 I/O
P24 I/O F3 I/O (D1)
P25 I/O F4 I/O
P26 GND F23 N.C.

September 18, 1996 (Version 1.04) 4-165

XC4000 Series Field Programmable Gate Arrays

BG352 Pin XC4028EX/XL BG352 Pin XC4028EX/XL

F24 I/O C25 I/O (A17)
F25 I/O C26 I/O, TDI
F26 I/O B1 GND
E1 GND B2 VCC
E2 I/O B3 I/O (A0, WS)
E3 I/O B4 N.C.
E4 I/O, GCK6 (DOUT) B5 I/O
E23 I/O B6 I/O
E24 I/O, TCK B7 I/O
E25 I/O B8 I/O
E26 GND B9 I/O
D1 N.C. B10 N.C.
D2 I/O B11 I/O
D3 I/O (D0, DIN) B12 I/O
D4 O (TDO) B13 I/O (A20)
D5 I/O B14 I/O (A7)
D6 I/O (CS1, A2) B15 I/O (A18)
D7 VCC B16 I/O (A11)
D8 I/O B17 I/O
D9 I/O B18 I/O
D10 I/O B19 I/O
D11 I/O B20 I/O
D12 I/O (A4) B21 I/O
D13 VCC B22 I/O (A12)
D14 I/O (A8) B23 N.C.
D15 I/O B24 I/O
D16 N.C. B25 VCC
D17 I/O B26 GND
D18 I/O A1 GND
D19 VCC A2 GND
D20 I/O A3 I/O
D21 I/O A4 I/O
D22 I/O (A14) A5 GND
D23 I/O, GCK1 (A16) A6 I/O
D24 I/O A7 I/O
D25 N.C. A8 GND
D26 I/O A9 I/O
C1 N.C. A10 VCC
C2 I/O A11 I/O
C3 CCLK A12 I/O
C4 I/O, GCK7 (A1) A13 I/O (A6)
C5 N.C. A14 GND
C6 I/O (A3) A15 I/O (A19)
C7 I/O A16 I/O (A10)
C8 N.C. A17 VCC
C9 I/O A18 N.C.
C10 I/O A19 GND
C11 N.C. A20 I/O
C12 I/O (A5) A21 I/O
C13 I/O (A21) A22 GND
C14 I/O (A9) A23 I/O
C15 I/O A24 N.C.
C16 I/O A25 GND
C17 I/O A26 GND
C18 I/O
2/28/96
C19 I/O
C20 I/O Note: Viewed from the bottom side, the package pins start
C21 I/O (A13) at the top row and go from the left edge to the right edge.
C22 I/O Viewed from the top side, the pins start at the top row and
C23 I/O go from the right edge to the left edge.
C24 I/O, GCK8 (A15)

4-166 September 18, 1996 (Version 1.04)

PG411 Package Pinouts PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL
AU15 N.C. N.C. I/O
The following table may contain pinout information for
AU17 N.C. I/O I/O
unsupported device/package combinations. Please see the
AU19 I/O (D3) I/O (D3) I/O (D3)
availability charts elsewhere in the XC4000 Series data
sheet for availability information. AU21 I/O I/O I/O
AU23 I/O I/O I/O
PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL AU25 N.C. N.C. I/O
AW1 I/O I/O I/O AU27 I/O (CS0) I/O (CS0) I/O (CS0)
AW3 GND GND GND AU29 I/O I/O I/O
AW5 I/O I/O I/O AU31 I/O I/O I/O
AW7 I/O (RCLK, I/O (RCLK, I/O (RCLK, AU33 I/O I/O I/O
RDY/BUSY) RDY/BUSY) RDY/BUSY) AU35 I/O I/O I/O
AW9 VCC VCC VCC AU37 N.C. N.C. I/O
AW11 GND GND GND AU39 GND GND GND
AW13 I/O I/O I/O AT2 N.C. N.C. I/O
AW15 N.C. I/O I/O AT4 I/O (A0, WS) I/O (A0, WS) I/O (A0, WS)
AW17 I/O I/O I/O AT6 GND GND GND
AW19 VCC VCC VCC AT8 I/O I/O I/O
AW21 GND GND GND AT10 I/O I/O I/O
AW23 N.C. I/O I/O AT12 I/O I/O I/O
AW25 N.C. I/O I/O AT14 GND GND GND
AW27 I/O I/O I/O AT16 I/O I/O I/O
AW29 VCC VCC VCC AT18 I/O I/O I/O
AW31 GND GND GND AT20 GND GND GND
AW33 I/O I/O I/O AT22 I/O I/O I/O
AW35 N.C. N.C. I/O AT24 I/O I/O I/O
AW37 VCC VCC VCC AT26 GND GND GND
AW39 I/O I/O I/O AT28 I/O, FCLK3 I/O, FCLK3 I/O, FCLK3
AV2 I/O, GCK7 (A1) I/O, GCK7 (A1) I/O, GCK7 (A1) AT30 N.C. I/O I/O
AV4 I/O I/O I/O AT32 I/O I/O I/O
AV6 I/O I/O I/O AT34 VCC VCC VCC
AV8 N.C. I/O I/O AT36 I/O, GCK4 I/O, GCK4 I/O, GCK4
AV10 I/O I/O I/O AT38 I/O I/O I/O
AV12 I/O I/O I/O AR1 I/O I/O I/O
AV14 I/O I/O I/O AR3 I/O I/O I/O
AV16 I/O I/O I/O AR5 CCLK CCLK CCLK
AV18 I/O I/O I/O AR7 I/O I/O I/O
AV20 I/O (RS) I/O (RS) I/O (RS) AR9 I/O I/O I/O
AV22 I/O I/O I/O AR11 I/O I/O I/O
AV24 I/O I/O I/O AR13 I/O, FCLK4 I/O, FCLK4 I/O, FCLK4
AV26 N.C. N.C. I/O AR15 I/O (D2) I/O (D2) I/O (D2)
AV28 I/O I/O I/O AR17 I/O I/O I/O
AV30 I/O I/O I/O AR19 I/O I/O I/O
AV32 I/O (D6) I/O (D6) I/O (D6) AR21 I/O I/O I/O
AV34 N.C. N.C. I/O AR23 I/O I/O I/O
AV36 I/O I/O I/O AR25 I/O I/O I/O
AV38 I/O I/O I/O AR27 I/O I/O I/O
AU1 VCC VCC VCC AR29 I/O I/O I/O
AU3 I/O, GCK6 I/O, GCK6 I/O, GCK6 AR31 I/O I/O I/O
(DOUT) (DOUT) (DOUT)
AR33 I/O I/O I/O
AU5 N.C. N.C. I/O
AR35 DONE DONE DONE
AU7 I/O (D1) I/O (D1) I/O (D1)
AR37 N.C. N.C. I/O
AU9 N.C. I/O I/O
AR39 I/O I/O I/O
AU11 I/O I/O I/O
AP2 I/O I/O I/O
AU13 N.C. N.C. I/O
AP4 VCC VCC VCC

September 18, 1996 (Version 1.04) 4-167

XC4000 Series Field Programmable Gate Arrays

PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL
AP6 I/O (D0, DIN) I/O (D0, DIN) I/O (D0, DIN) AJ39 GND GND GND
AP8 N.C. N.C. I/O AH2 I/O I/O I/O
AP10 I/O I/O I/O AH4 I/O I/O I/O
AP12 I/O I/O I/O AH6 I/O I/O I/O
AP14 I/O I/O I/O AH34 I/O I/O I/O
AP16 I/O I/O I/O AH36 I/O I/O I/O
AP18 I/O I/O I/O AH38 I/O I/O I/O
AP20 I/O (D4) I/O (D4) I/O (D4) AG1 I/O I/O I/O
AP22 I/O I/O I/O AG3 I/O I/O I/O
AP24 I/O (D5) I/O (D5) I/O (D5) AG5 I/O I/O I/O
AP26 I/O I/O I/O AG35 I/O I/O I/O
AP28 I/O I/O I/O AG37 I/O I/O I/O
AP30 N.C. I/O I/O AG39 I/O I/O I/O
AP32 I/O I/O I/O AF2 N.C. N.C. I/O
AP34 I/O, GCK5 I/O, GCK5 I/O, GCK5 AF4 GND GND GND
AP36 GND GND GND AF6 I/O I/O I/O
AP38 N.C. I/O I/O AF34 I/O I/O I/O
AN1 N.C. I/O I/O AF36 GND GND GND
AN3 I/O (A3) I/O (A3) I/O (A3) AF38 N.C. N.C. I/O
AN5 N.C. N.C. I/O AE1 I/O I/O I/O
AN7 O, TDO O, TDO O, TDO AE3 I/O I/O I/O
AN9 I/O I/O I/O AE5 I/O I/O I/O
AN31 I/O I/O I/O AE35 I/O I/O I/O
AN33 PROGRAM PROGRAM PROGRAM AE37 I/O I/O I/O
AN35 I/O I/O I/O AE39 I/O I/O I/O
AN37 I/O I/O I/O AD2 I/O (A4) I/O (A4) I/O (A4)
AN39 I/O I/O I/O AD4 I/O (A21) I/O (A21) I/O (A21)
AM2 I/O I/O I/O AD6 I/O I/O I/O
AM4 I/O I/O I/O AD34 I/O I/O I/O
AM6 I/O I/O I/O AD36 I/O I/O I/O
AM8 I/O I/O I/O AD38 I/O I/O I/O
AM32 I/O (D7) I/O (D7) I/O (D7) AC1 I/O I/O I/O
AM34 I/O I/O I/O AC3 N.C. I/O I/O
AM36 I/O I/O I/O AC5 I/O I/O I/O
AM38 I/O I/O I/O AC35 I/O I/O I/O
AL1 GND GND GND AC37 I/O I/O I/O
AL3 I/O I/O I/O AC39 N.C. I/O I/O
AL5 I/O I/O I/O AB2 N.C. I/O I/O
AL7 I/O I/O I/O AB4 I/O (A5) I/O (A5) I/O (A5)
AL33 I/O I/O I/O AB6 I/O I/O I/O
AL35 N.C. N.C. I/O AB34 I/O I/O I/O
AL37 I/O I/O I/O AB36 I/O I/O I/O
AL39 VCC VCC VCC AB38 I/O I/O I/O
AK2 N.C. I/O I/O AA1 GND GND GND
AK4 I/O I/O I/O AA3 I/O (A6) I/O (A6) I/O (A6)
AK6 I/O (CS1, A2) I/O (CS1, A2) I/O (CS1, A2) AA5 I/O (A20) I/O (A20) I/O (A20)
AK34 I/O I/O I/O AA35 I/O I/O I/O
AK36 I/O I/O I/O AA37 N.C. I/O I/O
AK38 N.C. I/O I/O AA39 VCC VCC VCC
AJ1 VCC VCC VCC Y2 I/O (A9) I/O (A9) I/O (A9)
AJ3 I/O I/O I/O Y4 GND GND GND
AJ5 N.C. N.C. I/O Y6 I/O (A7) I/O (A7) I/O (A7)
AJ35 I/O I/O I/O Y34 I/O I/O I/O
AJ37 I/O I/O I/O Y36 GND GND GND

4-168 September 18, 1996 (Version 1.04)

PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL
Y38 N.C. I/O I/O L39 VCC VCC VCC
W1 VCC VCC VCC K2 I/O I/O I/O
W3 I/O (A8) I/O (A8) I/O (A8) K4 I/O I/O I/O
W5 N.C. I/O I/O K6 I/O I/O I/O
W35 N.C. I/O I/O K34 I/O I/O I/O
W37 I/O (INIT) I/O (INIT) I/O (INIT) K36 N.C. I/O I/O
W39 GND GND GND K38 N.C. I/O I/O
V2 N.C. I/O I/O J1 VCC VCC VCC
V4 I/O (A19) I/O (A19) I/O (A19) J3 I/O I/O I/O
V6 I/O I/O I/O J5 N.C. I/O I/O
V34 I/O I/O I/O J7 I/O I/O I/O
V36 I/O I/O I/O J33 I/O I/O I/O
V38 I/O I/O I/O J35 I/O I/O I/O
U1 I/O I/O I/O J37 I/O I/O I/O
U3 I/O (A10) I/O (A10) I/O (A10) J39 GND GND GND
U5 I/O I/O I/O H2 I/O I/O I/O
U35 I/O I/O I/O H4 I/O (A12) I/O (A12) I/O (A12)
U37 I/O I/O I/O H6 I/O I/O I/O
U39 I/O I/O I/O H8 I/O, GCK1 (A16) I/O, GCK1 (A16) I/O, GCK1 (A16)
T2 I/O (A18) I/O (A18) I/O (A18) H32 I/O I/O I/O
T4 I/O I/O I/O H34 N.C. N.C. I/O
T6 I/O I/O I/O H36 I/O I/O I/O
T34 I/O I/O I/O H38 I/O I/O I/O
T36 I/O I/O I/O G1 I/O I/O I/O
T38 I/O I/O I/O G3 I/O (A13) I/O (A13) I/O (A13)
R1 I/O (A11) I/O (A11) I/O (A11) G5 N.C. N.C. I/O
R3 N.C. N.C. I/O G7 I/O, GCK8 (A15) I/O, GCK8 (A15) I/O, GCK8 (A15)
R5 I/O I/O I/O G9 I/O, TCK I/O, TCK I/O, TCK
R35 I/O I/O I/O G31 I/O I/O I/O
R37 I/O I/O I/O G33 I (M2) I (M2) I (M2)
R39 I/O I/O I/O G35 I/O (LDC) I/O (LDC) I/O (LDC)
P2 I/O I/O I/O G37 I/O I/O I/O
P4 GND GND GND G39 I/O I/O I/O
P6 I/O I/O I/O F2 N.C. N.C. I/O
P34 I/O I/O I/O F4 GND GND GND
P36 GND GND GND F6 I/O (A17) i/O (A17) i/O (A17)
P38 N.C. N.C. I/O F8 I/O I/O I/O
N1 I/O I/O I/O F10 I/O I/O I/O
N3 N.C. N.C. I/O F12 I/O I/O I/O
N5 I/O I/O I/O F14 I/O I/O I/O
N35 I/O I/O I/O F16 I/O I/O I/O
N37 I/O I/O I/O F18 N.C. I/O I/O
N39 I/O I/O I/O F20 I/O I/O I/O
M2 I/O I/O I/O F22 N.C. I/O I/O
M4 I/O I/O I/O F24 I/O I/O I/O
M6 I/O I/O I/O F26 I/O I/O I/O
M34 I/O I/O I/O F28 I/O I/O I/O
M36 I/O I/O I/O F30 I/O I/O I/O
M38 I/O I/O I/O F32 I/O I/O I/O
L1 GND GND GND F34 I/O I/O I/O
L3 I/O I/O I/O F36 VCC VCC VCC
L5 N.C. I/O I/O F38 I/O I/O I/O
L35 N.C. N.C. I/O E1 I/O I/O I/O
L37 I/O I/O I/O E3 I/O I/O I/O

September 18, 1996 (Version 1.04) 4-169

XC4000 Series Field Programmable Gate Arrays

PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL PG411 Pin XC4036EX/XL XC4044EX/XL XC4052XL
E5 I/O (A14) I/O (A14) I/O (A14) C35 I/O I/O I/O
E7 N.C. N.C. I/O C37 I/O (HDC) I/O (HDC) I/O (HDC)
E9 I/O I/O I/O C39 VCC VCC VCC
E11 I/O, TMS I/O, TMS I/O, TMS B2 I/O, TDI I/O, TDI I/O, TDI
E13 I/O I/O I/O B4 I/O I/O I/O
E15 I/O I/O I/O B6 N.C. N.C. I/O
E17 I/O I/O I/O B8 I/O I/O I/O
E19 I/O I/O I/O B10 I/O I/O I/O
E21 I/O I/O I/O B12 I/O I/O I/O
E23 N.C. N.C. I/O B14 I/O I/O I/O
E25 I/O I/O I/O B16 I/O I/O I/O
E27 I/O I/O I/O B18 I/O I/O I/O
E29 I/O I/O I/O B20 I/O I/O I/O
E31 I/O I/O I/O B22 I/O I/O I/O
E33 I/O I/O I/O B24 I/O I/O I/O
E35 I (M0) I (M0) I (M0) B26 I/O I/O I/O
E37 N.C. N.C. I/O B28 I/O I/O I/O
E39 I/O I/O I/O B30 I/O I/O I/O
D2 I/O I/O I/O B32 I/O I/O I/O
D4 I/O I/O I/O B34 N.C. N.C. I/O
D6 VCC VCC VCC B36 I/O, GCK2 I/O, GCK2 I/O, GCK2
D8 N.C. I/O I/O B38 I/O I/O I/O
D10 I/O I/O I/O A3 VCC VCC VCC
D12 N.C. N.C. I/O A5 I/O I/O I/O
D14 GND GND GND A7 I/O I/O I/O
D16 I/O I/O I/O A9 GND GND GND
D18 I/O I/O I/O A11 VCC VCC VCC
D20 GND GND GND A13 N.C. N.C. I/O
D22 I/O I/O I/O A15 I/O I/O I/O
D24 I/O I/O I/O A17 I/O I/O I/O
D26 GND GND GND A19 GND GND GND
D28 I/O I/O I/O A21 VCC VCC VCC
D30 N.C. I/O I/O A23 I/O I/O I/O
D32 N.C. I/O I/O A25 I/O I/O I/O
D34 GND GND GND A27 I/O I/O I/O
D36 I/O, GCK3 I/O, GCK3 I/O, GCK3 A29 GND GND GND
D38 I/O I/O I/O A31 VCC VCC VCC
C1 GND GND GND A33 I/O I/O I/O
C3 I/O I/O I/O A35 I/O I/O I/O
C5 I/O I/O I/O A37 GND GND GND
C7 N.C. I/O I/O A39 O (M1) O (M1) O (M1)
C9 I/O I/O I/O
8/23/96
C11 I/O, FCLK1 I/O, FCLK1 I/O, FCLK1
C13 I/O I/O I/O Note: Shaded pins should be taken into account when de-
C15 N.C. I/O I/O signing PC boards, in case of future replacement by differ-
C17 I/O I/O I/O ent devices.
C19 I/O I/O I/O Note: Viewed from the bottom side, the package pins start
C21 I/O I/O I/O at the top row and go from the left edge to the right edge.
C23 N.C. I/O I/O Viewed from the top side, the pins start at the top row and
C25 N.C. N.C. I/O go from the right edge to the left edge.
C27 I/O I/O I/O
C29 I/O, FCLK2 I/O, FCLK2 I/O, FCLK2
C31 I/O I/O I/O
C33 N.C. N.C. I/O

4-170 September 18, 1996 (Version 1.04)

BG432 Package Pinouts BG432 Pin XC4036EX XC4044EX XC4052XL
XC4036XL XC4044XL
The following table may contain pinout information for AK21 I/O I/O I/O
unsupported device/package combinations. Please see the AK22 I/O I/O I/O
availability charts elsewhere in the XC4000 Series data AK23 I/O I/O I/O
sheet for availability information. AK24 N.C. I/O I/O
AK25 I/O I/O I/O
BG432 Pin XC4036EX XC4044EX XC4052XL
XC4036XL XC4044XL AK26 I/O I/O I/O
AL1 VCC VCC VCC AK27 N.C. N.C. I/O
AL2 GND GND GND AK28 I/O I/O I/O
AL3 GND GND GND AK29 I/O, GCK3 I/O, GCK3 I/O, GCK3
AL4 I/O I/O I/O AK30 GND GND GND
AL5 I/O I/O I/O AK31 GND GND GND
AL6 I/O I/O I/O AJ1 GND GND GND
AL7 GND GND GND AJ2 I/O (D7) I/O (D7) I/O (D7)
AL8 I/O I/O I/O AJ3 VCC VCC VCC
AL9 GND GND GND AJ4 I/O, GCK4 I/O, GCK4 I/O, GCK4
AL10 I/O I/O I/O AJ5 N.C. N.C. I/O
AL11 VCC VCC VCC AJ6 I/O I/O I/O
AL12 I/O I/O I/O AJ7 I/O I/O I/O
AL13 I/O I/O I/O AJ8 N.C. I/O I/O
AL14 GND GND GND AJ9 I/O I/O I/O
AL15 N.C. I/O I/O AJ10 I/O I/O I/O
AL16 I/O I/O I/O AJ11 I/O I/O I/O
AL17 N.C. I/O I/O AJ12 N.C. N.C. I/O
AL18 GND GND GND AJ13 I/O I/O I/O
AL19 I/O I/O I/O AJ14 I/O I/O I/O
AL20 I/O I/O I/O AJ15 N.C. I/O I/O
AL21 VCC VCC VCC AJ16 I/O I/O I/O
AL22 I/O I/O I/O AJ17 I/O I/O I/O
AL23 GND GND GND AJ18 I/O I/O I/O
AL24 I/O I/O I/O AJ19 I/O I/O I/O
AL25 GND GND GND AJ20 N.C. N.C. I/O
AL26 I/O I/O I/O AJ21 I/O I/O I/O
AL27 I/O I/O I/O AJ22 I/O I/O I/O
AL28 I/O I/O I/O AJ23 I/O I/O I/O
AL29 GND GND GND AJ24 I/O I/O I/O
AL30 GND GND GND AJ25 I/O I/O I/O
AL31 VCC VCC VCC AJ26 N.C. N.C. I/O
AK1 GND GND GND AJ27 I/O I/O I/O
AK2 GND GND GND AJ28 I (M2) I (M2) I (M2)
AK3 I/O I/O I/O AJ29 VCC VCC VCC
AK4 I/O I/O I/O AJ30 I/O, GCK2 I/O, GCK2 I/O, GCK2
AK5 I/O I/O I/O AJ31 GND GND GND
AK6 I/O I/O I/O AH1 I/O I/O I/O
AK7 I/O I/O I/O AH2 I/O I/O I/O
AK8 I/O I/O I/O AH3 PROGRAM PROGRAM PROGRAM
AK9 I/O I/O I/O AH4 DONE DONE DONE
AK10 I/O I/O I/O AH5 I/O I/O I/O
AK11 N.C. N.C. I/O AH6 N.C. N.C. I/O
AK12 I/O I/O I/O AH7 I/O I/O I/O
AK13 I/O I/O I/O AH8 I/O I/O I/O
AK14 I/0 I/O I/O AH9 N.C. I/O I/O
AK15 I/O I/O I/O AH10 I/O I/O I/O
AK16 I/O (INIT) I/O (INIT) I/O (INIT) AH11 VCC VCC VCC
AK17 N.C. I/O I/O AH12 I/O I/O I/O
AK18 I/O I/O I/O AH13 I/O I/O I/O
AK19 I/O I/O I/O AH14 I/O I/O I/O
AK20 I/O I/O I/O AH15 I/O I/O I/O

September 18, 1996 (Version 1.04) 4-171

XC4000 Series Field Programmable Gate Arrays

BG432 Pin XC4036EX XC4044EX XC4052XL BG432 Pin XC4036EX XC4044EX XC4052XL
XC4036XL XC4044XL XC4036XL XC4044XL
AH16 GND GND GND AB2 I/O I/O I/O
AH17 I/O I/O I/O AB3 I/O I/O I/O
AH18 I/O I/O I/O AB4 I/O I/O I/O
AH19 N.C. N.C. I/O AB28 I/O I/O I/O
AH20 I/O I/O I/O AB29 I/O, FCLK2 I/O, FCLK2 I/O, FCLK2
AH21 VCC VCC VCC AB30 I/O I/O I/O
AH22 I/O I/O I/O AB31 I/O I/O I/O
AH23 N.C. I/O I/O AA1 VCC VCC VCC
AH24 I/O I/O I/O AA2 I/O (D5) I/O (D5) I/O (D5)
AH25 I/O I/O I/O AA3 I/O I/O I/O
AH26 I/O (LDC) I/O (LDC) I/O (LDC) AA4 VCC VCC VCC
AH27 I/O (HDC) I/O (HDC) I/O (HDC) AA28 VCC VCC VCC
AH28 I (M0) I (M0) I (M0) AA29 I/O I/O I/O
AH29 O (M1) O (M1) O (M1) AA30 I/O I/O I/O
AH30 I/O I/O I/O AA31 VCC VCC VCC
AH31 I/O I/O I/O Y1 N.C. N.C. I/O
AG1 N.C. N.C. I/O Y2 I/O (CS0) I/O (CS0) I/O (CS0)
AG2 I/O I/O I/O Y3 I/O I/O I/O
AG3 I/O I/O I/O Y4 I/O I/O I/O
AG4 I/O, GCK5 I/O, GCK5 I/O, GCK5 Y28 I/O I/O I/O
AG28 I/O I/O I/O Y29 I/O I/O I/O
AG29 I/O I/O I/O Y30 I/O I/O I/O
AG30 I/O I/O I/O Y31 N.C. N.C. I/O
AG31 I/O I/O I/O W1 N.C. N.C. I/O
AF1 I/O (D6) I/O (D6) I/O (D6) W2 N.C. I/O I/O
AF2 I/O I/O I/O W3 I/O I/O I/O
AF3 I/O I/O I/O W4 I/O I/O I/O
AF4 I/O I/O I/O W28 N.C. N.C. I/O
AF28 I/O I/O I/O W29 I/O I/O I/O
AF29 N.C. N.C. I/O W30 I/O I/O I/O
AF30 N.C. N.C. I/O W31 N.C. I/O I/O
AF31 I/O I/O I/O V1 GND GND GND
AE1 GND GND GND V2 N.C. I/O I/O
AE2 I/O I/O I/O V3 I/O I/O I/O
AE3 I/O I/O I/O V4 I/O I/O I/O
AE4 N.C. N.C. I/O V28 N.C. I/O I/O
AE28 I/O I/O I/O V29 I/O I/O I/O
AE29 I/O I/O I/O V30 I/O I/O I/O
AE30 I/O I/O I/O V31 GND GND GND
AE31 GND GND GND U1 I/O I/O I/O
AD1 I/O I/O I/O U2 I/O I/O I/O
AD2 N.C. I/O I/O U3 I/O I/O I/O
AD3 I/O I/O I/O U4 I/O I/O I/O
AD4 I/O I/O I/O U28 I/O I/O I/O
AD28 I/O I/O I/O U29 I/O I/O I/O
AD29 I/O I/O I/O U30 I/O I/O I/O
AD30 N.C. I/O I/O U31 I/O I/O I/O
AD31 N.C. I/O I/O T1 I/O (D4) I/O (D4) I/O (D4)
AC1 GND GND GND T2 I/O I/O I/O
AC2 I/O I/O I/O T3 I/O (D3) I/O (D3) I/O (D3)
AC3 I/O I/O I/O T4 GND GND GND
AC4 N.C. I/O I/O T28 GND GND GND
AC28 I/O I/O I/O T29 I/O I/O I/O
AC29 I/O I/O I/O T30 I/O I/O I/O
AC30 I/O I/O I/O T31 I/O I/O I/O
AC31 GND GND GND R1 I/O (RS) I/O (RS) I/O (RS)
AB1 I/O, FCLK3 I/O, FCLK3 I/O, FCLK3 R2 I/O I/O I/O

4-172 September 18, 1996 (Version 1.04)

BG432 Pin XC4036EX XC4044EX XC4052XL BG432 Pin XC4036EX XC4044EX XC4052XL
XC4036XL XC4044XL XC4036XL XC4044XL
R3 I/O I/O I/O H4 I/O I/O I/O
R4 I/O I/O I/O H28 I/O I/O I/O
R28 I/O I/O I/O H29 I/O I/O I/O
R29 I/O I/O I/O H30 I/O I/O I/O
R30 I/O I/O I/O H31 I/O I/O I/O
R31 I/O I/O I/O G1 GND GND GND
P1 GND GND GND G2 I/O I/O I/O
P2 I/O I/O I/O G3 N.C. I/O I/O
P3 I/O I/O I/O G4 I/O (D1) I/O (D1) I/O (D1)
P4 I/O I/O I/O G28 I/O I/O I/O
P28 I/O I/O I/O G29 I/O I/O I/O
P29 I/O I/O I/O G30 I/O I/O I/O
P30 I/O I/O I/O G31 GND GND GND
P31 GND GND GND F1 N.C. I/O I/O
N1 N.C. I/O I/O F2 I/O (RCLK, I/O (RCLK, I/O (RCLK,
N2 N.C. I/O I/O RDY/BUSY) RDY/BUSY) RDY/BUSY)
N3 I/O I/O I/O F3 I/O I/O I/O
N4 I/O I/O I/O F4 N.C. N.C. I/O
N28 I/O I/O I/O F28 N.C. N.C. I/O
N29 N.C. I/O I/O F29 N.C. N.C. I/O
N30 N.C. I/O I/O F30 N.C. I/O I/O
N31 I/O I/O I/O F31 N.C. I/O I/O
M1 I/O I/O I/O E1 I/O I/O I/O
M2 I/O I/O I/O E2 N.C. N.C. I/O
M3 N.C. N.C. I/O E3 I/O I/O I/O
M4 N.C. N.C. I/O E4 I/O I/O I/O
M28 N.C. N.C. I/O E28 I/O I/O I/O
M29 I/O I/O I/O E29 I/O I/O I/O
M30 N.C. N.C. I/O E30 I/O I/O I/O
M31 I/O I/O I/O E31 I/O I/O I/O
L1 VCC VCC VCC D1 I/O I/O I/O
L2 I/O (D2) I/O (D2) I/O (D2) D2 I/O I/O I/O
L3 I/O I/O I/O D3 I/O, GCK6 I/O, GCK6 I/O, GCK6
L4 VCC VCC VCC (DOUT) (DOUT) (DOUT)
L28 VCC VCC VCC D4 CCLK CCLK CCLK
L29 I/O I/O I/O D5 I/O, GCK7 (A1) I/O, GCK7 (A1) I/O, GCK7 (A1)
L30 I/O I/O I/O D6 N.C. N.C. I/O
L31 VCC VCC VCC D7 I/O (A3) I/O (A3) I/O (A3)
K1 I/O I/O I/O D8 I/O I/O I/O
K2 I/O, FCLK4 I/O, FCLK4 I/O, FCLK4 D9 I/O I/O I/O
K3 I/O I/O I/O D10 I/O I/O I/O
K4 I/O I/O I/O D11 VCC VCC VCC
K28 I/O, FCLK1 I/O, FCLK1 I/O, FCLK1 D12 I/O I/O I/O
K29 I/O I/O I/O D13 N.C. N.C. I/O
K30 I/O, TMS I/O, TMS I/O, TMS D14 I/O I/O I/O
K31 I/O I/O I/O D15 I/O I/O I/O
J1 GND GND GND D16 GND GND GND
J2 I/O I/O I/O D17 I/O (A8) I/O (A8) I/O (A8)
J3 I/O I/O I/O D18 I/O (A18) I/O (A18) I/O (A18)
J4 I/O I/O I/O D19 I/O I/O I/O
J28 I/O I/O I/O D20 N.C. N.C. I/O
J29 I/O I/O I/O D21 VCC VCC VCC
J30 I/O I/O I/O D22 I/O I/O I/O
J31 GND GND GND D23 N.C. I/O I/O
H1 I/O I/O I/O D24 I/O (A12) I/O (A12) I/O (A12)
H2 I/O I/O I/O D25 I/O I/O I/O
H3 I/O I/O I/O D26 N.C. N.C. I/O

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XC4000 Series Field Programmable Gate Arrays

BG432 Pin XC4036EX XC4044EX XC4052XL BG432 Pin XC4036EX XC4044EX XC4052XL
XC4036XL XC4044XL XC4036XL XC4044XL
D27 I/O I/O I/O B20 I/O I/O I/O
D28 I/O, GCK8 (A15) I/O, GCK8 (A15) I/O, GCK8 (A15) B21 N.C. N.C. I/O
D29 I/O, GCK1 (A16) I/O, GCK1 (A16) I/O, GCK1 (A16) B22 I/O I/O I/O
D30 I/O, TDI I/O, TDI I/O, TDI B23 I/O I/O I/O
D31 I/O, TCK I/O, TCK I/O, TCK B24 I/O I/O I/O
C1 GND GND GND B25 N.C. I/O I/O
C2 I/O (D0, DIN) I/O (D0, DIN) I/O (D0, DIN) B26 I/O (A13) I/O (A13) I/O (A13)
C3 VCC VCC VCC B27 I/O I/O I/O
C4 O, TDO O, TDO O, TDO B28 I/O I/O I/O
C5 I/O I/O I/O B29 I/O I/O I/O
C6 I/O I/O I/O B30 GND GND GND
C7 I/O I/O I/O B31 GND GND GND
C8 N.C. N.C. N.C. A1 VCC VCC VCC
C9 I/O I/O I/O A2 GND GND GND
C10 I/O I/O I/O A3 GND GND GND
C11 I/O I/O I/O A4 N.C. N.C. I/O
C12 I/O I/O I/O A5 I/O (CS1, A2) I/O (CS1, A2) I/O (CS1, A2)
C13 I/O I/O I/O A6 I/O I/O I/O
C14 I/O (A4) I/O (A4) I/O (A4) A7 GND GND GND
C15 I/O (A21) I/O (A21) I/O (A21) A8 N.C. I/O I/O
C16 N.C. I/O I/O A9 GND GND GND
C17 N.C. I/O I/O A10 I/O I/O I/O
C18 I/O (A19) I/O (A19) I/O (A19) A11 VCC VCC VCC
C19 I/O (A11) I/O (A11) I/O (A11) A12 I/O I/O I/O
C20 I/O I/O I/O A13 I/O (A5) I/O (A5) I/O (A5)
C21 I/O I/O I/O A14 GND GND GND
C22 I/O I/O I/O A15 N.C. I/O I/O
C23 I/O I/O I/O A16 I/O (A7) I/O (A7) I/O (A7)
C24 I/O I/O I/O A17 I/O (A9) I/O (A9) I/O (A9)
C25 I/O I/O I/O A18 GND GND GND
C26 I/O I/O I/O A19 I/O I/O I/O
C27 I/O I/O I/O A20 I/O I/O I/O
C28 I/O (A14) I/O (A14) I/O (A14) A21 VCC VCC VCC
C29 VCC VCC VCC A22 I/O I/O I/O
C30 I/O (A17) I/O (A17) I/O (A17) A23 GND GND GND
C31 GND GND GND A24 I/O I/O I/O
B1 GND GND GND A25 GND GND GND
B2 GND GND GND A26 I/O I/O I/O
B3 I/O (A0, WS) I/O (A0, WS) I/O (A0, WS) A27 I/O I/O I/O
B4 I/O I/O I/O A28 N.C. N.C. I/O
B5 I/O I/O I/O A29 GND GND GND
B6 I/O I/O I/O A30 GND GND GND
B7 I/O I/O I/O A31 VCC VCC VCC
B8 N.C. I/O I/O 3/26/96
B9 I/O I/O I/O
B10 I/O I/O I/O Note: Shaded pins should be taken into account when de-
B11 I/O I/O I/O signing PC boards, in case of future replacement by differ-
B12 N.C. N.C. I/O ent devices.
B13 I/O I/O I/O
B14 I/O I/O I/O Note: Viewed from the bottom side, the package pins start
B15 I/O (A20) I/O (A20) I/O (A20) at the top row and go from the left edge to the right edge.
B16 I/O (A6) I/O (A6) I/O (A6) Viewed from the top side, the pins start at the top row and
B17 N.C. I/O I/O go from the right edge to the left edge.
B18 I/O I/O I/O
B19 I/O (A10) I/O (A10) I/O (A10)

4-174 September 18, 1996 (Version 1.04)

Product Availability
Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales office
for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the
specifications.
Table 25: Component Availability Chart for XC4000E FPGAs

Speed PC PQ VQ PG TQ PG PQ CB PG CB PQ HQ PG BG CB PQ HQ PG HQ
Grade 84 100 100 120 144 156 160 164 191 196 208 208 223 225 228 240 240 299 304
XC -4 CI CI CI CI
4003E -3 CI CI CI CI
-2 C C C C
-4 CI CI CI CI CI MB CI
XC MB
4005E
-3 CI CI CI CI CI CI
-2 C C C C C C
XC -4 CI CI CI CI CI
4006E -3 CI CI CI CI CI
-2 C C C C C
XC -4 CI CI CI CI
4008E -3 CI CI CI CI
-2 C C C C
-4 CI CI C I MB CI CI CI
XC MB
4010E -3 CI CI CI CI CI CI
-2 C C C C C C
-4 CI CI CI CI CI MB CI CI
XC MB
4013E -3 CI CI CI CI CI CI CI
-2 C C C C C C C
-4 CI CI CI
XC
-3 CI CI CI
4020E
-2 C C C
-4 CI MB CI CI CI
XC MB
4025E -3 CI CI CI CI
-2 C C C C

C = Commercial, TJ = 0° to +85° C
I = Industrial, TJ = -40° to +100° C
M = Mil Temp, TC = -55° to +125° C
B = MIL-STD-883C Class B, TC = -55° to +125° C
Shaded device/package combinations are not supported.

September 18, 1996 (Version 1.04) 4-175

XC4000 Series Field Programmable Gate Arrays

Table 26: Component Availability Chart for XC4000EX FPGAs

Speed
HQ208 HQ240 PG299 HQ304 BG352 PG411 BG432
Grade
-4 CI CI CI CI CI
XC4028EX -3 C C C C C

-4 CI CI CI
XC4036EX -3 C C C

-4 CI CI
XC4044EX -3 C C

C = Commercial, TJ = 0° to +85° C
I = Industrial, TJ = -40° to +100° C
M = Mil Temp, TC = -55° to +125° C
B = MIL-STD-883C Class B, TC = -55° to +125° C
Shaded device/package combinations are not supported.
Table 27: Component Availability Chart for XC4000L and XC4000XL FPGAs

Speed PC TQ PQ HQ BG PQ HQ PG HQ BG PG BG PG
Grade 84 176 208 208 225 240 240 299 304 352 411 432 475
-6 C C
XC4005L -5 C C
-4
-6 C C C
XC4010L -5 C C C
-4
-6 C C C
XC4013L -5 C C C
-4
C C C C C
XC4028XL

C C C
XC4036XL

C C
XC4044XL

C C
XC4052XL

C
XC4062XL

C = Commercial, TJ = 0° to +85° C
I = Industrial, TJ = -40° to +100° C
M = Mil Temp, TC = -55° to +125° C
B = MIL-STD-883C Class B, TC = -55° to +125° C
Shaded device/package combinations are not supported.
Speed grades for the XC4000XL have not yet been determined.

4-176 September 18, 1996 (Version 1.04)

User I/O Per Package
Maximum available user I/O for each device/package combination is shown in Table 28 - Table 30.
Pinout tables for XC4000-Series devices follow. Pinout data is offered in two forms, as device-specific and package-specific
tables. Device-specific tables include all packages for each XC4000-Series device. They follow the pad locations around
the die, and include boundary scan register locations. Package-specific tables include all XC4000-Series devices available
in a given package. These tables are especially useful in determining which pads should be avoided, in case of a future
transition to a different device in the same package.
All pinouts defined at the time of publication are included in these tables. Additional information may be available. Call your
local sales office or see the Xilinx WEBLINX at http://www.xilinx.com for the latest information.
Table 28: Maximum User I/O for XC4000E Device/Package Combinations

No. of Package
XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E
Pins (Code)
Maximum User I/O 80 112 128 144 160 192 224 256
84 PLCC (PC) 61 61 61 61 61
100 PQFP (PQ) 77 77
VQFP (VQ) 77
120 PGA (PG) 80
144 TQFP (TQ) 112 113
156 PGA (PG) 112 125
160 PQFP (PQ) 112 128 129 129 129
164 CBFP (CB) 112
191 PGA (PG) 144 160
196 CBFP (CB) 160
208 PQFP (PQ) 112 128 144 160 160
HQFP (HQ) 160 160 160
223 PGA (PG) 192 192 192
225 BGA (BG) 160 192
228 CBFP (CB) 192 192
240 PQFP (PQ) 192
HQFP (HQ) 192 192 193
299 PGA (PG) 256
304 HQFP (HQ) 256

Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as
user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be
used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special
library symbols. The XACT software does not use them by default. (See Table 18 on page 47.)

September 18, 1996 (Version 1.04) 4-177

XC4000 Series Field Programmable Gate Arrays

Table 29: Maximum User I/O for XC4000EX Device/Package Combinations

No. of Pins Package (Code) XC4028EX XC4036EX XC4044EX

Maximum User I/O 256 288 320
208 HQFP (HQ) 160
240 HQFP (HQ) 193
299 PGA (PG) 256
304 HQFP (HQ) 256 256
352 BGA (BG) 256
411 PGA (PG) 288 320
432 BGA (BG) 288 320
Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as
user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be
used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special
library symbols. The XACT software does not use them by default. (See Table 18 on page 47.)

Table 30: Maximum User I/O for XC4000L and XC4000XL Device/Package Combinations

No. of Package
XC4005L XC4010L XC4013L XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL
Pins (Code)
Maximum User I/O 112 160 192 256 288 320 352 384
84 PLCC (PC) 61 61
176 TQFP (TQ) 153
208 PQFP (PQ) 112 160 160
208 HQFP (HQ) 160
225 BGA (BG) 192
240 PQFP (PQ) 192
240 HQFP (HQ) 193
299 PGA (PG) 256
304 HQFP (HQ) 256 256
352 BGA (BG) 256
411 PGA (PG) 288 320 352
432 BGA (BG) 288 320 352
475 PGA (PG) 384
Note: This table includes standard user-programmable I/O. It also includes the TDI, TCK, and TMS pins, which can function as
user-programmable I/O if not used for boundary scan. In addition to the I/O listed in this table, the M0 and M2 pins can be
used as inputs only; the M1 and TDO pins can be used as outputs only. All of these pins must be called out using special
library symbols. The XACT software does not use them by default. (See Table 18 on page 47.)

4-178 September 18, 1996 (Version 1.04)

Ordering Information

Example: XC4013E-3HQ240C

Device Type
Temperature Range
Speed Grade C = Commercial (TJ = 0 to +85°C)
-6 I = Industrial (TJ = -40 to +100°C)
-5 M = Military (TC = -55 to+125°C)
-4
-3 Number of Pins
-2

Package Type
PC = Plastic Lead Chip Carrier BG = Ball Grid Array
PQ = Plastic Quad Flat Pack PG = Ceramic Pin Grid Array
VQ = Very Thin Quad Flat Pack HQ = High Heat Dissipation Quad Flat Pack
TQ = Thin Quad Flat Pack MQ = Metal Quad Flat Pack
CB = Top Brazed Ceramic Quad Flat Pack

X6750

September 18, 1996 (Version 1.04) 4-179