Microelectronic

Circuits
Differential Amplifier
BITS Pilani Anu Gupta
Pilani Campus
 BITS Pilani
Pilani Campus

Differential Amplifier
Cascode amp with current bias---
capacitor???

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Remove capacitor, but no loss of
gain. How ???

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Differential input no capacitor
reqd.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Converting single input to
differential input

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Alternative simple method
Using a pair of OPAMP

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Alternative simple method
More error

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 BITS Pilani
Pilani Campus

Diff. Amp. --- more than CSA

Diff. amplifier
Benefits
• Same input magnitude, full voltage gain, no capacitor
• Input noise immunity (common mode operation)
• Double voltage swing
• Less harmonic distortion
• Flexibility in choosing phase of output

Drawback
• Diff. input required
• Double the no. of component
• Double power consumption ( not necessarily???)

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Input notation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Differential amplifier—
Double output signal swing

Extra node available

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Output signal swing-- doubles

vo1
2.8v 1.2v 3v

Vcm=1.6v
0.4v
vo2
vcm

1.2v

Vo1-vo2
2.4 v

Assume all overdrive 0.2v

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Differential amplifier---
2 Modes of operation

• Differential mode operation---gain

• Common mode operation– Noise immunity

𝒗𝟏 + 𝒗𝟐
𝒗𝒐𝒖𝒕 = 𝑨𝒅𝒎 𝒗𝟏 − 𝒗𝟐 + 𝑨𝒄𝒎
𝟐

BITS Pilani, Pilani Campus

 Diff operation—
No Even-Order Harmonic Distortion
• Expanding the transfer functions of circuits into a power series is a typical
way to quantify the distortion products.
• Taking a generic expansion of the outputs and assuming matched
amplifiers, we get:
Vout - = f(vin) = k1Vin + k2Vin2 + k3Vin3 + . . . , and
Vout+ = f(-vin) = k1(–Vin)+ k2(–Vin)2 + k3(–Vin)3 + . . . .

• Taking the differential output

Vod = 2k1Vin + 2k3Vin3 + . . . ,
where k1, k2 and k3 are constants.
• The quadratic terms gives rise to second-order harmonic distortion, the
cubic terms gives rise to third-order harmonic distortion, and so on.
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Diff amp
CSA-CSA coupled at source

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff amp.---
CSA, CDA-CGA in cascade

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Understanding of Diff Amp.—

• DC Bias,
• AC operation- Adm, Acm
• Large signal characteristics,
 BITS Pilani
Pilani Campus

DC Bias
 BITS Pilani
Pilani Campus

DC bias----
Differential Power Supply
Single Power Supply
Dual Power Supply
DC Bias

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Single Power Supply
DC Bias

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 BITS Pilani
Pilani Campus

AC Operation:
Difference mode
Common mode operation
Difference mode- AC
operation

• Rin, Rout

• Adm

• Output Signal swing

• CMRR

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AC Analysis using Half circuit
concept

Vin/2 Vin/2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Notations, Diff. amp voltage gain—
Differential Mode

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Notations
Half circuit transconductance,
𝒊𝒐𝟏
𝒈𝒎𝟏 = 𝑮𝒎,𝑯𝑪 =
𝒗𝒊𝒏𝟏
Differential input, single ended output Transconductance---
𝒊𝒐𝟏,𝟐
𝑮𝒎𝟏,𝒗𝒊𝒅 = 𝑮𝒎,𝒗𝒊𝒅 =
𝒗𝒊𝒅
Differential input, Differential output Transconductance-
±(𝒊𝒐𝟏 − 𝒊𝒐𝟐 ) 𝒊𝒐𝒅
𝑮𝒎,𝒅𝒊𝒇𝒇 = =
𝒗𝒊𝒅 𝒗𝒊𝒅
Differential input, single ended output, output conductance---
𝒗 𝒗
𝑹𝒐𝒖𝒕,𝑯𝑪 = 𝒐𝟏 = 𝒐𝟐
𝒊𝒐𝟏 𝒊𝒐𝟐
Differential input, Differential output, output conductance- -
𝒗𝒐𝒅 𝟐𝒗𝒐𝟏
𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 = =
𝒊𝒐𝒅 𝟐𝒊𝒐𝟏

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Rin/ Rout

Source degeneration is not required as Rin is

already high
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R out – Vx/ Ix

𝒗𝒙
𝑹𝒐𝒖𝒕 =
𝒊𝒙

𝑹𝒐𝒖𝒕 = 𝟐 𝒓𝒐 ||𝑹𝑫

𝒗𝒙𝟏− 𝒗𝒙𝟐 𝒗𝒙
𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 = = = 𝒓𝒐 ||𝑹𝑫
𝒊𝒙 − −𝒊𝒙 𝟐𝒊𝒙
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R out = [vx/ ix ]
using principle of superposition
𝑣𝑥
𝑅𝑜 =
𝑖𝑥
𝑣𝑥1
𝑅𝑜,𝑣𝑥1 = = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1

𝑣𝑥2
𝑅𝑜,𝑣𝑥2 = = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥2

𝑅𝑜𝑢𝑡 = 𝑅𝑜,𝑣𝑥1 + 𝑅𝑜,𝑣𝑥2

= 𝑅𝐷 ||𝑟𝑜 + 𝑅𝐷 ||𝑟𝑜

𝑹𝒐𝒖𝒕 = 2 𝑹𝑫 ||𝒓𝒐
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R out,diff, = [vod/ iod ]
using principle of superposition
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑥1 −𝑣𝑥2 𝑣𝑥1 𝑣𝑥2
= = −
𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2

𝑣𝑥1 𝑣𝑥2
𝑅𝑜,𝑑𝑖𝑓𝑓 = +
2𝑖𝑥1 2𝑖𝑥2
𝑣𝑥1 𝑣𝑥2
= 𝑅𝐷 ||𝑟𝑜 ; = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1 𝑖𝑥2
𝑖𝑥1 = −𝑖𝑥2 1 1
𝑅𝑜,𝑑𝑖𝑓𝑓 = 𝑅𝐷 ||𝑟𝑜 + 𝑅𝐷 ||𝑟𝑜
2 2
𝑹𝒐,𝒅𝒊𝒇𝒇 = 𝑹𝑫 ||𝒓𝒐
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BJT diff. amp ---Rin/ Rout

𝑅𝑖𝑛 = 2𝑟𝜋 ,

𝑹𝒐𝒖𝒕 = 𝟐 𝒓𝒐 ||𝑹𝒄

𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 = 𝒓𝒐 ||𝑹𝒄

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Rin, of BJT
(Using principle of superposition)

𝑅𝑖𝑛,𝑑𝑖𝑓𝑓 = 𝑅𝑖𝑛1 + 𝑅𝑖𝑛2

𝑖𝑖𝑛1 = −𝑖𝑖𝑛2 = 𝑖𝑖𝑛

𝑣𝑖𝑑 𝑣𝑖𝑛1 −|𝑣𝑖𝑛2 |

𝑅𝑖𝑛,𝑑𝑖𝑓𝑓 = = − == 𝑟𝜋1 + 𝑟𝜋1
𝑖𝑖𝑛 𝑖𝑖𝑛1 𝑖𝑖𝑛2
𝑅𝑖𝑛,𝑑𝑖𝑓𝑓 = 2𝑟𝜋1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 With Emitter degeneration resistor

High Rin with emitter degeneration

But gain reduces

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Difference mode– AC voltage gain

Input applied differentially

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Adm----Analysis using Half circuit

Vin/2 Vin/2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Benefit of half circuit concept

• Half circuit analysis can give the full Adm value directly

----------------------------------------------
• Diff amp gain = CSA gain only if we use double 2 vin, 2
Iss

NOTE----
• Diff amp gain is half/ Less if vid = vin
• Diff amp gain is half/ less if total bias current = Iss
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Adm using (G m diff x R out,diff )
G m diff - principle of superposition

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(G m diff
-- principle of superposition

𝑖𝑜,𝑑𝑖𝑓𝑓 𝑖𝑜1 − 𝑖𝑜2 𝑖𝑜1 𝑖𝑜2

𝐺𝑚,𝑑𝑖𝑓𝑓 = = = −
𝑣𝑖𝑑 𝑣𝑖𝑑 𝑣𝑖𝑑 𝑣𝑖𝑑
𝑖𝑜1 𝑖𝑜2 𝑔𝑚1 𝑣𝑖𝑛1 −𝑔𝑚2 𝑣𝑖𝑛2
𝐺𝑚,𝑑𝑖𝑓𝑓 = − = −
2𝑣𝑖𝑛1 2𝑣𝑖𝑛2 𝑣𝑖𝑑 𝑣𝑖𝑑
𝟐𝒈𝒎𝟏 𝒗𝒊𝒏𝟏
𝑮𝒎,𝒅𝒊𝒇𝒇 = = 𝒈𝒎𝟏 = 𝒈𝒎
𝟐𝒗𝒊𝒏𝟏

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

R out,diff, = [vod/ iod ]
using principle of superposition
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑥1 −𝑣𝑥2 𝑣𝑥1 𝑣𝑥2
= = −
𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2

𝑣𝑥1 𝑣𝑥2
𝑅𝑜,𝑑𝑖𝑓𝑓 = +
2𝑖𝑥1 2𝑖𝑥2
𝑣𝑥1 𝑣𝑥2
= 𝑅𝐷 ||𝑟𝑜 ; = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1 𝑖𝑥2
1 1
𝑅𝑜,𝑑𝑖𝑓𝑓 = 𝑅𝐷 ||𝑟𝑜 + 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1 = −𝑖𝑥2 = 𝑖𝑥 2 2
𝑹𝒐,𝒅𝒊𝒇𝒇 = 𝑹𝑫 ||𝒓𝒐
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Adm using
(G m diff x R out,diff )

𝑮𝒎,𝒅𝒊𝒇𝒇 = ∓𝒈𝒎𝟏,𝟐 = ∓𝒈𝒎

𝑨𝒅𝒎,𝒅𝒊𝒇𝒇 = ∓𝑮𝒎,𝒅𝒊𝒇𝒇 × 𝑹𝒐,𝒅𝒊𝒇𝒇

= ∓ 𝒈𝒎 𝑹𝑫 ||𝒓𝒐

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Acm-- Common Mode Gain–

using half circuit
AC common mode gain,
single ended output

Common
mode
Vod ≠ 0

for perfect
symmetry

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Common mode single ended gain
Half circuit concept

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

AC common mode gain,
differential output

Common
mode
differential
gain= 0

for perfect
symmetry

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rin/ Rout– common mode gain
Single ended output

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Common mode—
Output signal swing

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Common mode (active load)—
Output signal swing

𝑽𝒐,𝒎𝒂𝒙 = 𝑽𝑫𝑫 − 𝑽𝒐𝒗

𝑽𝒐,𝒎𝒊𝒏 = 𝑽𝒐𝒗𝟏 + 𝑽𝒐𝒗,𝑰𝒔𝒔

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 BITS Pilani
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Common Mode Rejection Ratio

CMRR
Common mode rejection ratio
CMRR
CMRR= |Adm/ Acm|; figure of merit

Ability to reject common signal

For diff output----

Acm=0;
CMRR→∞ ideal case

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Common mode rejection ratio
- single ended output
CMRR= |Adm| / |Acm|;

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 BITS Pilani
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Gain Comparison---
CSA gain , Diff . amp gain
CSA gain

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Differential Amp.--- Half circuit

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Diff amp gain-- Differential Mode
contd.

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Diff. amp gain-- using Gm, Rout

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Diff. amp gain-- Gm,diff, Rout,diff

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Diff. Amp voltage gain--
Common mode

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Diff. Amp voltage gain--
Common mode

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Summary

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Conclusion--

• Diff amp gain = CSA gain only if we use double resources i.e
----double input (vid = 2vin) and
-----double total bias current (2 Iss) , and
------2 matched arm.
• Half circuit analysis can give the full Adm value directly
----------------------------------------------------------------------
• NOTE----
• Diff amp gain is half/ Less if vid = vin
• Diff amp gain is half/ less if total bias current = Iss

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PMOS input differential pair

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 BITS Pilani
Pilani Campus

Large signal Characteristics

Extreme voltage/ current limits
for proper operation
1) Common mode characteristics----OCMR, ICMR
2) Differential characteristics
Single/ Diff vout vs. Diff. vin

Single/ Diff Iout vs. Diff. Vin

Gm diff . vs. diff vin

Single vout vs. single vin

Single Iout vs. single vin

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 BITS Pilani
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ICMR, OCMR
ICMR, OCMR

Input Common Mode Range

Range of possible common mode (DC) voltages at input

terminal

Output Common Mode Range

Range of possible DC voltages at output terminal

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Difference in OCMR, and
Output signal swing
• Are these same??---- NO

• OCMR (DC voltages) , common mode voltage

• Output signal swing (AC peak voltages), common/ differential

mode voltage

• Total Vout = DC Voltage + AC peak voltage

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Ex1--- ICMR, OCMR, O/P swing

ICMR

OCMR

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 Ex2---- OCMR, Output signal swing

They may be same, may not be same

OCMR

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Ex3– Identical OCMR, O/ P signal
swing

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Ex4– Different OCMR, O/ P signal
swing

𝑶𝑪𝑴𝑹 → 𝑽𝑫𝑫 − |𝑽𝑮𝑺𝟑 |

Fixed value

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Example

𝑽𝑫𝑫 = 𝟒𝑽, |𝑽𝑮𝑺𝟑 | = 𝟏. 𝟓𝑽, 𝑽𝑻 = 𝟏𝑽,

𝑽𝑶𝑽 = 𝟎. 𝟓𝑽

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Ex-- PMOS DIFF. AMP

Output signal swing—

2 [(Vdd – Vov3- Vov2 to Vov3 ]

vout

ICMR
Input common mode range-
[Vdd – Vov3 - Vsg2] to [Vov2 + Vov4- Vsg2]
;Vov2=|Vsg2|- |Vtp2|
Output common mode range–
[(Vdd – Vov5- Vov2 to Vov3 ] range here
 Ex- 5

Input common mode

range-
[(Vdd – Vov3) + Vgs1] to
[Vgs1 + Vov5]

Output common mode range–

[(Vdd – Vov4 to
Vov5 + Vov1 ] range here
 Ex- 6

Input common mode range-

[(Vdd – Vov3) + Vgs1] to
[Vgs1 + Vov5]

Output common mode range–

[(Vdd – Vov3 + IR ] to
Vov5 + Vov1 ] range here

Output signal swing range–

[(Vdd – Vov3 to Vov5 + Vov1 ]
Extreme voltage/ current limits
for proper operation
1) Differential characteristics
Single/ Diff vout vs. Diff. vin

Single/ Diff Iout vs. Diff. Vin

Gm diff . vs. diff vin (transfer characteristic)

Single vout vs. single vin

Single Iout vs. single vin

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Large signal Characteristics-

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Large signal Characteristics-

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Large signal analysis---
Transfer Characteristics

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Vid (max)— Range of differential
mode operation

Transistor remain in saturation

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 Range of Vin for Diff. Mode
Operation

𝐼𝑆𝑆
𝐷𝑖𝑓𝑓. 𝑀𝑜𝑑𝑒 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛, 𝑉𝑜𝑣,𝑑𝑖𝑓𝑓 = 𝑉𝐺𝑆1 − 𝑉𝑇 =
𝑊
𝜇𝑁 𝐶𝑜𝑥
𝐿

M1 trans. Conducting Iss ,

2𝐼𝑆𝑆
𝑉𝑜𝑣,𝑆𝑙𝑒𝑤 = 𝑉𝐺𝑆1 − 𝑉𝑇 = 𝑊 = 2 𝑉𝑜𝑣,𝑑𝑖𝑓𝑓 = 2 𝑉𝑜𝑣
𝜇𝑁 𝐶𝑜𝑥
𝐿

VIN 1  VGS 1  VP
VGS 2  VIN 2  VP  VT ; For  M 2  Cut  off
[VIN 1  VIN 2 ]  (VGS 1  VP )  (VT  VP )  VGS 1  VT
 [VIN 1  VIN 2 ]  2V0V
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Behaviour of P node

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Behaviour of ID(M1) / Vp in
difference/ slew mode

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Behaviour of P node in difference/
slew mode

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Large signal Characteristics-

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Large signal Characteristics-
Common Mode

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 BITS Pilani
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Effect of Mismatch on ADM/ ACM,

Random/ Systematic Input offset

Mismatch-
Random/ Systematic

Random--- Due to process variation, during fabrication of

design on Silicon. Can not be corrected.

Systematics-- Due to design errors. Can be corrected

while designing.

Consequence---INPUT OFFSET VOLTAGE

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Mismatch-
Random
Sources of mismatch-- MOSFET/ BJT

• Rd (load) mismatch

• Vt mismatch/ Vɤ

• Kn’ mismatch/ Is mismatch

• (W/L) mismatch

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Rss was unimportant in fully differential
circuit only with condition of perfect symmetry

As node p at ac ground

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Effect of Asymmetry

• Acm ≠ 0, CMRR is not infinite (noise

propagation to output

• Input offset voltage

• Remedy ---- Rss must be large

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Real case—asymmetry in diff.
pair

• Rd Asymmetry

• Transistor pair (M1, M2) Asymmetry

BITS Pilani, Pilani Campus

Rd asymmetry— Acm calculation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Acm----Rd mismatch
Contd…

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rd asymmetry— Acm calculation
contd.

Design tip----Increase Rss to reduce offset

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

gm mismatch-----Acm , CMRR
calculation diff. output ≠ 0
Find Vx - Vy

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

ID1=
Acm , CMRR calculation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Total Acm--- Rd & gm asymmetry
together

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Input offset voltage ( vout diff. for no ac
input)

 Diff output (Vo) exists even with both inputs grounded----

-output dc offset

 Input offset Vos= Vo/Adm

Vos = Vin1-Vin2 = Vgs1- Vgs2

Vos = (Vgs1- Vt)- (Vgs2-Vt)

Vos = Vov1- Vov2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Input offset

• The input offset voltage is defined as the diff. voltage that

must be applied between the two input terminals of the op

amp to obtain zero volts at the output.

• Ideally, the differential output of the op amp should be zero

volts when the inputs are at same potential.

• In reality , due to offset, the output terminals are at slightly

different potentials
BITS Pilani, Pilani Campus
Significance of input offset voltage

 Critical Specification in diff. amp as comparator

design

 Input offset= Output offset/ Adm

 Input less than Vos will not produce any output.

Or

 Voltages can not be compared

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Sources of input offset

Input offset in diff. amplifier is due to mismatch in dc currents

I1, I2 which causes differential current ; ∆𝑰 = 𝑰𝟐 - 𝑰𝟏

𝑮𝒎 𝑽𝒐𝒇𝒇𝒔𝒆𝒕 = 𝒈𝒎 𝑽𝒐𝒇𝒇𝒔𝒆𝒕 = ∆𝑰

Sources of input offset---

• Rd (load) mismatch
• Vt mismatch
• Kn’ mismatch
• (W/L) mismatch

BITS Pilani, Pilani Campus

Input offset due to Rd mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Output offset due to W/L mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Output offset due to Vt mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 OFFSET due to Kn´ mismatch
𝑖𝑛𝑝𝑢𝑡 𝑜𝑓𝑓𝑠𝑒𝑡 𝑑𝑢𝑒 𝑡𝑜 𝐾𝑛′ 𝑚𝑖𝑠𝑚𝑎𝑡𝑐ℎ − −
′
1 ∆𝐾𝑛 𝑊 2
𝐼1 = 𝐾𝑛 − 𝑉𝑔𝑠 − 𝑉𝑇
2 2 𝐿
′ 𝑊 2 ∆𝐾𝑛′ 𝑊 2
𝐼1 = 0.5𝐾𝑛 𝑉𝑔𝑠 − 𝑉𝑇 − 𝑉𝑔𝑠 − 𝑉𝑇
𝐿 4 𝐿

𝐼 ∆𝐾𝑛′ 1 𝑊 2
𝐼1 = − 𝑉𝑔𝑠 − 𝑉𝑇 𝐾𝑛′
2 2𝐾𝑛′ 2 𝐿
𝐼 𝑰 ∆𝐾𝑛′
𝐼1 = −
2 𝟐 2𝐾𝑛′
𝐼 𝐼 ∆𝐾𝑛′
Similarly--- 𝐼2 = +
2 2 𝐾𝑛′
𝑰 ∆𝐾𝑛′
∆𝑰 = 𝑰𝟐 - 𝑰𝟏 =
𝟐 𝐾𝑛′
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Voffset due to Kn´ (= μn Cox)
mismatch
𝑮𝒎 𝑽𝒐𝒇𝒇𝒔𝒆𝒕 = 𝒈𝒎 𝑽𝒐𝒇𝒇𝒔𝒆𝒕 = ∆𝑰

𝐼 ∆𝐾𝑛′
∆𝐼 2 𝐾𝑛′
𝑉𝑜𝑓𝑓𝑠𝑒𝑡 = =
𝑔𝑚 𝐼ൗ
𝑉𝑜𝑣.
∆𝐾𝑛′
𝑽𝒐𝒇𝒇𝒔𝒆𝒕 = 𝟐𝑽𝒐𝒗.
𝐾𝑛′

𝐼 ∆𝐾𝑛′
∆𝐼 = 𝐼2 - 𝐼1 =
2 𝐾𝑛′
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Total input offset
output offset= input offset x Adm

Voutput offset= Vinput offset x Adm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Random Offset due to Random Mismatch –
Diff. amp. with active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Active load -- Diff Amplifier

 BITS Pilani
Pilani Campus

Difference/ Common mode operation

Diff amp with Active (Current mirror) load
Why do we need single ended
output diff amp?

Convenience

Single output diff amp can easily cascade with single stage

amplifiers like CSA, CGA, CDA, CASCODE amplifiers

BITS Pilani, Pilani Campus

What do we loose?

1) Symmetry of the circuit even if we have matched devices.

So two currents through M1 and M2 will not be exactly same
(diff through current through ro component )

Consequences---

 ac currents not exactly equal, an ac current flows through Iss.

source (Vp) is not at ac ground and

 Acm >0, CMRR reduces, (noise immunity reduces)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

What do we loose?

• Acm ≠ 0, CMRR less. Hence to again make that it small,

make Rss very large

• Systematic offset may be present, Careful design is

required to get differential operation here

2) Output Voltage swing reduces (not double).

3) Even order harmonics (not cancelled) present in output

BITS Pilani, Pilani Campus

 Difference mode--single ended
output

Assume input splits equally.( Will they?)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff. amp. with Active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff amp with current mirror load
symmetry of two arms is lost

VDD

i
gm4vF

i -i

i = gm vin/2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

How much AC voltage at P node?

How much AC voltage at P node?

VDD

i
gm4vF

i -i

i = gm vin/2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Using principle of superposition
1+2+3

i = gm vin/2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

AC behavior of P node for diff. input—
ideally vp=0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Now, Rss plays a crucial role

 If Iss is implemented as diode connected

transistor------ Vp ≠ vin/2---two inputs may not
be equal. why? DC BIAS CURRENT WILL CHANGE
VDD

i
gm4vF

i -i

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

ADM—when Vp is not ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Source coupled node--- ac ground
for intuitive analysis

Thus, node p is assumed at AC ground for all

calculations

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

What happens if Rss is small?

 The [Rss|| 1/gm] shall reduce

 so Vp will increase

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Implementation—increasing Rout

 Cascode current source— use

source degeneration

For identical devices

CTR = 1
loss = 2 Vgs- Vt
Rout Rout = ro + ro + gm
Voltage loss ro2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 High Rss current mirror

 Casode CM

2 Vgs-Vt

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BJT Cascode current mirror
Impact of rπ1 - Rss reduces

rπ1 || ro4

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Wilson current mirror, Iref ideal

i= gm (-iro - i/gm) + [v-{i/ gm}] / ro

v/i = gm ro2 +3ro

v

i
-iro

-gm ro i/gm = = i/gm

2 Vgs-Vt

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Contd…
i= gm (-iro-i/gm) + [v-i/gm] / ro

v/i = gm ro2 +3ro

v

i
-iro

-gm ro i/gm = = i/gm

2 Vgs-Vt
Modified Wilson current mirror (to
negate Vds mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BJT Wilson current mirror—
Impact of rπ - reduced Rout

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design Tips for current mirror
design

 DESIGN TIPS---to get differential operation with

asymmetric diff. amp

 ---Rss very large

 ---Take L large to get ro very large

 Both will help in splitting vin nearly equally between

two differential transistors, to bring p node to nearly
ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Gain Using [Gm × Rout] method

Gm with Assumption----node p at
ac ground

VDD
-gm4vF = gm4 [gm1/gm3] vid/2
i -gm4vF
i
As gm3=gm4
-[gm1/gm3]
vin/2
-gm4 vF = gm1 vid/2= i
i i
vid Gm
1/gm2 i
io = 2i= 2gm1 vin1
1/gm1
Rss= 1/gm5 vout

i Rout= ro4 || ro2

Gm≈ gm1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Rout --- Vp not ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Contd.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rout-- intuitively
gm4 (1/gm3) Vx

2ro2+ 1/gm3

Vx (1/gm3)
2ro2+ 1/gm3

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rout --- Vp node ac ground

i2 / gm3

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Adm, Voltage gain= Gm x Rout

Thus node p is assumed

at AC ground for all
calculations

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Active Load Diff. Amp

Common mode operation---
Acm, CMRR
Common Mode Rejection Ratio-
CMRR

 CMRR= |Adm/ Acm|; figure of merit

 Ability to reject common signal

 For diff output---- Acm=0; CMRR→∞

ideal case

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Single ended output Diff Amp

• With resistive load

• With Active load

BITS Pilani, Pilani Campus

Resistive load diff amp—
single ended output, using half circuit concept

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

CMRR--- Resistive load diff. amp.

= ½ gmRd

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Active load diff amp - Acm
using half circuit (folding) concept

1 𝑟𝑜3,4
||
2𝑔𝑚3,4 2
𝐴𝐶𝑀 ≈ −
1
+ 𝑅𝑠𝑠
2𝑔𝑚1,2
−1 𝑔𝑚1,2
𝐴𝐶𝑀 ≈ ×
1 + 2𝑔𝑚1,2 𝑅𝑠𝑠 𝑔𝑚3,4
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Active load Diff Amp-- Adm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Active load Diff amp--- CMRR

Rss should be large

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Systematic Offset voltage

calculation
Random Offset due to Random Mismatch –
Diff. amp. with active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Systematic Offset –
Diff. amp. with active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Systematic Offset – (for matched devices)
Diff. amp. with active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Systematic offset--- more in BJT diff amp
Need base current compensation to reduce it

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Can we apply input single endedly

but obtain differential operation??
Why??? Convenience
Example---Applying input single
endedly

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Difference mode operation
Input applied is single ended. Why?
Convenience.
Differential o/p is not always available.

Now, Half circuit concept cannot be applied

Ac ground
Vin
Not ac gnd., for
equal input to M1,
M2, it should be
vin/2 ideally
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Can we still get differential gain?
Yes, condition--- Rss large

Thevenin equivalent

= gm/2 Rd

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Gm= gm/2

= - gm Rd
 BITS Pilani
Pilani Campus

End