®

OPA627
OPA
627
OPA637
OPA
627

Precision High-Speed
Difet ® OPERATIONAL AMPLIFIERS

FEATURES APPLICATIONS
● VERY LOW NOISE: 4.5nV/√Hz at 10kHz ● PRECISION INSTRUMENTATION
● FAST SETTLING TIME: ● FAST DATA ACQUISITION
OPA627—550ns to 0.01% ● DAC OUTPUT AMPLIFIER
OPA637—450ns to 0.01%
● OPTOELECTRONICS
● LOW VOS: 100µV max
● SONAR, ULTRASOUND
● LOW DRIFT: 0.8µV/°C max
● HIGH-IMPEDANCE SENSOR AMPS
● LOW IB: 5pA max
● HIGH-PERFORMANCE AUDIO CIRCUITRY
● OPA627: Unity-Gain Stable
● ACTIVE FILTERS
● OPA637: Stable in Gain ≥ 5

DESCRIPTION High frequency complementary transistors allow in-

creased circuit bandwidth, attaining dynamic perform-
The OPA627 and OPA637 Difet operational amplifi- ance not possible with previous precision FET op
ers provide a new level of performance in a precision amps. The OPA627 is unity-gain stable. The OPA637
FET op amp. When compared to the popular OPA111 is stable in gains equal to or greater than five.
op amp, the OPA627/637 has lower noise, lower offset
Difet fabrication achieves extremely low input bias
voltage, and much higher speed. It is useful in a broad
currents without compromising input voltage noise
range of precision and high speed analog circuitry.
performance. Low input bias current is maintained
The OPA627/637 is fabricated on a high-speed, dielec- over a wide input common-mode voltage range with
trically-isolated complementary NPN/PNP process. It unique cascode circuitry.
operates over a wide range of power supply voltage—
The OPA627/637 is available in plastic DIP, SOIC
±4.5V to ±18V. Laser-trimmed Difet input circuitry
and metal TO-99 packages. Industrial and military
provides high accuracy and low-noise performance
temperature range models are available.
comparable with the best bipolar-input op amps.

7
Trim +VS
Trim
1 5

Output
6

+In –In
3 2

Difet ®, Burr-Brown Corp. –VS

4

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©1989 Burr-Brown Corporation PDS-998H Printed in U.S.A. March, 1998

SPECIFICATIONS
ELECTRICAL
At TA = +25°C, and VS = ±15V, unless otherwise noted.

OPA627BM, BP, SM OPA627AM, AP, AU

OPA637BM, BP, SM OPA637AM, AP, AU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
OFFSET VOLTAGE (1)
Input Offset Voltage 40 100 130 250 µV
AP, BP, AU Grades 100 250 280 500 µV
Average Drift 0.4 0.8 1.2 2 µV/°C
AP, BP, AU Grades 0.8 2 2.5 µV/°C
Power Supply Rejection VS = ±4.5 to ±18V 106 120 100 116 dB
INPUT BIAS CURRENT (2)
Input Bias Current VCM = 0V 1 5 2 10 pA
Over Specified Temperature VCM = 0V 1 2 nA
SM Grade VCM = 0V 50 nA
Over Common-Mode Voltage VCM = ±10V 1 2 pA
Input Offset Current VCM = 0V 0.5 5 1 10 pA
Over Specified Temperature VCM = 0V 1 2 nA
SM Grade 50 nA
NOISE
Input Voltage Noise
Noise Density: f = 10Hz 15 40 20 nV/√Hz
f = 100Hz 8 20 10 nV/√Hz
f = 1kHz 5.2 8 5.6 nV/√Hz
f = 10kHz 4.5 6 4.8 nV/√Hz
Voltage Noise, BW = 0.1Hz to 10Hz 0.6 1.6 0.8 µVp-p
Input Bias Current Noise
Noise Density, f = 100Hz 1.6 2.5 2.5 fA/√Hz
Current Noise, BW = 0.1Hz to 10Hz 30 60 48 fAp-p
INPUT IMPEDANCE
Differential 1013 || 8 * Ω || pF
Common-Mode 1013 || 7 * Ω || pF
INPUT VOLTAGE RANGE
Common-Mode Input Range ±11 ±11.5 * * V
Over Specified Temperature ±10.5 ±11 * * V
Common-Mode Rejection VCM = ±10.5V 106 116 100 110 dB
OPEN-LOOP GAIN
Open-Loop Voltage Gain VO = ±10V, RL = 1kΩ 112 120 106 116 dB
Over Specified Temperature VO = ±10V, RL = 1kΩ 106 117 100 110 dB
SM Grade VO = ±10V, RL = 1kΩ 100 114 dB
FREQUENCY RESPONSE
Slew Rate: OPA627 G =
–1, 10V Step 40 55 * * V/µs
OPA637 G =
–4, 10V Step 100 135 * * V/µs
Settling Time: OPA627 0.01% G =
–1, 10V Step 550 * ns
0.1% G =
–1, 10V Step 450 * ns
OPA637 0.01% G =
–4, 10V Step 450 * ns
0.1% G =
–4, 10V Step 300 * ns
Gain-Bandwidth Product: OPA627 G=1 16 * MHz
OPA637 G = 10 80 * MHz
Total Harmonic Distortion + Noise G = +1, f = 1kHz 0.00003 * %
POWER SUPPLY
Specified Operating Voltage ±15 * V
Operating Voltage Range ±4.5 ±18 * * V
Current ±7 ±7.5 * * mA
OUTPUT
Voltage Output RL = 1kΩ ±11.5 ±12.3 * *
Over Specified Temperature ±11 ±11.5 * * V
Current Output VO = ±10V ±45 * mA
Short-Circuit Current ±35 +70/–55 ±100 * * * mA
Output Impedance, Open-Loop 1MHz 55 * Ω
TEMPERATURE RANGE
Specification: AP, BP, AM, BM, AU –25 +85 * * °C
SM –55 +125 °C
Storage: AM, BM, SM –60 +150 * * °C
AP, BP, AU –40 +125 * * °C
θJ-A: AM, BM, SM 200 * °C/W
AP, BP 100 * °C/W
AU 160 °C/W

* Specifications same as “B” grade.

NOTES: (1) Offset voltage measured fully warmed-up. (2) High-speed test at TJ = +25°C. See Typical Performance Curves for warmed-up performance.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®

OPA627, 637 2
PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS(1)
Top View DIP/SOIC Supply Voltage .................................................................................. ±18V
Input Voltage Range .............................................. +VS + 2V to –VS – 2V
Differential Input Range ....................................................... Total VS + 4V
Offset Trim Power Dissipation ........................................................................ 1000mW
1 8 No Internal Connection
Operating Temperature
–In 2 7 +VS M Package .................................................................. –55°C to +125°C
P, U Package ............................................................. –40°C to +125°C
+In 3 6 Output Storage Temperature
M Package .................................................................. –65°C to +150°C
–VS 4 5 Offset Trim P, U Package ............................................................. –40°C to +125°C
Junction Temperature
M Package .................................................................................. +175°C
P, U Package ............................................................................. +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
SOlC (soldering, 3s) ................................................................... +260°C

NOTE: (1) Stresses above these ratings may cause permanent damage.
Top View TO-99
No Internal Connection

PACKAGE/ORDERING INFORMATION
8 +VS
Offset Trim PACKAGE DRAWING TEMPERATURE
1 7
PRODUCT PACKAGE NUMBER(1) RANGE

OPA627AP Plastic DIP 006 –25°C to +85°C

–In OPA627BP Plastic DIP 006 –25°C to +85°C
2 6 Output
OPA627AU SOIC 182 –25°C to +85°C
OPA627AM TO-99 Metal 001 –25°C to +85°C
OPA627BM TO-99 Metal 001 –25°C to +85°C
3 5 OPA627SM TO-99 Metal 001 –55°C to +125°C

+In 4 Offset Trim OPA637AP Plastic DIP 006 –25°C to +85°C

OPA637BP Plastic DIP 006 –25°C to +85°C
–VS OPA637AU SOIC 182 –25°C to +85°C
OPA637AM TO-99 Metal 001 –25°C to +85°C
Case connected to –VS. OPA637BM TO-99 Metal 001 –25°C to +85°C
OPA637SM TO-99 Metal 001 –55°C to +125°C

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

3 OPA627, 637
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VS = ±15V, unless otherwise noted.

INPUT VOLTAGE NOISE SPECTRAL DENSITY TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH
1k 100
p-p
Noise Bandwidth:
Voltage Noise (nV/ √ Hz)

Input Voltage Noise (µV)

10 0.1Hz to indicated
frequency.
100

10
0.1
RMS

1 0.01
1 10 100 1k 10k 100k 1M 10M 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Bandwidth (Hz)

VOLTAGE NOISE vs SOURCE RESISTANCE OPEN-LOOP GAIN vs FREQUENCY

1k 140
–
120
+
Voltage Noise (nV/ √ Hz)

100 OPA637
Voltage Gain (dB)

RS
100
80

60
Comparison with
OPA627 + Resistor
OPA27 Bipolar Op 40
10 OPA627
Amp + Resistor
20
Spot Noise
Resistor Noise Only at 10kHz 0

1 –20
100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M
Source Resistance ( Ω) Frequency (Hz)

OPA627 GAIN/PHASE vs FREQUENCY OPA637 GAIN/PHASE vs FREQUENCY

30 –90 30 –90

20 –120 20 –120
Phase (Degrees)
Phase (Degrees)
Gain (dB)

Gain (dB)

Phase Phase
75° Phase
Margin Gain
10 –150 10 –150
Gain

0 –180 0 –180

–10 –210 –10 –210

1 10 100 1 10 100
Frequency (MHz) Frequency (MHz)

OPA627, 637 4
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

OPEN-LOOP GAIN vs TEMPERATURE OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY

125 100

80

Output Resistance (Ω)

120
Voltage Gain (dB)

60
115
40

110
20

105 0
–75 –50 –25 0 25 50 75 100 125 2 20 200 2k 20k 200k 2M 20M
Temperature (°C) Frequency (Hz)

COMMON-MODE REJECTION vs
COMMON-MODE REJECTION vs FREQUENCY INPUT COMMON MODE VOLTAGE
140 130
Common-Mode Rejection Ratio (dB)

Common-Mode Rejection (dB)

120 OPA637
120
100
110
80 OPA627

60 100

40
90
20

0 80
1 10 100 1k 10k 100k 1M 10M –15 –10 –5 0 5 10 15
Frequency (Hz) Common-Mode Voltage (V)

POWER-SUPPLY REJECTION AND COMMON-MODE

POWER-SUPPLY REJECTION vs FREQUENCY REJECTION vs TEMPERATURE
140 125

120
Power-Supply Rejection (dB)

PSR
120
CMR and PSR (dB)

100
–VS PSRR 627
80 and 637 CMR
115
60
+VS PSRR 627
40 637 110

20

0 105
1 10 100 1k 10k 100k 1M 10M –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)

5 OPA627, 637
 TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

SUPPLY CURRENT vs TEMPERATURE OUTPUT CURRENT LIMIT vs TEMPERATURE

8 100

+IL at VO = 0V
80
7.5
Supply Current (mA)

Output Current (mA)

+IL at VO = +10V
60
7
40
–IL at VO = 0V
6.5
20
–IL at VO = –10V

6 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

OPA627 GAIN-BANDWIDTH AND SLEW RATE OPA637 GAIN-BANDWIDTH AND SLEW RATE
vs TEMPERATURE vs TEMPERATURE
24 60 120 160
Slew Rate
Gain-Bandwidth (MHz)
Gain-Bandwidth (MHz)

20 100 140

Slew Rate (V/µs)

Slew Rate (V/µs)

Slew Rate

16 55 80 120

GBW
GBW
12 60 100

8 50 40 80
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

OPA627 TOTAL HARMONIC DISTORTION + NOISE OPA637 TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY vs FREQUENCY
0.1 G = +1 G = +10 1
G = +10 G = +50
VI + VO = ±10V VI + VO = ±10V
VI + VO = ±10V VI + VO = ±10V
– 600 Ω – 600 Ω
100pF 5kΩ 100pF – 600Ω – 600Ω
0.01 0.1 5k Ω 100pF 5k Ω 100pF
549 Ω
549Ω 102 Ω
THD+N (%)

THD+N (%)

0.001 Measurement BW: 80kHz 0.01

G = +50
G = +10 Measurement BW: 80kHz

0.0001 0.001
G = +1

G = +10
0.00001 0.0001
20 100 1k 10k 20k 20 100 1k 10k 20k
Frequency (Hz) Frequency (Hz)

OPA627, 637 6
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

INPUT BIAS AND OFFSET CURRENT INPUT BIAS CURRENT

vs JUNCTION TEMPERATURE vs POWER SUPPLY VOLTAGE
10k 20
NOTE: Measured fully
1k warmed-up.

Input Bias Current (pA)

15
Input Current (pA)

TO-99
100
IB
10 Plastic
10 IOS DIP, SOIC

5
1

TO-99 with 0807HS Heat Sink

0.1 0
–50 –25 0 25 50 75 100 125 150 ±4 ±6 ±8 ±10 ±12 ±14 ±16 ±18
Junction Temperature (°C) Supply Voltage (±VS)

INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE INPUT OFFSET VOLTAGE WARM-UP vs TIME
1.2 50

Beyond Linear Offset Voltage Change (µV)

Input Bias Current Multiplier

Common-Mode Range
1.1 25

1 0

0.9 –25
Beyond Linear
Common-Mode Range

0.8 –50
–15 –10 –5 0 5 10 15 0 1 2 3 4 5 6
Common-Mode Voltage (V) Time From Power Turn-On (Min)

MAX OUTPUT VOLTAGE vs FREQUENCY SETTLING TIME vs CLOSED-LOOP GAIN

30 100
Output Voltage (Vp-p)

Error Band: ±0.01%

Settling Time (µs)

20 10

OPA627
OPA637

10 1 OPA637
OPA627

0 0.1
100k 1M 10M 100M –1 –10 –100 –1000
Frequency (Hz) Closed-Loop Gain (V/V)

7 OPA627, 637
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

SETTLING TIME vs ERROR BAND SETTLING TIME vs LOAD CAPACITANCE

1500 3
CF

RI +5V OPA627 OPA637

– RF RI 2kΩ 500Ω OPA637
–5V Error Band: G = –4
Settling Time (ns)

Settling Time (µs)

1000 +
RF 2kΩ 2kΩ 2
2kΩ CF 6pF 4pF ±0.01%

OPA627 OPA627
500 1 G = –1
G = –1

OPA637
G = –4
0 0
0.001 0.01 0.1 1 10 0 150 200 300 400 500
Error Band (%) Load Capacitance (pF)

APPLICATIONS INFORMATION RF < 4RI

The OPA627 is unity-gain stable. The OPA637 may be used
OPA627 OPA627
to achieve higher speed and bandwidth in circuits with noise – –

gain greater than five. Noise gain refers to the closed-loop + +

Buffer
gain of a circuit as if the non-inverting op amp input were Non-Inverting Amp
RI G<5
being driven. For example, the OPA637 may be used in a
non-inverting amplifier with gain greater than five, or an
inverting amplifier of gain greater than four. RF < 4R

When choosing between the OPA627 or OPA637, it is OPA627 RI

– – OPA627
important to consider the high frequency noise gain of your
circuit configuration. Circuits with a feedback capacitor +
Bandwidth
+
Inverting Amp
(Figure 1) place the op amp in unity noise-gain at high Limiting G < |–4|
frequency. These applications must use the OPA627 for
proper stability. An exception is the circuit in Figure 2,
where a small feedback capacitance is used to compensate OPA627 OPA627
for the input capacitance at the op amp’s inverting input. In – –

this case, the closed-loop noise gain remains constant with + +

frequency, so if the closed-loop gain is equal to five or Integrator Filter

greater, the OPA637 may be used.

FIGURE 1. Circuits with Noise Gain Less than Five Require

the OPA627 for Proper Stability.
®

OPA627, 637 8
OFFSET VOLTAGE ADJUSTMENT amp contributes little additional noise. Below 1kΩ, op amp
The OPA627/637 is laser-trimmed for low offset voltage noise dominates over the resistor noise, but compares
and drift, so many circuits will not require external adjust- favorably with precision bipolar op amps.
ment. Figure 3 shows the optional connection of an external
potentiometer to adjust offset voltage. This adjustment should
CIRCUIT LAYOUT
not be used to compensate for offsets created elsewhere in a
As with any high speed, wide bandwidth circuit, careful
system (such as in later amplification stages or in an A/D
layout will ensure best performance. Make short, direct
converter) because this could introduce excessive tempera-
interconnections and avoid stray wiring capacitance—espe-
ture drift. Generally, the offset drift will change by approxi-
cially at the input pins and feedback circuitry.
mately 4µV/°C for 1mV of change in the offset voltage due
to an offset adjustment (as shown on Figure 3). The case (TO-99 metal package only) is internally connected
to the negative power supply as it is with most common op
amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages
C2 has no internal connection.
Power supply connections should be bypassed with good
high frequency capacitors positioned close to the op amp
C1 R2 pins. In most cases 0.1µF ceramic capacitors are adequate.
–
The OPA627/637 is capable of high output current (in
+
OPA637
excess of 45mA). Applications with low impedance loads or
capacitive loads with fast transient signals demand large
R1 C1 = CIN + CSTRAY currents from the power supplies. Larger bypass capacitors
R1 C1 such as 1µF solid tantalum capacitors may improve dynamic
C2 = performance in these applications.
R2

FIGURE 2. Circuits with Noise Gain Equal to or Greater than

Five May Use the OPA637. +VS

100kΩ
NOISE PERFORMANCE 7 10kΩ to 1MΩ
Some bipolar op amps may provide lower voltage noise 1 Potentiometer
2
performance, but both voltage noise and bias current noise – 5 (100kΩ preferred)
contribute to the total noise of a system. The OPA627/637 3 6
is unique in providing very low voltage noise and very low +
OPA627/637
current noise. This provides optimum noise performance 4
over a wide range of sources, including reactive source ±10mV Typical
Trim Range
impedances. This can be seen in the performance curve –VS
showing the noise of a source resistor combined with the
noise of an OPA627. Above a 2kΩ source resistance, the op FIGURE 3. Optional Offset Voltage Trim Circuit.

Non-inverting Buffer

2 2
– –
6 6
Out Out
3 In 3
In + +
OPA627 OPA627

TO-99 Bottom View

Inverting
In

OPA627 3 4
2
– 5
6
Out
3
+ 2 6
Board Layout for Input Guarding:
Guard top and bottom of board. 7
Alternate—use Teflon® standoff for sen- 1
sitive input pins. 8 No Internal Connection

Teflon® E.I. du Pont de Nemours & Co. To Guard Drive

FIGURE 4. Connection of Input Guard for Lowest IB.

®

9 OPA627, 637
INPUT BIAS CURRENT takes approximately 500ns. When the output is driven into
Difet fabrication of the OPA627/637 provides very low the positive limit, recovery takes approximately 6µs. Output
input bias current. Since the gate current of a FET doubles recovery of the OPA627 can be improved using the output
approximately every 10°C, to achieve lowest input bias clamp circuit shown in Figure 5. Diodes at the inverting
current, the die temperature should be kept as low as pos- input prevent degradation of input bias current.
sible. The high speed and therefore higher quiescent current
of the OPA627/637 can lead to higher chip temperature. A
simple press-on heat sink such as the Burr-Brown model +VS
807HS (TO-99 metal package) can reduce chip temperature
by approximately 15°C, lowering the IB to one-third its
5kΩ
warmed-up value. The 807HS heat sink can also reduce low- (2)
frequency voltage noise caused by air currents and thermo- HP 5082-2811
electric effects. See the data sheet on the 807HS for details.
ZD1 Diode Bridge
Temperature rise in the plastic DIP and SOIC packages can BB: PWS740-3
be minimized by soldering the device to the circuit board. 1kΩ
Wide copper traces will also help dissipate heat.
5kΩ ZD1 : 10V IN961
The OPA627/637 may also be operated at reduced power
supply voltage to minimize power dissipation and tempera- RF
ture rise. Using ±5V power supplies reduces power dissipa- VI – –VS
tion to one-third of that at ±15V. This reduces the IB of TO- RI
+
VO

99 metal package devices to approximately one-fourth the OPA627 Clamps output

at VO = ±11.5V
value at ±15V.
Leakage currents between printed circuit board traces can FIGURE 5. Clamp Circuit for Improved Overload Recovery.
easily exceed the input bias current of the OPA627/637. A
circuit board “guard” pattern (Figure 4) reduces leakage
effects. By surrounding critical high impedance input cir- CAPACITIVE LOADS
cuitry with a low impedance circuit connection at the same As with any high-speed op amp, best dynamic performance
potential, leakage current will flow harmlessly to the low- can be achieved by minimizing the capacitive load. Since a
impedance node. The case (TO-99 metal package only) is load capacitance presents a decreasing impedance at higher
internally connected to –VS. frequency, a load capacitance which is easily driven by a
Input bias current may also be degraded by improper han- slow op amp can cause a high-speed op amp to perform
dling or cleaning. Contamination from handling parts and poorly. See the typical curves showing settling times as a
circuit boards may be removed with cleaning solvents and function of capacitive load. The lower bandwidth of the
deionized water. Each rinsing operation should be followed OPA627 makes it the better choice for driving large capaci-
by a 30-minute bake at 85°C. tive loads. Figure 6 shows a circuit for driving very large
load capacitance. This circuit’s two-pole response can also
Many FET-input op amps exhibit large changes in input
be used to sharply limit system bandwidth. This is often
bias current with changes in input voltage. Input stage useful in reducing the noise of systems which do not require
cascode circuitry makes the input bias current of the
the full bandwidth of the OPA627.
OPA627/637 virtually constant with wide common-mode
voltage changes. This is ideal for accurate high input-
impedance buffer applications.
RF
1kΩ
PHASE-REVERSAL PROTECTION
The OPA627/637 has internal phase-reversal protection. 200pF
Many FET-input op amps exhibit a phase reversal when the G = +1
CF
input is driven beyond its linear common-mode range. This RO BW ≥ 1MHz
– 20Ω
is most often encountered in non-inverting circuits when the
input is driven below –12V, causing the output to reverse + CL
into the positive rail. The input circuitry of the OPA627/637 RF OPA627 5nF
G = 1+ R1
does not induce phase reversal with excessive common- R1
mode voltage, so the output limits into the appropriate rail. Optional Gain For Approximate Butterworth Response:
Gain > 1 2 RO CL
CF = RF >> RO
RF
OUTPUT OVERLOAD
1
When the inputs to the OPA627/637 are overdriven, the f–3dB =
2π √ RF RO CF CL
output voltage of the OPA627/637 smoothly limits at ap-
proximately 2.5V from the positive and negative power
FIGURE 6. Driving Large Capacitive Loads.
supplies. If driven to the negative swing limit, recovery
®

OPA627, 637 10
INPUT PROTECTION Sometimes input protection is required on I/V converters of
The inputs of the OPA627/637 are protected for voltages inverting amplifiers (Figure 7b). Although in normal opera-
between +VS + 2V and –VS – 2V. If the input voltage can tion, the voltage at the summing junction will be near zero
exceed these limits, the amplifier should be protected. The (equal to the offset voltage of the amplifier), large input
diode clamps shown in Figure 7a will prevent the input transients may cause this node to exceed 2V beyond the
voltage from exceeding one forward diode voltage drop power supplies. In this case, the summing junction should
beyond the power supplies—well within the safe limits. If be protected with diode clamps connected to ground. Even
the input source can deliver current in excess of the maxi- with the low voltage present at the summing junction,
mum forward current of the protection diodes, use a series common signal diodes may have excessive leakage current.
resistor, RS, to limit the current. Be aware that adding Since the reverse voltage on these diodes is clamped, a
resistance to the input will increase noise. The 4nV/√Hz diode-connected signal transistor can be used as an inexpen-
theoretical thermal noise of a 1kΩ resistor will add to the sive low leakage diode (Figure 7b).
4.5nV/√Hz noise of the OPA627/637 (by the square-root of
the sum of the squares), producing a total noise of 6nV/√Hz.
Resistors below 100Ω add negligible noise. +VS

Leakage current in the protection diodes can increase the –

total input bias current of the circuit. The specified maxi- D VO
+ OPA627
mum leakage current for commonly used diodes such as the D
D: IN4148 — 25nA Leakage
1N4148 is approximately 25nA—more than a thousand Optional RS
2N4117A — 1pA Leakage
times larger than the input bias current of the OPA627/637. –VS Siliconix
Leakage current of these diodes is typically much lower and =
may be adequate in many applications. Light falling on the (a)
junction of the protection diodes can dramatically increase
leakage current, so common glass-packaged diodes should
IIN
be shielded from ambient light. Very low leakage can be
–
achieved by using a diode-connected FET as shown. The VO
2N4117A is specified at 1pA and its metal case shields the D D + OPA627
junction from light. D: 2N3904
=
(b)

NC

FIGURE 7. Input Protection Circuits.

LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE

(A) (B)

FPO

When used as a unity-gain buffer, large common-mode input voltage steps – G=1
produce transient variations in input-stage currents. This causes the rising
edge to be slower and falling edges to be faster than nominal slew rates +
observed in higher-gain circuits. OPA627

FIGURE 8. OPA627 Dynamic Performance, G = +1.

11 OPA627, 637
 LARGE SIGNAL RESPONSE

+10 +10
VOUT (V)

VOUT (V)
0 (C) 0 (D)

–10 –10

6pF(1)
NOTE: (1) Optimum value will
When driven with a very fast input step (left), common-mode
depend on circuit board lay-
transients cause a slight variation in input stage currents which
out and stray capacitance at
will reduce output slew rate. If the input step slew rate is reduced
the inverting input. 2kΩ
(right), output slew rate will increase slightly.
– G = –1
2kΩ
+ VOUT
OPA627

FIGURE 9. OPA627 Dynamic Performance, G = –1.

OPA637 OPA637
LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE

+10 +100
VOUT (mV)
VOUT (V)

0 (E) 0 (F)

FPO
–10 –100

4pF(1)

2kΩ
– G=5

+ VOUT
OPA637
500Ω
NOTE: (1) Optimum value will depend on circuit
board layout and capacitance at inverting input.

FIGURE 10. OPA637 Dynamic Response, G = 5.

OPA627, 637 12
 Error Out
/
RI 2kΩ

OPA627 OPA637
CF
RI , R 1 2kΩ 500Ω
HP- CF 6pF 4pF
5082- 2kΩ Error Band ±0.5mV ±0.2mV
2835 (0.01%)
+15V

RI
High Quality –
±5V NOTE: CF is selected for best settling time performance
Pulse Generator
depending on test fixture layout. Once optimum value is
51Ω Out
+ determined, a fixed capacitor may be used.

–15V

FIGURE 11. Settling Time and Slew Rate Test Circuit.

Gain = 100
OPA637 CMRR ≈ 116dB
–In +
Bandwidth ≈ 1MHz
– RF
5kΩ 2 25kΩ 25kΩ 5
Input Common-Mode
Range = ±5V INA105
RG
3pF Differential
101Ω – Output
Amplifier 6
3
+
RF 25kΩ
– 5kΩ 25kΩ

+In + 1
OPA637
Differential Voltage Gain = 1 + 2RF /RG

FIGURE 12. High Speed Instrumentation Amplifier, Gain = 100.

Gain = 1000
OPA637 CMRR ≈ 116dB
–In +
Bandwidth ≈ 400kHz
– RF
5kΩ 10kΩ 100kΩ 5
2
Input Common-Mode
Range = ±10V INA106
RG
3pF Differential
101Ω – Output
Amplifier 6
3
+
RF 10kΩ
– 5kΩ 100kΩ

+In + 1
OPA637

Differential Voltage Gain = (1 + 2RF /RG) • 10

FIGURE 13. High Speed Instrumentation Amplifier, Gain = 1000.

This composite amplifier uses the OPA603 current-feedback op amp to

R2 provide extended bandwidth and slew rate at high closed-loop gain. The
feedback loop is closed around the composite amp, preserving the
precision input characteristics of the OPA627/637. Use separate power
– supply bypass capacitors for each op amp.
A1 + *Minimize capacitance at this node.
VI + VO
– GAIN A1 R1 R2 R3 R4 –3dB SLEW RATE
OPA603 RL ≥ 150Ω
R1 for ±10V Out (V/V) OP AMP (Ω) (kΩ) (Ω) (kΩ) (MHz) (V/µs)
100 OPA627 50.5(1) 4.99 20 1 15 700
R3 * R4 1000 OPA637 49.9 4.99 12 1 11 500

NOTE: (1) Closest 1/2% value.

FIGURE 14. Composite Amplifier for Wide Bandwidth.

®

13 OPA627, 637