micromachines

Review
SRAM Cell Design Challenges in Modern Deep Sub-Micron
Technologies: An Overview
Waqas Gul *, Maitham Shams and Dhamin Al-Khalili

Department of Electronics, Carleton University, 1125 Colonel Bay Drive, Ottawa, ON K1S 5B6, Canada
* Correspondence: [email protected]; Tel.: +1-(613)-520-2600 (ext. 8411)

Abstract: Microprocessors use static random-access memory (SRAM) cells in the cache memory
design. As a part of the central computing component, their performance is critical. Modern system-
on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for
logic, while the remaining transistors are for the cache memory. Moreover, modern implantable,
portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient
and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements,
maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated
applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices,
the off-state current of a transistor is becoming comparable to the on-state current. On the other
hand, process variations change the transistor design parameters and eventually compromise design
integrity. Furthermore, sensitive information processing, environmental conditions and charge
emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with
aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This
article comprehensively reviews prominent challenges to the SRAM cell design after classifying them
into five distinct categories. Each category explains underlying mathematical relations followed by
viable solutions.
Citation: Gul, W.; Shams, M.;
Al-Khalili, D. SRAM Cell Design
Challenges in Modern Deep
Keywords: 6T-SAM; low power; leakage current; process variations; soft errors; fault-tolerant;
Sub-Micron Technologies: An reliability; multi-threshold; noise margins; assist circuits
Overview. Micromachines 2022, 13,
1332. https://doi.org/10.3390/
mi13081332
1. Introduction
Academic Editors: Carlos Sampedro
and Francisco Gamiz As an indispensable part of a computing system, memory dominates the semicon-
ductor industry. According to the world semiconductor trade statistics (WSTS), memory
Received: 27 June 2022
held 27% (USD117 bn) and 28% (USD154 bn) of the total semiconductor industry mar-
Accepted: 15 August 2022
ket share in 2020 and 2021, respectively. By the end of 2024, the semiconductor memory
Published: 17 August 2022
market is expected to surpass USD730 bn [1]. The ever-increasing demand for fast data
Publisher’s Note: MDPI stays neutral processing necessitates memory integration within the processor in contemporary artificial
with regard to jurisdictional claims in intelligence (AI) and internet-of-things (IoT) capable edge devices. Machine learning (ML)
published maps and institutional affil- is in dire need of such devices to perform compute-in-memory (CIM) for the energy and
iations. performance-efficient algorithms implementations [2,3].
Memory holds data either temporarily or permanently while processing. Two im-
portant parameters, access time and data retention, determine a memory hierarchy; faster
memory placement will be closer to the processing unit. Figure 1 shows memory clas-
Copyright: © 2022 by the authors.
sifications. Several emerging nonvolatile memory cells, such as MRAM, FRAM, RRAM,
Licensee MDPI, Basel, Switzerland.
PCM-RAM and FLASH, are appealing because of their improved retention time, density
This article is an open access article
and performance [4–7]. However, lower latency and push-rule-based manufacturing [8]
distributed under the terms and
have made the SRAM cell a suitable choice for cache memory.
conditions of the Creative Commons
Attribution (CC BY) license (https://
Technological scaling has aggressively improved SRAM performance and density. Cur-
creativecommons.org/licenses/by/
rently, a modern SoC contains about 90% of the transistors that account for the memory [9].
4.0/).

Micromachines 2022, 13, 1332. https://doi.org/10.3390/mi13081332 https://www.mdpi.com/journal/micromachines

 Short channel effects (SCE) [10] affect performance and enhance the leakage current. Con-
sequently, a transistor structural shift from planer to 3D-CMOS [11] and silicon on insu-
lator (SOI) [12] technologies mitigates the SCE and junction leakage. A FinFET-SRAM
Micromachines 2022, 6, x FOR PEER REVIEW 2 cell
of 23
provides better control over the conduction channel. Thus, FinFET is inevitable in modern
Micromachines 2022, 13, 1332 deep-submicron nodes. Nevertheless, the lower supply voltage poses severe threats to2 the of 22
SRAMTechnological
cell stability. scaling
The leakage current is similarly accelerating
has aggressively improved SRAM performance and density. the power budget [13].
Furthermore,
Currently, a variations
modern SoC in the threshold
contains about voltage
90% (V ) have
of ththe made non-erroneous
transistors that account SRAM for the
cell operation
memory [9]. alarming
However, [14]. The
technological reliability
scaling isisa direct
also implication
rendering a of process
confluence of variations
challenges.
However, technological scaling is also rendering a confluence of challenges. Short chan-
[15].
Short Besides
channel theeffects
aforementioned issues,performance
SRAM soft errors and data security
leakageare emerging
nel effects (SCE) [10] (SCE) [10] affect
affect performance and enhance andthe enhance
leakage thecurrent. current.
Consequently,Con-
areas [16]. Researchers
sequently, a transistor have proposed
structural shift many
from solutions
planer to to overcome
3D-CMOS [11] these
and issues
silicon on as
insu-a
a transistor structural shift from planer to 3D-CMOS [11] and silicon on insulator (SOI) [12]
tradeoff for
lator (SOI) [12]performance
technologies parameters
mitigates [17–19].
the SCE Additionally,
and junction recent trends
leakage. A cell in CIM
FinFET-SRAM need re-
cell
technologies mitigates the SCE and junction leakage. A FinFET-SRAM provides better
liable SRAM
provides performance
better whenthe multiple memory locations are simultaneously accessed.
control over the control
conductionover conduction
channel. channel.
Thus, FinFET Thus, FinFET
is inevitable is inevitable
in modern in modern
deep-submicron
Therefore,
deep-submicron
nodes. a comprehensive
nodes.the
Nevertheless, reviewsupply
Nevertheless,
lower as atheguideline
lower supply
voltage for
poses SRAMvoltage
severelimitations
poses
threats and
severe
to thestate-of-the-
threats
SRAM to cell
the
art
SRAMsolutions
cell is essential.
stability. The leakage current is similarly accelerating
stability. The leakage current is similarly accelerating the power budget [13]. Furthermore, the power budget [13].
This article
Furthermore,
variations in the reviews
variations
thresholdSRAM the cell
in voltage design
threshold obstacles
voltage
(Vth ) have made (Vand workarounds
) have
non-erroneous
th
(Figure
made non-erroneous
SRAM cell2).operation
Section
SRAM
2alarming
introduces
cell operation the conventional
[14]. alarming [14]. The
The reliability 6T-SRAM
is a reliabilitycell architecture
is a directofimplication
direct implication and associated
of process
process variations performance
[15].variations
Besides
measurement
[15].aforementioned
the Besides the parameters.
issues, Section
aforementioned SRAM 3 presents
issues, SRAM
soft errors theandlow-voltage
soft errors
data andoperation
security data issuesare
aresecurity
emerging and availa-
emerging
areas [16].
ble
areasremedies.
Researchers Section
[16]. Researchers
have 4 highlights
proposed havemany the
proposed leakage
manytocurrent’s
solutions solutions
overcome significance
tothese
overcomeissues and as minimization
these issues asfor
a tradeoff a
techniques.
tradeoff forNext,
performance Section 5[17–19].
performance
parameters details Additionally,
parameters process
[17–19].variations'
recentimpact
Additionally, on
in SRAM
trendsrecent CIM trends cellinreliable
need performance.
CIM need SRAM re-
Section
performance6 explains
liable SRAM when soft
performanceerrors’
multiple occurrence
when multiple
memory and
memory
locations solutions.
arelocations Then, are
simultaneously Section 7 overviews
simultaneously
accessed. secu-
accessed.
Therefore,
rity-aware
aTherefore, SRAM
comprehensive cell designs.
review as a review
a comprehensive Section
guideline 8 discusses
as afor current
SRAM limitations
guideline for SRAMand and future research
state-of-the-art
limitations trends. Fi-
solutions
and state-of-the-
nally,
is Section
artessential. 9 concludes
solutions is essential. this article.
This article reviews SRAM cell design obstacles and workarounds (Figure 2). Section
2 introduces the conventional 6T-SRAM cell architecture and associated performance
measurement parameters. Section 3 presents the low-voltage operation issues and availa-
ble remedies. Section 4 highlights the leakage current’s significance and minimization
techniques. Next, Section 5 details process variations' impact on SRAM cell performance.
Section 6 explains soft errors’ occurrence and solutions. Then, Section 7 overviews secu-
rity-aware SRAM cell designs. Section 8 discusses current and future research trends. Fi-
nally, Section 9 concludes this article.

Figure
Figure1.1.Computer
Computermemory
memoryclassifications
classificationsbased
basedon
ondata
dataretention.
retention.

This article reviews SRAM cell SRAM design obstacles and workarounds (Figure 2). Section 2
introduces the conventional 6T-SRAM cell architecture and associated performance mea-
surement
Issues Low
parameters. Section 3Process
presents
&
the low-voltage operation
Security
issues and available
Leakage Soft
remedies. SectionCurrents
Voltage 4 highlights the leakage current’s
Environmental Errorssignificance and minimization tech-
Aware
niques.Alternate
Next, Section 5 details process variations’
Bitline impact on
Modified PowerSRAM cell performance.
Redundancy
Section Cells
6 explains softLeakage Cells
errors’ occurrence and solutions. Then, Analysis
Section 7 overviews security-
Assist Asymmetric Cache Error and future research trends. Finally,
aware SRAM
Circuitscell designs.
Cells SectionRe-sizing
8 discusses current
Correcting Modified
Figure 1. Computer memory
Power classifications based on data
Codes
retention.
Cells
SectionDevice
9 concludes Gating
this article.
Structures Statistical
Performance
Body SRAM
Biasing Internal
&Extrnal
Novel
Solutions Devices
Issues Low Leakage Process & Soft Security
Voltage Currents Environmental Errors Aware
Figure 2. Overview of the SRAM challenges and potential solutions.
Alternate Bitline Modified Power
Cells Leakage Redundancy Cells Analysis
Assist Asymmetric Cache Error
Circuits Cells Re-sizing Correcting Modified
Device Power Codes Cells
Structures Gating Statistical
Performance
Body
Biasing Internal
&Extrnal
Novel
Solutions Devices

Figure 2. Overview of the SRAM challenges and potential solutions.

2. SRAM Cell
The conventional SRAM cell consists of six transistors, as shown in Figure 3. The
internal nodes, Q and Qb, hold the bit value and its inverse, respectively. PMOS transistors,
PU1 and PU2, pull up these nodes. Similarly, NMOS transistors, PD1 and PD2, pull down
 Table 1. Performance evaluation parameters for SRAM cells.
S. No. Parameters Explanation
1 Read Access Time WL activation (50%) to 50–200 mV differential bitline voltage
2 Write Access Time WL activation (50%) to 90%/10% of rising/falling internal node
3 Read/Write Power Power consumption during read/write access time
Micromachines 2022, 13, 1332 4 Leakage Power Power consumption during standby or hold mode 3 of 22
5 Cell Area Layout area of the one SRAM cell
6 Noise Margins SRAM noise tolerance under hold/read/write mode
7 Reliability Performance under process/voltage/environmental variations
the
8 internal nodes. The
Soft Error passCritical
transistors, PG1 and PG2,
charge accumulation to flipprovide access
the internal for the
node value read and
write operations.

VDD VDD
Wordline Wordline
(W L) (W L)
PU2 PU1
Q Qb
PG2 PG1

Bitline (BLB)
Bitline (BL) (V2) (V1)
PD2 PD1

Figure
Figure 3. Conventional
3. Conventional 6T-SRAM
6T-SRAM cellcell with:
with: pullpull
up up (PU),
(PU), pullpull
downdown (PD)
(PD) andand pass
pass gate
gate (PG)
(PG) transistors.
transistors.

An SRAM cell can operate in three modes: hold, read and write. During the hold
Bit Line Conditioning
mode, the wordline (WL) signal is low; thus, the cell keeps the internal bit value. Before
a read or write operation, an initial conditioning circuit pre-charges the bitlines (BL and
Row Decoder

A0
BLB). During the read operation, the WL signal activates both PG transistors, providing
A1
access to the stored value. One of the BLs is consequently discharged through its respective
PG and PD transistors, while the other BL remains high. In this way, the SRAM cell puts
theA0stored bit and its inverse on the BLs. To discharge a BL, the corresponding PD transistor
Column Decoder
must
A1 be stronger than its respective PG transistor, known as read stability. Equation (1)
shows the relative strength of these transistors. CR values should be greater than one to
Sense Amplifier/
Write Driver
ensure the read operation. I/O Since a BL connects numerous cells, it has a high capacitive
value. Accordingly, discharging takes a considerable time. Hence, a sense amplifier is used
Figure 4. A 4 × 4 (16 bits) SRAM architecture for a complete operation as memory cell.
to magnify the small differential voltage between the BLs and transfers the bit value to the
external circuitry.
3. Low Voltage Operation (W/L)PD1 (W/L)PD2
Dynamic power contributes Cell Ratio (CR) =
a major constituent = total power (1)
(W/L)PG1in the(W/L )PG2 consumption of a
digital circuit. The integrants’ composition (αCfV ) is switching activity (α), switching
During the write operation, a strong write driver pulls one of the BLs down depending
frequency (f), node capacitance (C) and supply voltage (V ). The supply voltage is a
on which value is to be written onto the cell. The WL assertion takes time, as the increased
squared term that indicates the highest contribution. The tuning of parameters and
design density has put more capacitance on it. The BL Instantly pulls the storage node
affects the SRAM cell performance but increases the power budget. Technology advance-
down via a PG transistor, but a PU transistor opposes it. This imposes a constraint known
ment reduces capacitances (C), but the improved design density diminishes overall re-
as writability. The PG transistor must be stronger than the corresponding PU transistor to
turns.
copy the BL value into the SRAM cell. Equation (2) shows that the value of PR should be
Transistor downsizing leads to scale-downs in the supply voltage. T.H. Bao et al. [23]
less than one for the write operation.
reports feature sizes down to 5 nm as workable at the commercial scale. The international
roadmap for devices and systems (IRDS 2022)(W/L predicts
)PU1transistor
(W/Lscaling
)PU2 down to the 0.7 nm
node by 2034. However, size Ratio (PR) =brings forward
Pullminimization = obstacles (2)
(W/L)PG1 (W/L)PG2such as degraded sub-
threshold slopes (SSs) and increased drain-induced barrier lowering (DIBL) [24]. The SRAM
Thehas
cell design noise tolerance level,
consequently shiftedwithout upsetting
from planar devicesthetoundergoing operation,
fully depleted defines the
silicon-on-insula-
tornoise margin
(FDSOI) [25],for that particular
which permits anoperation.
acceptable The cell and pullasratios
performance, shownaffect the read
in Figure 5a.and write
In the
noise margins, respectively. Stronger PD and weaker PG transistors
future, sheet or gate-all-around (GAA) transistors [26] will replace the current FinFET in theensure a higher read
SRAMmargin,
cell whereas
design. stronger PG and weaker PU transistors improve the write margin. This
conflicting
Figure 5bdevice
explains sizingtheresults in a tradeoff
compromise between
on noise marginstheas
read
theand writevoltage
supply noise margins.
reduces. In
AnFinFET
SRAMtechnology, the device
cell can initially sizing
operate at a is
VDDmore challenging,
of 0.9 V and thenasatransistors’
decreasingwidth, represented
trend continues
to by
0.5 the number
V. The of fins,
threshold is quantized.
voltage (Vth) could not comparatively follow this trend at the same
pace. To measure static noise margins, the butterfly curve plot is used [20]. Since the butterfly
curve method is incapable of fast and automated measurements, industrial designers rely
on N-curves [21]. In N-curves, supply-read retention voltage (SRRV) and wordline-read
retention voltage (WRRV) render the read noise margin measurements. For the write noise
margin, bitline-write trip voltage (BWTV) and wordline-write trip voltage (WWTV) furnish
the write noise margin measurements [22]. Table 1 mentions details of key performance
evaluation parameters of an SRAM cell.
 13,x 1332
Micromachines 2022, 6, FOR PEER REVIEW 4 4ofof 23
22

Table 1.
Table Performance evaluation
1. Performance evaluation parameters
parameters for
for SRAM
SRAM cells.
cells.

S. No. S.Parameters
No. Parameters Explanation
Explanation
1 Read Access Time WL activation (50%) to 50–200 mV differential bitline voltage
1 Read Access 2 TimeWrite Access Time WL activation (50%)(50%)
WL activation to 50–200 mV differential
to 90%/10% bitline
of rising/falling voltage
internal node
2 Write Access 3 TimeRead/Write Power WL activation (50%) to 90%/10% of rising/falling
Power consumption during read/write access time internal node
3 Read/Write4 Power Leakage Power Power Power
consumption during
consumption read/write
during standby or access
hold time
mode
4 Leakage Power5 Cell Area Power Layout
consumption during
area of the standby
one SRAM cellor hold mode
5 Cell Area 6 Noise Margins LayoutSRAM
area ofnoise
the tolerance
one SRAM cell
under hold/read/write mode
6 Noise Margins7 Reliability SRAM Performance
noise toleranceunderunder hold/read/write mode variations
process/voltage/environmental
7 Reliability 8 Soft Error Performance
Criticalunder
chargeprocess/voltage/environmental
accumulation to flip the internal node variations
value
8 Soft Error Critical charge accumulation to flip the internal node value

VDD VDD
Wordline
The aforementioned conventional
Wordline
(W L) (W L)6T-SRAM cell necessitates the peripheral circuitry
for operational procedures. Figure 4 presents the main peripheral components: row and
PU2 PU1
Q Qb
columnPG2 decoders, sense amplifiers, PG1 bitline conditioning and write drivers. The exter-

Bitline (BLB)
(V2) (V1)
Bitline (BL)

nal components’PD2 performance PD1plays a crucial role in the overall memory design. For

example, amortization reduces the number of sense amplifiers required for an SRAM
cell array design [22]. Hence, an SRAM array achieves efficiency in design density and
power3.consumption.
Figure Conventional 6T-SRAM cell with: pull up (PU), pull down (PD) and pass gate (PG) transistors.

Bit Line Conditioning

Row Decoder

A0

A1

A0 Column Decoder
A1

Sense Amplifier/
Write Driver
I/O

A 44 ××44(16
Figure 4. A
Figure (16bits)
bits)SRAM
SRAMarchitecture
architecturefor
foraacomplete
completeoperation
operationas
asmemory
memorycell.
cell.

3. Low Voltage Operation

3. Low Voltage Operation
Dynamic power contributes a major constituent in the total power consumption of
Dynamic power contributes a major constituent in the total power consumption of a
a digital circuit. The integrants’ composition (αCfV2DD ) is switching activity (α), switch-
digital circuit. The integrants’ composition (αCfV ) is switching activity (α), switching
ing frequency (f), node capacitance (C) and supply voltage (V ). The supply voltage is
frequency (f), node capacitance (C) and supply voltage (V ).DDThe supply voltage is a
a squared term that indicates the highest contribution. The tuning of parameters α and f af-
squared term that indicates the highest contribution. The tuning of parameters and
fects the SRAM cell performance but increases the power budget. Technology advancement
affects the SRAM cell performance but increases the power budget. Technology advance-
reduces capacitances (C), but the improved design density diminishes overall returns.
ment reduces capacitances (C), but the improved design density diminishes overall re-
Transistor downsizing leads to scale-downs in the supply voltage. T.H. Bao et al. [23]
turns.
reports feature sizes down to 5 nm as workable at the commercial scale. The international
Transistor downsizing leads to scale-downs in the supply voltage. T.H. Bao et al. [23]
roadmap for devices and systems (IRDS 2022) predicts transistor scaling down to the 0.7 nm
reports feature sizes down to 5 nm as workable at the commercial scale. The international
node by 2034. However, size minimization brings forward obstacles such as degraded
roadmap for devices
sub-threshold slopesand systems
(SSs) (IRDS 2022)
and increased predicts transistor
drain-induced barrier scaling down
lowering to the
(DIBL) 0.7 The
[24]. nm
node by 2034. However, size minimization brings forward obstacles such as degraded
SRAM cell design has consequently shifted from planar devices to fully depleted silicon-on- sub-
threshold slopes (SSs)
insulator (FDSOI) [25],and increased
which permitsdrain-induced
an acceptablebarrier lowering
performance, as(DIBL)
shown[24]. The SRAM
in Figure 5a. In
cell design has consequently shifted from planar devices to fully depleted silicon-on-insula-
the future, sheet or gate-all-around (GAA) transistors [26] will replace the current FinFET
tor (FDSOI)
in the SRAM[25],cell which
design.permits an acceptable performance, as shown in Figure 5a. In the
future, sheet or gate-all-around (GAA) transistors
Figure 5b explains the compromise on noise[26] will replace
margins as thethe current
supply FinFET
voltage in the
reduces.
SRAM cell design.
An SRAM cell can initially operate at a VDD of 0.9 V and then a decreasing trend continues
to 0.5Figure
V. The5bthreshold
explains the compromise
voltage on noise
(Vth ) could margins as the follow
not comparatively supply this
voltage reduces.
trend at the
An
same SRAM
pace.cell can initially operate at a VDD of 0.9 V and then a decreasing trend continues
to 0.5 V. The threshold voltage (Vth) could not comparatively follow this trend at the same
pace.
Micromachines 2022, 6, x FOR PEER REVIEW 5 of 23
Micromachines 2022, 13, 1332 5 of 22

Voltage (V)
(a) (b)
Figure
Figure5.5.(a)(a)Gate
Gatelength
lengthevolution
evolutionofofapplication-specific
application-specificcircuit
circuitdesign
designfor
forlow
lowstandby
standbypower
power
(LSTP), low operational power (LOP) and high performance (HP). (b) Supply voltage and
(LSTP), low operational power (LOP) and high performance (HP). (b) Supply voltage and threshold threshold
voltage scaling decreasing the noise margin headroom. (ITRS).
voltage scaling decreasing the noise margin headroom. (ITRS).

3.1.
3.1.Alternate
AlternateCells
Cells
ToToovercome
overcomethe thelow
lowsupply
supplyvoltage
voltagechallenge,
challenge,designers
designershave haveput putforward
forwardmultiple
multiple
SRAM
SRAMcell designs
cell designs [26–31].
[26–31].Primarily,
Primarily,alternate
alternateSRAM cells cells
SRAM aim to improve
aim the noise
to improve themar-
noise
margins.
gins. EnhancedEnhanced noise margins
noise margins ensureensure a particular
a particular SRAM SRAM cell hascell has sufficient
sufficient stabilitystability
room
atroom at a decreased
a decreased supply supply
voltage.voltage.
Figure 6 highlights
Figure 6 highlights different differentSRAMSRAMcells cellsandandassociated
associatedcontrol
controlsignals.
signals.Without
Withoutloss loss
of generality,
of generality, the basic operation is similar in essence, as explained in
basic operation is similar in essence, as explained in Section 2. A 7T- Section 2. A 7T-SRAM
cell, ascell,
SRAM seenasin Figure
seen 6a, has6a,
in Figure a single read-bitline
has a single (RBL)(RBL)
read-bitline and read-wordline
and read-wordline (RWL)(RWL) for the
read
for theoperation. The newly
read operation. added added
The newly transistor M4 breaks
transistor M4 the back-to-back
breaks inverters’
the back-to-back feedback
inverters’
throughthrough
feedback the WL the signal
WLand signalimproves the write
and improves thenoise
writemargin. An 8T-SRAM
noise margin. An 8T-SRAM cell, ascell,
seen
in Figure 6b, separates the read-port (M7 and M8) to avoid device
as seen in Figure 6b, separates the read-port (M7 and M8) to avoid device size conflict and size conflict and thus,
this cell
thus, this can
cell independently
can independently tune tune
the read
the noise margin.
read noise Furthermore,
margin. Furthermore,a 9T-SRAMa 9T-SRAMcell, as
seen in Figure 6c, has a separate read and write port (M7, M8
cell, as seen in Figure 6c, has a separate read and write port (M7, M8 and M9). Addition- and M9). Additionally, this
cell has wordline pull-up (WLPU) and wordline pull-down
ally, this cell has wordline pull-up (WLPU) and wordline pull-down (WLPD) transistors (WLPD) transistors for the
power
for gatinggating
the power to save power.
to save Next,Next,
power. 10T-SRAM
10T-SRAM cells,cells,
as seen in Figure
as seen in Figure 6d,6d,manifest
manifest the
separate read and write port concepts as the same as 8T-SRAM
the separate read and write port concepts as the same as 8T-SRAM cells. But the M7, M8 cells. But the M7, M8 and
M9M9
and transistors’
transistors’buffer provides
buffer strong
provides logiclogic
strong for thefor0 the
or 10value. The addition
or 1 value. of M2, of
The addition M5M2,
and
M7, as seen in Figure 6e, is an alternate way to furnish the
M5 and M7, as seen in Figure 6e, is an alternate way to furnish the strong logic value.strong logic value. Transistors
(M9 and M10)
Transistors (M9 in and anM10)
11T-SRAM cell remove
in an 11T-SRAM cellinterdependency
remove interdependency between the read and
between write
the read
and write noise margins. Tri-state buffers for the read and write operations in a 12T-SRAMas
noise margins. Tri-state buffers for the read and write operations in a 12T-SRAM cell,
seen
cell, asin Figure
seen 6f, improve
in Figure the read-
6f, improve and write-energy
the read- and write-energy per cycle whilewhile
per cycle the read or write
the read or
operation is in progress.
write operation is in progress.
Table 2 reports the performance parameters analysis among Figure 6 cells. It is noted
that the proposed SRAM-design cells, with the extra transistors, enhance the area and put
VDD stringent requirements VDDthe layout regularity. Although the alternateWLPU
on cell designs show
WWL RWL WL WL M2 VDD
M3 M1 better read and write ability as compared with their WL WWL
counterparts, this is at the expense of
M3 M1 M3
M7 M1
M6
more control signals M5 and increasedM6 area.RWL
Adaptability and flexibility M7 to other components
___ M7 M9
WL
WBL C

M4 determine the overall efficiency of the specific SRAM cell design. M8

WBLT
WBL

RBL

M2 M6 M4
3.2. Assist-Circuits M4
BL

M2 M8
RBL

VSS
M5 M5
GND GND power but makes read and write operations GND
GND A lower supply voltage improves dynamic WLPD
challenging. Therefore, assist-circuits ensure an SRAM cell operations’ reliability. Two
(a) (b) (c)
circuit-level choices for a low voltage operation are the use of assist-circuits and adaptation
to alternate SRAM cells. Both options have tradeoffs at the cost of extra hardware and
control signals. In FinFET technologies, the 6T-SRAM cell utilization alongside assist-
circitry is inescapable to guarantee the high design density.
 and M9 transistors’ buffer provides strong logic for the 0 or 1 value. The addition of M2,
M5 and M7, as seen in Figure 6e, is an alternate way to furnish the strong logic value.
Transistors (M9 and M10) in an 11T-SRAM cell remove interdependency between the read
and write noise margins. Tri-state buffers for the read and write operations in a 12T-SRAM
Micromachines 2022, 13, 1332 cell, as seen in Figure 6f, improve the read- and write-energy per cycle while the read 6 ofor
22
write operation is in progress.

VDD VDD WLPU

WWL RWL WL WL M2 VDD
M3 M1 WL WWL
M3 M1 M3
M7 M1
M6 M5 M6 RWL M7
___ M7 M9

WBLC
WL
M4 M8
WBL

WBLT
RBL
M2 M6 M4

BL
M4

RBL
M2 M8 VSS
M52022, 6, x FOR PEER REVIEW
Micromachines M5 6 of 23
GND GND GND
GND WLPD

(a) (b) (c)

VDD
VDD VDD
VDD WL
WL Shared
WL RWL M4 M1 M5 M1
M3 M1 M7 M7
M8 WWL_B RWL_B
M5 M6 M10 M11 M9 M6 M2
WL WWL
WBL C

M8 M5 M2
WWL
W BL T

RWL
M9 M12 M10 M7 M3
RBL

M4 M11
M2 M9 WWL_B
SBL

M6 M3
GND

BL
GND VSS M10 Shared M8 M4
GND WWL GND

(d) (e) (f)

Figure 6.
Figure 6. Alternate
AlternateSRAMSRAM cellcell
designs for low
designs for voltage operation
low voltage using feedback
operation break, isolated
using feedback break,port,
isolated
power-gating, buffered values, read or write independency and concurrent read or write strategies.
port, power-gating, buffered values, read or write independency and concurrent read or write
(a) 7T-SRAM cell [26], (b) 8T-SRAM cell [27] (c) 9T-SRAM cell [28], (d) 10T-SRAM cell [29], (e) 11T-
strategies.
SRAM cell(a) 7T-SRAM
[30], cell [26],
(f) 12T-SRAM cell(b) 8T-SRAM cell [27] (c) 9T-SRAM cell [28], (d) 10T-SRAM cell [29],
[31].
(e) 11T-SRAM cell [30], (f) 12T-SRAM cell [31].
Table 2 reports the performance parameters analysis among Figure 6 cells. It is noted
Table 2. Performance
that the analysis of 6T-12T
proposed SRAM-design cells,SRAM
with cells. (Simulation
the extra in 65 enhance
transistors, nm CMOS at area
the nominal
andvoltage).
put
stringent requirements on the layout regularity. Although the alternate cell designs show
S. No Parameter
better6Tread and write
7T [26]
ability as8Tcompared
[27] 9T [28]
with 10T [29]
their counterparts, this 11T
is at[30] 12T [31]
the expense of
1 Area Overhead * 0% 16% 30% 43% 58% 71% 89%
2 Read Dynamic Power (µW) more16.85
control signals
25.48and increased
18.14 area. Adaptability
18.96 and23.73
flexibility to other
58.15 components73.1
3 Write Dynamic Power (µW) 24.31
determine 7.5 efficiency26.52
the overall 8.19
of the specific 27.49
SRAM cell design. 50.83 69.1
4 Leakage Power (nW) 5.6 5.3 5.98 6.13 5.99 2.26 7.69
5 Read Access Time (ps) 3.06 9.18 16.04 17.23 36.9 91.2 103.5
6 33.53 27.96 37.93 36.7
7
Write Access Time (ps)
Sensing Method Table 2. Performance
Differential Singleanalysis
Ended ofSingle
6T-12T SRAM cells.
Ended Single(Simulation
Ended in41.83
65Ended
Single nm CMOS 61.06
at
Single nominal 118.3
Ended voltage).
Single Ended
* Area
S. Noestimation using 65 nm design rules.
Parameter 6T 7T [26] 8T [27] 9T [28] 10T [29] 11T [30] 12T [31]
1 Area Overhead * 0% 16% 30% 43% 58% 71% 89%
2 AsRead Dynamic Power
illustrated (µW) 3, the
in Figure 16.85 25.48
conventional 18.14
6T-SRAM 18.96
cell is 23.73
connected 58.15to three
73.1 types
3 Write Dynamic Power (µW) 24.31 7.5 26.52 8.19 27.49 50.83 69.1
of control signals: voltage supplies (VDD and GND ), BLs and WLs. An assist-circuit raises
4 Leakage Power (nW) 5.6 5.3 5.98 6.13 5.99 2.26 7.69
or lowers
5 the signal voltage
Read Access Time (ps) level as per
3.06 the operational
9.18 16.04 mode.
17.23 Table 3
36.9 shows
91.2eight different
103.5
possible
6 combinations
Write of assist schemes
Access Time (ps) 33.53 [32].
27.96 37.93 36.7 41.83 61.06 118.3
Single Single Single Single Single Single
7 Sensing Method Differential
Table 3. Summary of assist scheme for read and Ended
write Ended Ended
at the low voltage.Ended Ended Ended
* Area estimation using 65 nm design rules.
S. No. Assist Scheme Type Overhead
3.2. Assist-Circuits
1 Negative BL (NBL) Write Coupling capacitor
2 Suppressed BLA (SBL)
lower supply voltage improves
Read dynamic power but makesdevices
Discharge read and write opera-
3 tions challenging.
WL overdrive (WLOD) Therefore, assist-circuits
Write ensure an SRAM
Chargecell operations’
pump and level reliability.
shifter
4 Two circuit-level
WL under-drive (WLUD) choices for a lowReadvoltage operation arePMOS
the use of assist-circuits
devices and ad-
and bias current
5 VDD boosting Readoptions have tradeoffs
aptation to alternate SRAM cells. Both Column MUX
at the cost of extra hardware
6 VDD lowering Write
and control signals. In FinFET technologies, the 6T-SRAM Pull-up and pull-down
cell utilization devices
alongside assist-
7 GND boosting
circitry is inescapable to guaranteeWrite External level shifter
the high design density.
8 GND loweringAs illustrated in Figure 3, the Read
conventional 6T-SRAM External level shifterto three types
cell is connected
of control signals: voltage supplies (VDD and GND), BLs and WLs. An assist-circuit raises
or lowers the signalbitline
In a negative voltage level as
(NBL), per the operational
a coupling mode.generates
capacitor (CC) Table 3 shows eight differ-
the negative voltage
ent possible combinations of assist schemes [32].
on a BL to aid in flipping the cell value. However, the charging and discharging of CC
as an additional component raises the overall power consumption [32]. Recently, TSMC
Table 3. Summary
proposed of assist
the design scheme for
technology andread and write at the (DTCO)
co-optimization low voltage.
[33] for the generation of CC
using the BL-length Assist
S. No. adjustment,
Scheme optimizing theTypeoperational voltage by 300 mV at the 5 nm
Overhead
node.1 Next, the suppressed
Negative BL (NBL) bitline (SBL), instead
Write of pre-charging
Coupling capacitor BLs to the VDD level,
2 Suppressed BL (SBL) Read Discharge devices
3 WL overdrive (WLOD) Write Charge pump and level shifter
4 WL under-drive (WLUD) Read PMOS devices and bias current
5 VDD boosting Read Column MUX
6 VDD lowering Write Pull-up and pull-down devices
7 GND boosting Write External level shifter
 become stronger and assist in the write operation. However, the gate oxide comes under
stress because of the high voltage level. Opposite to WLOD, wordline under-drive
(WLUD) assists by weakening the PG transistors (WL voltage lowering). For boosting VDD,
a column MUX helps to choose the desired level. Extra power line grids and pads incur
more area and delay penalty. Enhanced VDD aids in putting the internal node value onto
Micromachines 2022, 13, 1332 7 of 22
BLs faster, whereas the VDD lowering helps in flipping the stored value of the SRAM cell.
PMOS devices along biasing current circuits achieve adjustments in the dynamic supply
voltage. The last two schemes in Table 3 raise or lower the ground level, but the GND rail
discharges
sharing among BLs to allthe intermediate
of the SRAM cells voltage. The lower voltage level discharge ascertains
is challenging.
read operation
Researchers have also used combinations ofover-drive
assistance. Furthermore, wordline (WLOD)
multiple assist needssuch
schemes to use
as aSBL
charge
and
pump and biasing circuitry to achieve a higher voltage level. The
NBL; and dual-transient wordline (DTWL) [34]. The underlying strategy is to segregate PG transistors become
stronger andsignal
each control assist (WL,
in theBL,write
VDDoperation.
and GND) and However,
then apply the gate oxide comes
an increased under stress
or decreased volt-
because of the high voltage level. Opposite to WLOD, wordline under-drive
age level on each of these signals to perform low power read and write operations [35,36]. (WLUD) assists
by weakening
Transient the PG
voltage transistors
collapse (TVC) (WL(VDDvoltage lowering).
lowering) Forstepped
[37,38], boostingWL VDD , a column
(WLUD) [37]MUX
and
helps to choose the desired level. Extra power line grids and pads incur more area and delay
dual write driver [39] assist low voltage operations. Before target application information,
penalty. Enhanced VDD aids in putting the internal node value onto BLs faster, whereas the
low power (LP), high density (HD) or high performance (HP) enables circuit designers to
VDD lowering helps in flipping the stored value of the SRAM cell. PMOS devices along
set the transistors’ strength to effectively achieve the design’s goal.
biasing current circuits achieve adjustments in the dynamic supply voltage. The last two
schemes in Table 3 raise or lower the ground level, but the GND rail sharing among all of
3.3. Device Structure
the SRAM cells is challenging.
Innovation inhave
Researchers device structure
also is another option
used combinations to operate
of multiple SRAM
assist cells atsuch
schemes a lower
as SBLvoltage.
and
Two classes of device structure modifications are available: the back
NBL; and dual-transient wordline (DTWL) [34]. The underlying strategy is to segregate each end of line (BEOL) and
front end of line (FEOL). Figures 7 and 8 show one structure from each
control signal (WL, BL, VDD and GND ) and then apply an increased or decreased voltage class as a representative
model.
level on each of these signals to perform low power read and write operations [35,36].
Negative
Transient voltagecapacitance
collapse (NC)
(TVC)[40] in FinFET-SRAM
(VDD lowering) [37,38], cellsstepped
providesWL better
(WLUD)noise margins.
[37] and
Insertion of the ferroelectric material between two gate metal layers,
dual write driver [39] assist low voltage operations. Before target application information, as shown in Figure
7, creates
low powerNC. The
(LP), applied
high densitygate voltage
(HD) polarizes
or high the ferroelectric
performance (HP) enablesdielectric
circuitthat amplifies
designers to
thethe
set gate voltage atstrength
transistors’ the second gate metal
to effectively layer underneath
achieve the design’s thegoal.dielectric material. This
improves the ION/IOFF ratio, leading to better SS and DIBL. The thickness and composition
3.3. Device
of the Structure
dielectric material are a tradeoff with the read and write performance.
The second
Innovation in type of device
device structure
structure is illustrated
is another option to inoperate
Figure 8. It is acells
SRAM tunnel
at aFinFET
lower
(TFET) with
voltage. Twoboth terminals,
classes of device source and drain,
structure joined through
modifications an intrinsic
are available: the channel
back end[41] and
of line
has a doping
(BEOL) of opposite
and front end of linepolarities.
(FEOL).Such transformation
Figures 7 and 8 showimproves the sub-threshold
one structure from each classfac- as
ator (KT/q) and gate-work
representative model. function to support the low voltage operation down to 0.3 V.

Micromachines 2022, 6, x FOR PEER REVIEW 8 of 23

Figure 7.
Figure 7. Negative capacitance-based
capacitance-based FinFET
FinFET with
with ferroelectric
ferroelectric layer
layer as
as dielectric
dielectric [40].
[40].

Figure 8. TFET structure: a cross-section showing doping levels [41].

Negative
4. Leakage capacitance (NC) [40] in FinFET-SRAM cells provides better noise margins.
Current
Insertion of the ferroelectric material between two gate metal layers, as shown in Figure 7,
Technological node scaling has improved the design density; subsequently, a greater
creates NC. The applied gate voltage polarizes the ferroelectric dielectric that amplifies
number of transistors on the same IC area result in a considerable increase in leakage
the gate voltage at the second gate metal layer underneath the dielectric material. This
power. Now leakage current constitutes a significant portion of the overall power budget.
improves the ION /IOFF ratio, leading to better SS and DIBL. The thickness and composition
A modern transistor exhibits three leakage currents: the tunneling current between
of the dielectric material are a tradeoff with the read and write performance.
conduction channel and gate, PN junction or body leakage current between source and
The second type of device structure is illustrated in Figure 8. It is a tunnel FinFET
drain and body interface, and the sub-threshold conduction current between the source
(TFET) with both terminals, source and drain, joined through an intrinsic channel [41] and
and drain under sub-threshold voltages due to DIBL and GIDL [10]. However, the body
has a doping of opposite polarities. Such transformation improves the sub-threshold factor
leakage current is no longer a serious concern in modern technologies, as SOI [11] has
(KT/q) and gate-work function to support the low voltage operation down to 0.3 V.
reduced the junction leakage magnitude. Considering Figure 3, assume the SRAM cell
stores ‘1′, meaning the node Q is at a logic of ‘1′, whereas the node Qb is at a logic of ‘0′,
and both BLs are pre-charged. Under this condition, transistors (PU1, PG1 and PD2) suffer
from sub-threshold leakage. Three transistors (PU2, PG2 and PD1) will face the sub-threshold
leakage in case an internal node stores the ‘0′ value, thus confirming unavoidable leakage in
either case.
Micromachines 2022, 13, 1332 8 of 22

4. Leakage Current
Technological node scaling has improved the design density; subsequently, a greater
number of transistors on the same IC area result in a considerable increase in leakage power.
Now leakage current constitutes a significant portion of the overall power budget.
A modern transistor exhibits three leakage currents: the tunneling current between
conduction channel and gate, PN junction or body leakage current between source and
drain and body interface, and the sub-threshold conduction current between the source
and drain under sub-threshold voltages due to DIBL and GIDL [10]. However, the body
leakage current is no longer a serious concern in modern technologies, as SOI [11] has
reduced the junction leakage magnitude. Considering Figure 3, assume the SRAM cell
stores ‘1’, meaning the node Q is at a logic of ‘1’, whereas the node Qb is at a logic of ‘0’, and
both BLs are pre-charged. Under this condition, transistors (PU1, PG1 and PD2) suffer from
sub-threshold leakage. Three transistors (PU2, PG2 and PD1) will face the sub-threshold
leakage in case an internal node stores the ‘0’ value, thus confirming unavoidable leakage
in either case.

4.1. Bitline Leakage

Bitlines leak current through PG transistors. An approach to reduce this leakage is
by the BLs’ initial condition. The assist-circuits presented in Section 3, such as NBL and
SBL, reduce the leakage as well [42]. In both assist schemes, the voltage on BL is less than
VDD ; hence, the leakage current subsides. Likewise, the WLUD-assist scheme reduces the
leakage current from the internal nodes towards BLs. VDD lowering similarly decreases
both power consumption components, i.e., dynamic and leakage. The assist schemes in
Table 3 minimize leakage currents except in the lowering of GND , boosting of the VDD
and WLOD schemes. These schemes widen the rail-to-rail potential difference, eventually
increasing the leakage current.

4.2. Asymmetric Cells

The multi-threshold SRAM cell design minimizes the leakage current by choosing
‘0’ or ‘1’ as the preferential state. Each logic state associated with a leakage current has
already been explained above (Section 4). Leaky transistors are set to a high threshold
value (hvt) to reduce the leakage [43]. This approach, as seen in Figure 9a, reduces the
leakage about 70 times by choosing ‘1’ as its preferential state, but at the cost of a degraded
read ability. The SRAM cell in Figure 9b provides 1.6 and 70 times less leakage current for
selecting ‘1’ and ‘0’, respectively, as preferential states. This asymmetry causes an increase
Micromachines 2022, 6, x FOR PEER REVIEW 9 of 23
in write delay. Next, the SRAM cell in Figure 10c reduces the leakage current about seven
times for the ‘0’ state but compromises the read and write noise margins.

VDD
WL WL
hvt hvt
P1 P2 hvt
Q Qb N4
N3
Bitline (BLB)
Bitline (BL)

N1 N2
hvt hvt
GND

(a) (b) (c)

Figure
Figure9.9.Asymmetrical
Asymmetrical6T 6TSRAM
SRAMcells
cellsfor
forleakage
leakagereduction
reductionusing
usingpreferential
preferentialstate
stateand
andmulti-
multi-
threshold
thresholdvoltage
voltage[43].
[43].(a)
(a)Asymmetric:
Asymmetric:‘1′‘1’asaspreferential
preferentialstate;
state;(b)
(b)asymmetric:
asymmetric:‘0′
‘0’as
aspreferential
preferential
state;
state;(c)
(c)asymmetric
asymmetricleakage
leakageoptimization.
optimization.

4.3. Alternate
GhasemSRAM Cellsproposed the SRAM cell size variation in combination with multi-
et al. [44]
threshold voltage designs
The conventional 6T-SRAM at the architectural level.stability
cell suffers from SRAM issues,
cells in especially
the same row exhibit
in FinFET
multiple delays, i.e., cells farther from the row driver have more delays
technology. Researchers have explored more than 6T-SRAM cells to reduce the leakage and vice versa.
A row decoder drives longer wires and more capacitance for the SRAM cells placed
current. We have already illustrated some configurations in Figure 6. Table 2 provides detailstowards
of each SRAM cell leakage power. The 7T-SRAM and 8T-SRAM cells show comparable leak-
age power to the 6T cell since transistor stacking reduces the leakage current. In the case of
11T-SRAM cells, the leakage value significantly reduces due to transistor stacking in both feed-
back inverters.
 4.4. Power Control
Additional transistors along the control signals in an SRAM cell can cut off the power.
One approach is to power-gate a few transistors in a cell, as shown in Figure 6c. Two other
mechanisms are controlling the ground node through internal components [45] and ex-
Micromachines 2022, 13, 1332 ternal signals [46]. Architectural level power gating reduces leakage drastically [47]. 9 of 22
Figure 10a demonstrates the first mechanism; the WL signal controls the connection
to the ground through transistor N5, and the internal diode prevents internal node flip-
ping the
by raising
end of the ground
a row. Hence,node
thelevel.
speedFigure 10b,
of cells as representative
located towards theofend
theof
second mecha-
the row is slower.
nism,The
provides
use of multi-Vth has improved not only the delay but also the leakage of theVoverall
a stringent grip over the leakage as compared with Figure 10a. High th

and ground-level
SRAM array. control transistors manage the leakage current but cost extra signals.

(a) (b)
Figure 10. Leakage
Figure controlcontrol
10. Leakage mechanisms for SRAM
mechanisms cells using
for SRAM cellsinternal components
using internal and external
components and external
control signals for raised ground levels [45,46]. (a) SRAM cell with virtual ground; (b) asymmetric
control signals for raised ground levels [45,46]. (a) SRAM cell with virtual ground; (b) asymmetric
SRAM cell with
SRAM cell virtual ground.
with virtual ground.

4.3. Alternate
4.5. Body Biasing SRAM Cells
The conventional
To improve 6T-SRAM
the performance andcell suffers
leakage from stability
currents, issues, especially
two prevalent in FinFET
body biasing mech- tech-
anismsnology. Researchers
are forward bodyhave explored
biasing (FBB)more than 6T-SRAM
and reverse cells to(RBB).
body biasing reduceThe
the SRAM
leakagecell
current.
We have
[48] shown inalready
Figure illustrated
11 exploitssome
both configurations in Figure
techniques through N5 6. Table
and N6 2transistors
provides details of each
with the
SRAM cell leakage power. The 7T-SRAM and 8T-SRAM cells show comparable
external control signal ‘ctrl.’ Two transistors, N5 and N6, select voltage levels of ‘-1′ and leakage
power to theto6T
‘0′, respectively, cell since
utilize RBB.transistor
In modernstacking
FinFETreduces the leakage
technology, SOI hascurrent. In the
eliminated case of
body
biasing. However, FinFET-independent gates (IG) biasing IGFET [49] offers a modulation both
11T-SRAM cells, the leakage value significantly reduces due to transistor stacking in
of thefeedback
thresholdinverters.
voltage to subside the leakage current.
4.4. Power Control
Additional transistors along the control signals in an SRAM cell can cut off the power.
One approach is to power-gate a few transistors in a cell, as shown in Figure 6c. Two
other mechanisms are controlling the ground node through internal components [45] and
external signals [46]. Architectural level power gating reduces leakage drastically [47].
Figure 10a demonstrates the first mechanism; the WL signal controls the connection to
the ground through transistor N5, and the internal diode prevents internal node flipping
by raising the ground node level. Figure 10b, as representative of the second mechanism,
provides a stringent grip over the leakage as compared with Figure 10a. High Vth and
ground-level control transistors manage the leakage current but cost extra signals.

4.5. Body Biasing

To improve the performance and leakage currents, two prevalent body biasing mecha-
nisms are forward body biasing (FBB) and reverse body biasing (RBB). The SRAM cell [48]
shown in Figure 11 exploits both techniques through N5 and N6 transistors with the ex-
ternal control signal ‘ctrl.’ Two transistors, N5 and N6, select voltage levels of ‘-10 and ‘0’,
respectively, to utilize RBB. In modern FinFET technology, SOI has eliminated body biasing.
However, FinFET-independent gates (IG) biasing IGFET [49] offers a modulation of the
threshold voltage to subside the leakage current.

4.6. Novel Devices

First, graphene nano-ribbon FET (GNRFET) holds excellent conducting properties [50]
due to un-doped GNR channels underneath the gate (reduces leakage) and highly doped
GNR channels between the gate and source and drain terminals. Figure 12 (FEOL) shows
the ribbon-shape structure of the GNRFET.
Micromachines 2022,
Micromachines 2022, 13,
6, x1332
FOR PEER REVIEW 10
10 of 23
of 22
Figure 11. SRAM cell with body biasing control circuit [48].

4.6. Novel Devices

First, graphene nano-ribbon FET (GNRFET) holds excellent conducting properties
[50] due to un-doped GNR channels underneath the gate (reduces leakage) and highly
doped GNR channels between the gate and source and drain terminals. Figure 12 (FEOL)
Figure
shows11.the SRAM cell with body
ribbon-shape biasingofcontrol
structure circuit [48].
the GNRFET.
Figure 11. SRAM cell with body biasing control circuit [48].
Another device structure [51], shown in Figure 13, shows improved off-state perfor-
4.6. Novelfor
mance Devices
the correlated-material (CM) (or hyper FET) SRAM cell. CM-FET performs the
4.6. Novel Devices
transition from the nano-ribbon
First, graphene insulator to metal (ITM) andholds
FET (GNRFET) then back fromconducting
excellent the metal to insulator
properties
First, graphene nano-ribbon FET (GNRFET) holds excellent conducting properties
(MTI).
[50] dueThe hysteresisGNR
to un-doped curvechannels
in Figure 14 demonstrates
underneath the gatethe transitions
(reduces of ITM
leakage) andand MTI
highly
[50] due to un-doped GNR channels underneath the gate (reduces leakage) and highly
from 0.20
doped GNRVchannels
to 0.27 V.between
Th on-current
the gate of and
CM-FET sourceand andFinFET
drainare comparable;
terminals. Figurehowever,
12 (FEOL)the
doped11.
Figure
Figure GNR
11. SRAM channels
cell withbetween
body the gate
body biasing
biasing controlandcircuit
control source
circuit and drain terminals. Figure 12 (FEOL)
[48].
[48].
off-current
shows of CM-FET is
the ribbon-shape substantially
structure of thelower.
GNRFET.
shows the ribbon-shape structure of the GNRFET.
Another device structure [51], shown in Figure 13, shows improved off-state perfor-
4.6. Novel
AnotherDevices
device structure [51], shown in Figure 13, shows improved off-state perfor-
mance for the correlated-material (CM) (or hyper FET) SRAM cell. CM-FET performs the
mance for the
First,from correlated-material
graphene nano-ribbon (CM)(GNRFET)
FET (or hyper FET) holdsSRAM cell.conducting
excellent CM-FET performs the
properties
transition the insulator to metal (ITM) and then back from the metal to insulator
transition
[50] due from the insulator to metalunderneath
(ITM) and the thengate
back from the metal to insulator
(MTI). Thetohysteresis
un-doped GNRinchannels
curve Figure 14 demonstrates (reduces
the transitions leakage)
of ITM and
and highly
MTI
(MTI). GNR
doped The hysteresis
channels curve inthe
between Figure
gate 14 demonstrates
and source and the transitions
drain terminals. of ITM12and
Figure MTI
(FEOL)
from 0.20 V to 0.27 V. Th on-current of CM-FET and FinFET are comparable; however, the
from 0.20
shows theof V to 0.27
ribbon-shape V. Th on-current
structure of theof CM-FET
GNRFET. and FinFET are comparable; however, the
off-current CM-FET is substantially lower.
off-current of CM-FET is substantially lower.
Another device structure [51], shown in Figure 13, shows improved off-state perfor-
mance for the correlated-material (CM) (or hyper FET) SRAM cell. CM-FET performs the
transition
Figure from thenano-ribbon
12. Graphene insulator to metal of
structure (ITM)
FinFETand then back from the metal to insulator
[50].
(MTI). The hysteresis curve in Figure 14 demonstrates the transitions of ITM and MTI
fromAnother
0.20 V todevice V.structure
0.27VDD [51], shown
Th on-current of CM-FET in Figure 13, shows
and FinFET are improved
comparable; off-state
however,perfor-
the
WL WL
mance for the
off-current of correlated-material
CM-FET is (CM)
substantially
P1
(or
lower. hyper FET) SRAM cell. CM-FET performs the
P2
transition
N4
from the insulator to metal N3
(ITM) and then back from the metal to insulator
(MTI). The hysteresis curve in Figure 14 demonstrates the transitions of ITM and MTI
Bitline (BL)

Bitline (BLB)

from 0.20 N2 N1
V to 0.27 V. Th on-current of CM-FET and FinFET are comparable; however, the
Figure 12. Graphene nano-ribbon structure of FinFET [50].
off-current
FigureCM2 of CM-FET
12. Graphene is substantially
nano-ribbon structure
CM1 lower.
of FinFET [50].
GND
VDD
WL VDD WL
WL WL
P2 P1
Figure
N4
13. Correlated
P2 material-based
P1
N3
6T-SRAM cell [51].
N4 N3
Bitline (BL)

Bitline (BLB)
Bitline (BL)

Bitline (BLB)

N2 N1
Figure 12. Graphene
N2 nano-ribbon
N1 structure of FinFET [50].
CM2 CM1
CM2 GND
VDD CM1
WL GND WL
-6
1x10 P2 P1
N4 13. Correlated material-based 6T-SRAM
Figure N3 cell [51].
Id(A)

Figure13.
Figure 13. Correlated
Correlatedmaterial-based
material-based
CM-FET 6T-SRAM
6T-SRAM cell
cell [51].
[51].
Bitline (BL)

Bitline (BLB)

N2 N1
-8
1x10
CM2 CM1
GND

-6
1x10 -60 0.1 0.2 0.3 0.4
Figure
1x10 13. Correlated material-based 6T-SRAM cell [51].
Vgs(V)
Id(A)

CM-FET
Id(A)

Figure 14. HFET &FinFETCM-FET

transition between ON and OFF states [51].
-8
1x10 -8
1x10

-6
1x10 0.1 0.2 0.3 0.4
0
0 0.1 0.2
Vgs(V) 0.3 0.4
Id(A)

Vgs(V) CM-FET
Figure14.
Figure HFET&FinFET
14.HFET &FinFETtransition
transitionbetween
betweenON
ONand
andOFF
OFFstates
states[51].
[51].
Figure
-8 14. HFET &FinFET transition between ON and OFF states [51].
1x10
5. Process and Environmental Variations
5.1. Process Variations
In
0 modern
0.1 technology,
0.2 0.3 variations
0.4 in parameters characterizing the device performance
Vgs(V)
are comparable with their nominal values. Some device instances show different perfor-
mances,
Figure 14.and
HFET they sometimes
&FinFET are unable
transition betweento
ONmeet
andspecifications.
OFF states [51]. Nevertheless, a degree of
 5. Process and Environmental Variations
5.1. Process Variations
Micromachines 2022, 13, 1332 In modern technology, variations in parameters characterizing the device perfor- 11 of 22
mance are comparable with their nominal values. Some device instances show different
performances, and they sometimes are unable to meet specifications. Nevertheless, a de-
gree of uncertainty
uncertainty in performance
in performance exists.exists.
FinFET FinFET smaller
smaller size affects
size affects manufacturing
manufacturing yield yield
owing
owing to the process variations.
to the process variations.
Figure
Figure1515presents
presentscategories
categoriesofofprocess
processvariations:
variations:lot-to-lot
lot-to-lot(L2L),
(L2L),wafer-to-wafer
wafer-to-wafer
(W2W),
(W2W), die-to-die (D2D) and inter- or within-die (WID) variations.The
die-to-die (D2D) and inter- or within-die (WID) variations. TheL2L
L2LandandW2W
W2W
variations
variationsprevail
prevailwithin
within different lots of
different lots of the
thecylindrical
cylindricalsilicon
siliconboules
boules and
and circular
circular sili-
silicides
cides of the
of the samesame boule,
boule, respectively.
respectively. TheL2L
The L2Land
andW2W
W2W effects
effects on
on the
thecircuit
circuitperformance
performance
are
aregenerally
generallyminute;
minute;therefore,
therefore,they
theyareareignored
ignoredquite
quiteoften.
often.However,
However,D2D D2Dvariations
variations
influence device parameters on different dies belonging to the same
influence device parameters on different dies belonging to the same wafer. wafer.

Figure 15. Process variations in the deep sub-Micron and FinFETs [8,52].
Figure 15. Process variations in the deep sub-Micron and FinFETs [8,52].
The systematic (WID) variations [52] are usually caused by some anomaly in the
The during
system systematic (WID)
the mass variationsprocess,
production [52] arewhile
usuallythecaused
random by(WID)
some variations
anomaly in the
are sys-
a direct
tem during the mass production process, while the random (WID) variations
result of the random behaviors in recent technological nodes. These variations are in- are a direct
result of theand
scrutable random
requirebehaviors indistribution
statistical recent technological nodes. These variations
for their characterization. are inscru-
First, dopant atoms
table and require statistical distribution for their characterization. First, dopant
give rise to the phenomenon of random dopant fluctuation (RDF). Second, the gate pattern- atoms give
rise to the phenomenon of random dopant fluctuation (RDF). Second, the
ing has not been smooth and straight in modern feature-length sizes, referred to as the linegate patterning
has
edgenotroughness
been smooth and straight
(LER). Equation in(3)
modern
showsfeature-length
variations in sizes, referred to
the threshold as the line
voltage, where edgeq is
roughness (LER). Equation (3) shows variations in the threshold voltage, where
the charge; εsi and εox are the permittivity values of silicon and gate oxide, respectively; q is the charge;
ε Nand ε are the permittivity values of silicon and gate oxide, respectively; N is the do-
a is the dopant concentration; ΦB is the energy level of inter-potential bands; tox is the
pant concentration;
gate oxide thickness; Φ Wisandthe Lenergy
are thelevel of inter-potential
channel bands;
width and length, t is the gate oxide
respectively.
thickness; W and L are the channel width q and length, respectively.

tox 1
σVth = 4 2q3 εsi Na ΦB t √1 (3)
σ = ( 2q ε N Φ ) εox 3WL (3)
ε √3WL
FinFET
FinFET technology
technology withwith moderate
moderate dopingdoping inside
inside the the shows
channel channel fewershows fewer
Vth varia-
V
tions variations [53]. But Fin geometrical dimensions and quantized
th [53]. But Fin geometrical dimensions and quantized natures still show the Vth varia- natures still show
the V
tions for variations for the SRAM cell design. Figure 16 [54] shows variations
th the SRAM cell design. Figure 16 [54] shows variations in DIBL, whose sequel is in DIBL, whose
sequel
the is the Vth variations.
Vth variations. Equation (4) Equation
describes (4)the
describes the interdependency
interdependency of DIBL and of DIBL
Vth. Theandpa- Vth .
The parameter
rameter V represents the intended value of the threshold voltage, whereas V is theis
V th∞ represents the intended value of the threshold voltage, whereas V th
the actual
actual value. value.
Vth = Vth∞ − SCE − DIBL (4)
V =V − SCE − DIBL (4)
Process variations pose challenges to reduced noise margins, stability and malfunc-
tioning. Solutions such as assist-schemes, alternate cell designs and novel device structures
are not sufficient. Hence, architectural level remedies substitute the faulty SRAM cells to
ensure a workable memory array.
A. Redundant rows and columns: The introduction of extra SRAM cells avoids failure
because of the process variations. Faulty cells can be replaced in two ways. One way is to
switch from a failed SRAM sub-array to a redundant sub-array, irrespective of the number
of defective rows and columns. Otherwise, an extra row and column of cells can substitute
only failed rows and columns. However, the re-routing of redundant SRAM cells needs
complex control signals and address generations that boost the area overhead, the faulty
cells recovery yield, and the switching timing penalty.
 6, x1332
Micromachines 2022, 13, FOR PEER REVIEW 1212of
of 23
22

Figure 16. DIBL in bulk fully depleted silicon on insulator (FDSOI) and FinFET [54].

Process variations pose challenges to reduced noise margins, stability and malfunc-
tioning. Solutions such as assist-schemes, alternate cell designs and novel device struc-
tures are not sufficient. Hence, architectural level remedies substitute the faulty SRAM
cells to ensure a workable memory array.
A. Redundant rows and columns: The introduction of extra SRAM cells avoids failure
because of the process variations. Faulty cells can be replaced in two ways. One way is to
switch from a failed SRAM sub-array to a redundant sub-array, irrespective of the number
of defective rows and columns. Otherwise, an extra row and column of cells can substitute
only failed rows and columns. However, the re-routing of redundant SRAM cells needs
complex
Figure 16. control signals
DIBL in bulk and
fully address
depleted generations
silicon that
on insulator boost and
(FDSOI) the area
FinFET overhead,
[54]. the faulty
cells recovery yield, and the switching timing penalty.
The
The technique
Process technique proposed
proposed
variations in
in [55]
[55] uses
pose challenges uses aa master-slave
master-slave
to reduced latch
latch instead
noise margins, instead of
stabilityof extra rows
rows of
extramalfunc-
and of
SRAM
SRAM cells.
cells. Figure
Figure 17
17 illustrates
illustrates the
the flip-flop
flip-flop redundancy
redundancy technique.
technique.
tioning. Solutions such as assist-schemes, alternate cell designs and novel device struc- Here,
Here, the
the redundant
redundant
row
row of
tures of flip-flops,
are comparator
a comparator
not sufficient. Hence, andandMUXMUXare
architectural arelevel
theextra
the extra hardware
hardware
remedies components.
components.
substitute the faulty During
During
SRAM an
an operation,
operation, a a comparator
comparator compares
compares
cells to ensure a workable memory array. both
both addresses,
addresses, i.e.,
i.e., regular
regular and
and faulty.
faulty. If they match,
then the
thenA. control
controlsignals
theRedundant rowsdivert
signals divertthe
thepath
and columns: to
pathThetothe
the redundant
redundantof
introduction flip-flops
flip-flops
extra SRAM totoavoid
cellsfaulty
avoid faultycells.
avoids cells.
failure
because of the process variations. Faulty cells can be replaced in two ways. One way is to
switch from a failed SRAM sub-array to a redundant sub-array, irrespective of the number
of defective rows and columns. Otherwise, an extra row and column of cells can substitute
only failed rows and columns. However, the re-routing of redundant SRAM cells needs
complex control signals and address generations that boost the area overhead, the faulty
cells recovery yield, and the switching timing penalty.
The technique proposed in [55] uses a master-slave latch instead of extra rows of
SRAM cells. Figure 17 illustrates the flip-flop redundancy technique. Here, the redundant
row of flip-flops, a comparator and MUX are the extra hardware components. During an
operation, a comparator compares both addresses, i.e., regular and faulty. If they match,
then the control signals divert the path to the redundant flip-flops to avoid faulty cells.

Figure 17. Architecture of row redundancy scheme using flip-flops [55].

Figure 17. Architecture of row redundancy scheme using flip-flops [55].
B. Dynamic cache resizing: Built-in-self-tests (BISTs) together with dynamic caches
bypass B. the
Dynamic cache resizing:
faulty locations Built-in-self-tests (BISTs)improves
[56]. Defective-cell-avoidance together thewithSRAMdynamic
chipcaches
yield
bypass the faulty locations [56]. Defective-cell-avoidance improves
and tradeoffs with the performance. Figure 18 shows the architecture of a re-sizable the SRAM chipcache.
yield
and tradeoffs
Data with the
arrays contain performance.
a sea of SRAM Figurecells. A18tag-array-block
shows the architecture of a re-sizable
determines cache.
the location of
Data
the arraysdata
SRAM contain
arraya sea
(hit of
way)SRAM cells.
to be A tag-array-block
accessed, using the tag determines
and indexthe location of the
information. In
SRAM data
addition, thearray
state(hit way)
array to be accessed,
validates usingtag.
a particular the The
tag and indexarchitecture
resizable information.contains
In addi-
tion, the state array validates a particular tag. The resizable architecture
an extra masking bit in the state array, providing information on whether an accessed contains an extra
maskingisbit
location in the
faulty or state
not. array, providing information on whether an accessed location is
faulty or not. BIST architecture tests the whole data array and retrieves the faulty SRAM
Moreover,
cells. To maintain a cache’s performance, the system immediately performs BISTs after
turning
Figure 17.on the power.of Once
Architecture the number
row redundancy of faulty
scheme usingcells exceeds
flip-flops [55]. the threshold value, the
cache becomes unusable.
C. Dynamic
B. Reprogrammable Redundancy:
cache resizing: The SRAM
Built-in-self-tests hardware
(BISTs) run-time
together reconfiguration
with dynamic caches
bypass the faulty locations [56]. Defective-cell-avoidance improves the SRAM chipshows
makes it robust, as it is applicable even after SRAM-chip testing. Figure 19a [57] yield
dynamic
and column
tradeoffs withredundancy
the performance. (DCR). A spare
Figure column
18 shows theisarchitecture
inserted with of athe SRAM’scache.
re-sizable data.
A DCR contains two-way multiplexers. A memory controller dynamically
Data arrays contain a sea of SRAM cells. A tag-array-block determines the location of the assigns them
according
SRAM data to array
fault occurrence
(hit way) toinbe anaccessed,
SRAM array. usingInternal
the tagredundancy access (RA) re-routes
and index information. In addi-
the redundant column cell to the faulty location. Tag SRAM
tion, the state array validates a particular tag. The resizable architecture containscells hold RA information
an extra
and subsequently share across all lines once a fault occurs. DCR
masking bit in the state array, providing information on whether an accessed location offers minimum area
is
and timing
faulty or not. overhead as compared with the technique where redundant rows substitute
an entire faulty sub-array.
 6, x1332
Micromachines 2022, 13, FOR PEER REVIEW 1313of
of 23
22

Figure 18. Runtime re-sizeable cache architecture [56].

Moreover, BIST architecture tests the whole data array and retrieves the faulty SRAM
cells. To maintain a cache’s performance, the system immediately performs BISTs after
turning on the power. Once the number of faulty cells exceeds the threshold value, the
cache becomes unusable.
C. Reprogrammable Redundancy: The SRAM hardware run-time reconfiguration
makes it robust, as it is applicable even after SRAM-chip testing. Figure 19a [57] shows
dynamic column redundancy (DCR). A spare column is inserted with the SRAM’s data.
A DCR contains two-way multiplexers. A memory controller dynamically assigns them
according to fault occurrence in an SRAM array. Internal redundancy access (RA) re-
routes the redundant column cell to the faulty location. Tag SRAM cells hold RA infor-
mation and subsequently share across all lines once a fault occurs. DCR offers minimum
area and timing overhead as compared with the technique where redundant rows substi-
tute an entire
Figure faultyre-sizeable
18. Runtime sub-array.cache architecture [56].

Moreover, BIST architecture tests the whole data array and retrieves the faulty SRAM
cells. To maintain a cache’s performance, the system immediately performs BISTs after
turning on the power. Once the number of faulty cells exceeds the threshold value, the
cache becomes unusable.
C. Reprogrammable Redundancy: The SRAM hardware run-time reconfiguration
makes it robust, as it is applicable even after SRAM-chip testing. Figure 19a [57] shows
dynamic column redundancy (DCR). A spare column is inserted with the SRAM’s data.
A DCR contains two-way multiplexers. A memory controller dynamically assigns them
according to fault occurrence in an SRAM array. Internal redundancy access (RA) re-
routes the redundant column cell to the faulty location. Tag SRAM cells hold RA infor-
mation and subsequently share across all lines once a fault occurs. DCR offers minimum
area and timing overhead as compared with the technique where redundant rows substi-
(a)
tute an entire faulty sub-array. (b)

Figure
Figure19.19.Flip-flop-based row redundancy
Flip-flop-based row redundancyarchitecture
architecture [57].
[57]. (a) (a) Dynamic
Dynamic column
column redundancy
redundancy (DCR);
(DCR); (b) bitline
(b) bitline bypassbypass
(BB). (BB).

Bitlinebypass
Bitline bypass (BB),
(BB), shown
shown in Figure
in Figure 19b,19b, repairs
repairs faultyfaulty
SRAM SRAM
cellscells through
through the re-the
redundant
dundant rowsrows or columns
or columns of SRAM
of SRAM cells.
cells. WhenWhen repairing
repairing is is complete,
complete, rowrow andcolumn
and column
addressesare
addresses arere-programmed
re-programmedtotoensure ensurethe thecorrect
correctoperation.
operation.The Thetiming
timingoverheads
overheadstoto
bypassfaulty
bypass faultySRAM
SRAM cellscells are the
the setup
setuptime
timeduring
duringthe write
the write operation
operationandandthe the
multiplexer
multi-
delay in the read operation. Another simpler approach is line disabling
plexer delay in the read operation. Another simpler approach is line disabling (LD), where (LD), where faulty
lines of SRAM are disabled at the cost of a reduced cache
faulty lines of SRAM are disabled at the cost of a reduced cache size. size.
D.D.Statistical
StatisticalPerformance
Performance Evaluation
Evaluation of ofthe
theSRAM
SRAMCell:
Cell:ThisThis unique
unique approach
approach discards
dis-
SRAM caches showing under-performance during the
cards SRAM caches showing under-performance during the testing phase. The testing phase. The performance
evaluation against a benchmark is a fair criterion to decide a particular cache’s acceptability.
The corner-case analysis conventionally manifests an SRAM performance evaluation
under extreme scenarios. (a) Recently, increasing WID variability shows (b) variations in the
performance
Figure 19. Flip-flop-based row redundancy architecture [57]. (a) Dynamic columnperformance
of PMOS and NMOS devices. Thus, uncertainty in SRAM cell redundancy
increases.
(DCR); Montebypass
(b) bitline Carlo(BB).
(MC) simulations lay out the statistical performance with random
variations. The probability of a certain event, E, is accomplished through the unknown
random variable
Bitline bypassX distribution.
(BB), shown The randomization
in Figure produces
19b, repairs faulty aSRAM huge sample space with
cells through N
the re-
number ofrows
dundant samples. Equation
or columns (5) describes
of SRAM the probability
cells. When repairingofisan interest event
complete, row and [58].column
addresses are re-programmed to ensure the correct operation. The timing overheads to
1 N
N ∑ i=1
bypass faulty SRAM cells are the P̂MC = time
setup 1(Xi ∈the
during E) write operation and the multi-(5)
plexer delay in the read operation. Another simpler approach is line disabling (LD), where
faultyInlines
someofcases,
SRAM theare
number of samples
disabled is effectively
at the cost of a reducedreduced
cache by employing the concept
size.
of importance sampling
D. Statistical (IS) [58].
Performance A careful
Evaluation analysis
of the SRAMprovides a unique
Cell: This relationship function
approach dis-
cards SRAM caches showing under-performance during the testing phase. The
Micromachines 2022, 13, 1332 14 of 22

f between random variable X and event of interest E. Equation (6) sets forth the probability
distribution through IS.
1 N
N ∑ i=1
P̂IS = f(Xi )1(Xi ∈ E) (6)

The efficacy of sampling can be improved by utilizing the algorithms such as

norm-minimization [58], loop-flattening, spherical [58] and Gibbs sampling [59].

5.2. Environmental Variations

The temperature is a paramount factor in environmental variations. Any variation in
the temperature affects the charges’ transportation in a device and accordingly impacts
the circuit performance. At low temperatures, SRAM performance is better due to the
high ION /IOFF current ratio. Increasing the design density shows more leakage current
on the same footprint, which appears in the form of heat dissipation and, hence, raises
the temperature. Therefore, modern technologies’ performance suffers more due to the
improved design density.
Temperature control mechanisms are either internal or external to a chip. External
mechanisms include heat sinks, fans and liquid nitrogen. Internal mechanisms control the
temperature at the circuit or architecture level. During the circuit design, minimizing the
leakage current helps in limiting the temperature rise.
The throttling mechanism [18] prohibits the temperature elevation at the architecture
level, resulting from operational conditions and process variations. The throttling method
continuously tracks the temperature value. As the value crosses the critical level, control
circuitry lowers the operational frequency and voltage. The system restores nominal opera-
tional parameters provided that the temperature has returned to an appropriate range.
Besides the control of the supply voltage and operational frequency, temperature-
aware perspective methods are (1) body biasing, (2) BL sensing and (3) WL voltage. These
methods maintain the SRAM cell performance despite the temperature variations.
Body biasing voltage tuning shows improved performance despite temperature
fluctuations [60]. Performance is sustained on a chip by the generation of multiple volt-
ages and then switching to a suitable level. Another challenge is the BLs’ sensing margin
reduction. The leakage current is more dominant at high temperatures because of charge
scattering. In the SRAM design, the leakage current flows from BL to the access transistor.
As currents flow through the BLs’, the voltage level is reduced, which is an issue in a read
operation. A temperature controller tracks the leakage current and compensates for any
deficient voltage level to restore the BL voltage [61]. Similarly, the WL voltage lowering [62]
in a higher temperature enhances the read performance while maintaining the operational
frequency. The temperature compensation circuit [61] regulates the WL voltage. Similarly,
a circuit-level modification [63] where a buffer replaces the access transistor and sense
amplifier demonstrates a reliable operation up to 275 ◦ C in SOI technology.

6. Soft Errors
Environmental conditions can cause the emission of alpha particles, high-energy
neutrons and muons from a packaging material [64]. These particles possess sufficient
energy to alter the SRAM storage node. Scaling has lowered the critical charge on recent
technological nodes; hence, expediting the internal state logic inversion. However, FinFET
reduced geometry and drain-area exposure to the striking of high-energy particles lessens
the soft errors rate [65].
Radiation-induced soft errors can either be a single event upset (SEU) or multiple
events upset (MEU). Regardless, the exposed nodes of the SRAM cell collect the charge (Q).
When a node charge exceeds the critical charge value, it switches a node to the opposite
logic level. Equation (7) models the critical charge [66].
 − tf 
Qcritical = Q 1 − e τ (7)
Micromachines 2022, 13, 1332 15 of 22

The critical charge (Qcritical ) is the minimum charge to invert a nodal value. The
charges collected depend on the fall (tf ) and rise times of the internal voltage (τ) to change
the internal node state. Equation (8) explicates the number of SEUs. Apart from the
critical (Qcritical ) and collected charges (Qcollected ), SEU is also dependent on the flux (Φ)
and sensitive areas (A).
Qcritical
(− Q )
NSEU = Φ.Ae collected (8)
Specifically, MEUs are triggered by bipolar amplification and charge sharing [67].
Bipolar amplification is the result of a bipolar transistor formation between the source and
drain, with the body acting as a base. Equation (9) characterizes the number of MEUs
(NMEU ), which depends on the occurrence of SEUs (NSEU ) and the probability of multiple
upsets (PMEU ).
NMEU = NSEU .PMEU (9)
Here in Equation (9), PMEU ≈ 1 − Qcritical /Qcollected (x), x represents the relative dis-
tance along the direction of charge collection.
Soft error remedies can be performed at three levels: processing, cell and architecture.
The processing level treatment alters the device structure and doping concentrations.
These modifications either increase the critical charge or make devices less exposed to
radiation. Structural innovations consequently enhance the SRAM cell tolerance against
soft errors. Modern FinFET, PDSOI and FDSOI show fewer error rates due to processing
level modifications [64]. The last two soft error remedies are presented below.
A. Modified SRAM Cells: The SRAM cell hardening either enhances the sensitive-node
critical charge or slows down the transistor response. Figure 20a shows the addition of
an extra inverter in the conventional 6T-SRAM cell [68]. The newly added inverter increases
the critical charge and refreshes the sensitive node value. Similarly, a fully interlocked
SRAM cell cuts off a direct connection to the internal node, i.e., P1 and P2 drains, as shown
in Figure 20b [69]. The nodes connected to the gates of P1 and P2 are passed down to BLs.
This suppresses any external leakage and exposure to the internal nodes. Under normal
circumstances, both BLs are at a logic of zero. Next is the hybrid approach, as demonstrated
in Figure 20c [70]. The presence of the coupling capacitor multiplies the critical charge
value, while resistors slow down the SRAM cell response. The value of coupling capacitors
Micromachines 2022, 6, x FOR PEER REVIEW 16 of 23
and resistors decides the degree of soft error tolerance. However, the addition of integrated
components accelerates power exhaustion.

(a) (b) (c)

Figure
Figure20.
20.SRAM
SRAMcell
cellhardening
hardeningforforsoft
softerrors
errorsmitigation.
mitigation.(a)
(a)Increasing
Increasingcritical
criticalcharge
chargevalue
value[68];
[68];
(b)
(b) indirect connection to internal nodes [69]; (c) external components to slow down response [70].
indirect connection to internal nodes [69]; (c) external components to slow down response [70].

B.
B. Error CorrectingCodes:
Error Correcting Codes:The Thesimpler
simpler wayway to implement
to implement errorerror correcting
correcting codescodes
(ECC)
(ECC)
is to add a parity bit to each of the words in an SRAM array. The parity bit is an XORisofan
is to add a parity bit to each of the words in an SRAM array. The parity bit all
XOR of all
the bits in athe bits in
word. In acase
word. In error
a soft case aalters
soft error
an SRAMalterscell
anvalue,
SRAMthe cellparity
value,bitthe parity
value bit
would
value would than
be different be different
the XOR than the of
result XOR
theresult
bits inofthat
the bits in that
specific specific
word. But word.
only theButsingle
only the
soft
single soft error functions
error detection detection withfunctions with
parity. Theparity.
basicThe basic approach
approach followedfollowed
for ECCfor ECC
is as is as
follows:
follows:
data bits’data bits’ encoding
encoding is followed
is followed by syndrome
by syndrome calculation
calculation using already
using codes codes already imple-
implemented;
mented; then, the syndromes’ comparison locates the error bits. Errors correction is the last
step to complete the rectification.
Matrix ECCs are appealing because of their low complexity in implementation. They
divide an SRAM array into the matrix format at the logical level. Each horizontal row and
vertical column contain the parity bits. Figure 21 shows the logical partitioning of memory
 B. Error Correcting Codes: The simpler way to implement error correcting codes
(ECC) is to add a parity bit to each of the words in an SRAM array. The parity bit is an
XOR of all the bits in a word. In case a soft error alters an SRAM cell value, the parity bit
Micromachines 2022, 13, 1332 value would be different than the XOR result of the bits in that specific word. But only 16 the
of 22
single soft error detection functions with parity. The basic approach followed for ECC is as
follows: data bits’ encoding is followed by syndrome calculation using codes already imple-
mented; then, the syndromes’ comparison locates the error bits. Errors correction is the last
then, the syndromes’ comparison locates the error bits. Errors correction is the last step to
step to complete
complete the rectification.
the rectification.
Matrix
Matrix ECCsare
ECCs areappealing
appealingbecause
becauseof oftheir
theirlow
lowcomplexity
complexityininimplementation.
implementation.TheyThey
divide
divide an SRAM array into the matrix format at the logical level. Eachhorizontal
an SRAM array into the matrix format at the logical level. Each horizontalrowrowand
and
vertical
verticalcolumn
columncontain
containthe theparity
paritybits.
bits.Figure
Figure21 21shows
showsthe thelogical
logicalpartitioning
partitioningofofmemory
memory
using
usingmatrix
matrixcodes
codes[71].
[71].InInFigure
Figure21,21,DDrepresents
representsdata databits,
bits,HHisisthe
thehorizontal
horizontalparity
parity
hamming bit, while r is the hidden hamming bit. At the bottom, V shows
hamming bit, while r is the hidden hamming bit. At the bottom, V shows the vertical parity the vertical par-
ity bit. Taking the XOR of all the data bits in a row produces a horizontal
bit. Taking the XOR of all the data bits in a row produces a horizontal hamming parity bit. hamming parity
bit. Hidden
Hidden hamming
hamming (r) (r)
bit bit XORs
XORs alternate
alternate data
data bitsbits
forfor
thethe
samesame row.
row. Vertical
Vertical parity
parity (V) (V)
bits
bits are the result of alternate hidden hamming bits’ XOR operation.
are the result of alternate hidden hamming bits’ XOR operation. The comparison of bits The comparison of
bits r and V locates data bits containing an error. This way, a matrix code
r and V locates data bits containing an error. This way, a matrix code detects and corrects detects and
corrects
multiplemultiple
errors inerrors in a particular
a particular SRAM block.
SRAM block.

Figure21.
Figure Matrixerrors’
21.Matrix errors’correcting
correctingcodes
codesfor
forerror
errordetection
detectionand
andcorrection
correction[71].
[71].

Likewise,column
Likewise, columnlinelinecodes
codes(CLC)
(CLC)use
useextended
extendedhamming
hammingcodescodesfor
forerror
errordetection
detection
and correction [72]. In addition to parity bits, extended codes enable the detection
and correction [72]. In addition to parity bits, extended codes enable the detection and and
correction of the maximum number of errors. The number of redundant bits raises to in-to
correction of the maximum number of errors. The number of redundant bits raises
increase
crease thethe error
error tolerance.
tolerance.
However, to ameliorate
However, to ameliorate the the hardware
hardware redundancy,
redundancy,thethesingle-error-correction
single-error-correctiondouble-
dou-
error-detection (SEC-DED) or double-error correction (DEC) offers a solution
ble-error-detection (SEC-DED) or double-error correction (DEC) offers a solution through through
directcomparison
direct comparison[73].
[73].This
Thisincorporation
incorporationimmensely
immenselyreduces
reducesthe
theoverhead,
overhead,whereas
whereasthe the
cache-hit triggers error-bit detection and correction.
cache-hit triggers error-bit detection and correction.
7. Security-Aware Design
As part of cache memory, an SRAM cell array might hold sensitive data in an embed-
ded system design. Data attackers can exploit design parameters for the memory envision.
Table 4 provides a summary of such data stealing techniques.

Table 4. Summary of data attack techniques to sneak into the SRAM cell.

S. No. Technique Description

1 Power Analysis (PA) Power consumption information to predict internal data
2 Supply Voltage aging Variation in supply voltage as of NBTI in PMOS device
3 Cold Boot Attack Data retention at lower temperatures
4 Delayering Microscopy Data imprinting effects to guess stored data

A. Data Attacks
1. Power Analysis (PA) Attack [74]: Side channel analysis can trace an SRAM cell’s
content using current characteristics, especially the leakage current. Increasing the design
density increases the leakage current; hence, SRAM cells are more prone to PA attacks.
Figure 22 illustrates the concept of the PA attack by assuming an SRAM cell is storing
a ‘0’. The write ‘0’ operation showed a value of about 160 nA, whereas the write ‘1’
operation showed the current value of 100 µA. Thus, a side attacker can guess internal
 A. Data Attacks
1. Power Analysis (PA) Attack [74]: Side channel analysis can trace an SRAM cell’s
content using current characteristics, especially the leakage current. Increasing the design
density increases the leakage current; hence, SRAM cells are more prone to PA attacks.
Micromachines 2022, 13, 1332 Figure 22 illustrates the concept of the PA attack by assuming an SRAM cell is storing17 of 22a
‘0’. The write ‘0’ operation showed a value of about 160 nA, whereas the write ‘1’ operation
showed the current value of 100 µA. Thus, a side attacker can guess internal data through the
leakage
data of current
through information
the leakage of a write
of current operation.
information ofFor PA, an
a write attacker For
operation. needs knowledge
PA, an attackerof
and access
needs to the internal
knowledge of andarchitecture
access to thesuch as timing
internal control, power
architecture distribution
such as or peripheral
timing control, power
distribution
circuitry. or peripheral circuitry.

0.2 200

Current (µA)

Current (µA)
Write 0 Write 1
0.1 100

0.9 0.95 1 1.05 1.1 0.9 0.95 1 1.05 1.1

Time (ns) Time (ns)

Figure22.
Figure 22. Write
Writecurrent
currentflow
flowinformation
information6T-SRAM
6T-SRAMcell
cellfor
forinternal
internaldata
datasneaking
sneaking[74].
[74].

2.
2. Supply
SupplyVoltage
Voltageaging
aging[75]:
[75]:Generally,
Generally,thethesupply
supply voltage
voltageconnection
connection to to
thethe
circuit is
circuit
through PMOS devices. The aging of the gate oxide under negative biasing
is through PMOS devices. The aging of the gate oxide under negative biasing temperature temperature
instability
instability(NBTI)
(NBTI)puts
putsthe
thegate
gateoxide under
oxide understress, which
stress, whichleads to the
leads change
to the in characteris-
change in charac-
tics of pull-up PMOS devices in an SRAM cell. The differential change
teristics of pull-up PMOS devices in an SRAM cell. The differential change in the in the V th of devices
Vth of
results in distinct power-up levels. Attackers usually perform the read operation
devices results in distinct power-up levels. Attackers usually perform the read operation alongside
power-up
alongside level information
power-up to predict the
level information stored data.
to predict the stored data.
3. Cold Boot Attack [76]: We typically
3. Cold Boot Attack [76]: We typically assume assume a volatile
a volatile memorymemorylosesloses internal
internal data
data as power turns off. However, a volatile memory holds data for quite some time
as power turns off. However, a volatile memory holds data for quite some time after that.
after that. The retention time depends on the device material chemistry. Applying a low
The retention time depends on the device material chemistry. Applying a low temperature
temperature immediately after power loss enhances retention time. Subsequent scanning
immediately after power loss enhances retention time. Subsequent scanning of a device
of a device through external probes can reveal the stored data contents. Data encryption
through external probes can reveal the stored data contents. Data encryption and crypto-
and cryptographic keys are among potential candidates to secure against a cold boot attack.
graphic keys are among potential candidates to secure against a cold boot attack.
4. Microscopy of de-layering [77]: If an SRAM cell keeps the same data values
4. Microscopy of de-layering [77]: If an SRAM cell keeps the same data values for
for longer, the data imprinting effects change the transistor’s parameters. A technique
longer, the data imprinting effects change the transistor’s parameters. A technique known
known as atomic force microscopy (AFM) can provide layer information to a deeper level.
as atomic force microscopy (AFM) can provide layer information to a deeper level. Exten-
Extensive analysis of information predicts data stored in the SRAM cells. The modern
sive analysis of information predicts data stored in the SRAM cells. The modern FinFET-
FinFET-SRAM cell’s lower dimensions need less area analysis which eases data stealing.
SRAM cell’s lower dimensions need less area analysis which eases data stealing.
Besides data stealing, an attacker may try to fail SRAM cells. Failure attack could
Besides data stealing,
contain gate resizing, an attacker
gate oxide may
thickness try to fail
alteration SRAM voltage
or supply cells. Failure attack could
variations.
contain gate resizing,
B. Solutions: gateanalysis
Power oxide thickness alteration or supply
and data-imprinting effectsvoltage variations.
jeopardize data security,
Micromachines 2022, 6, x FOR PEER REVIEW B. Solutions: Power analysis and data-imprinting effects
but modifications in the conventional 6T-SRAM cell mitigate them. Figure jeopardize data security,
18 of 23 but
23 presents
modifications in the conventional 6T-SRAM
security-aware SRAM cell designs. [74,78,79]. cell mitigate them. Figure 23 presents secu-
rity-aware SRAM cell designs. [74,78,79].

VDD

WL WL
P2 P1

N4 Q QB N3

N6 N5
Bitline (BLB)
Bitline (BL)

N2 N1

GND

(a) (b) (c)

Figure23.
Figure 23.Modified
Modified SRAM
SRAM cell
celldesigns
designsfor
fordata
datasecurity.
security.(a)(a)
SRAM cellcell
SRAM with balanced
with current
balanced before
current before
read and write operations [74]. (b) Incorporating false leakage current information to protect data
read and write operations [74]. (b) Incorporating false leakage current information to protect data [78].
[78]. (c) SRAM cell toggling values to mitigate NBTI effects [79].
(c) SRAM cell toggling values to mitigate NBTI effects [79].
TheSRAM
The SRAM cell
cell in
in Figure
Figure 23a
23a equates
equatestotothe
thecurrent
currentinformation irrespective
information of aofcell
irrespective a cell
having a ‘0’ or ‘1’ value. Pre-charge (PC) signal goes low to connect cells to the supply
having a ‘0’ or ‘1’ value. Pre-charge (PC) signal goes low to connect cells to the supply
voltage via transistor P4. As PC goes high, it cuts power off and turns on the P3 transistor
voltage via transistor P4. As PC goes high, it cuts power off and turns on the P3 transistor
through an inverter, equalizing the voltage level on both internal nodes, i.e., Q and QB.
through an inverter, equalizing the voltage level on both internal nodes, i.e., Q and QB.
Any write operation will result in the same current for the ‘0’ or ‘1’ value.
Any write operation will result in the same current for the ‘0’ or ‘1’ value.
Next, Figure 23b presents an 8T-SRAM cell with additional transistors N5 and N6.
Next, Figure 23b presents an 8T-SRAM cell with additional transistors N5 and N6. The
The gates of these transistors are tied to the ground, thus keeping them always off. Re-
gates of these transistors are tied to the ground, thus keeping them always off. Regardless
gardless of internal nodes’ values, the SRAM cell will have the same number of off tran-
sistors; so, an SRAM cell can balance out the leakage current, and this makes tracing un-
feasible.
Figure 23c shows the architecture of data toggling to diminish the NBTI aftermath
anytime either an N2 or N3 transistor is on as per the internal node value. Next, as the
Micromachines 2022, 13, 1332 18 of 22

of internal nodes’ values, the SRAM cell will have the same number of off transistors; so,
an SRAM cell can balance out the leakage current, and this makes tracing unfeasible.
Figure 23c shows the architecture of data toggling to diminish the NBTI aftermath
anytime either an N2 or N3 transistor is on as per the internal node value. Next, as the
M_CLK signal goes high, a ‘0’ value is copied to Q or QB via slave circuit1 or slave circuit2
through an N2 or N3 transistor, respectively. Generally, the master circuit toggles the data
values then the slave circuit copies that specific value. At the same time, the reset circuit
resets the value of Q and QB to ‘1’ and ‘0’, respectively. Nevertheless, frequent data toggling
reduces imprints but suffers from the hardware and power overhead.

8. Discussion
This section discusses prominent challenges related to the SRAM operation and its
application as CIM for AI in brief.
A. Bitline voltage swing: Narrow differential voltage (around 50–200 mV) sensing
ensures low read latency. Accordingly, a quick and reliable sense amplifier design that ac-
curately detects BLs’ differential voltage [17] is challenging. Single-ended sensing schemes
are power hungry; therefore Chandras et al. [80] proposed three single-ended BL-sensing
schemes to optimize power consumption.
B. Biasing temperature instability: PBTI is associated with NMOS, so NBTI is related
to PMOS. The root cause is electron traps (ET) in gate oxide, affecting the Vth of a transistor.
Consequently, SRAM performance degrades or even becomes unacceptable [17].
M. Duang et al. [81] uses cyclic and anti-neutralization models with an appropriate voltage
level and duration to protect against ETs.
C. Half-select SRAM cells: To access a specific SRAM cell, the row driver and column
decoder select one row and column, respectively. Besides a selected cell, SRAM cells in the
same row or column are selected either column-wise or row-wise, but not both. Such cells,
known as half-select cells, suffer from the risk of the storage node value flipping through
BLs. Internal nodes are isolated during the read and write operations and SRAM cell level
alterations can make the SRAM cells half-select free [82].
D. Manufacturing and material issues: Fabrication process imperfections cause short,
void, and open interconnects, referred to as hard errors. Hard fault detection and correction
approaches [83] add significant overhead. Modern 3D monolithic structures for SRAM use
through-silicon vias (TSV) or multiple inter-tier vias (MIV) [84] for inter-tier communication
that exaggerates hard errors’ occurrence.
In addition, material losses become significant in the long run. The performance matrix,
for example, means time to failure (MTTF) [85] predicts SRAM performance expectancy.
E. SRAM-based CIM: Deep neural networks (DNNs) duplicate human brain structure,
enabling them to execute AI tasks with high accuracy and efficiency [86]. However, DNNs
are data-centric and accelerate the data traffic between microprocessor and memory, thus
becoming energy hungry. CIM performs frequent NN computations in or near memory to
reduce the data traffic. SRAM-CIM for content addressable memory (CAM) [87], neuro-
morphic vision [88] and convolution neural networks [86] has proven SRAM as a potential
candidate for AI applications.
SRAM achieves computation operations either inside or at the periphery of memory
using special computational units, known as in/near computations (IMC/NMC). Experts
have explored SRAM-CIM for analog or digital signal domains. Analog CIM solutions
are energy efficient but suffer from non-idealities [89]. Digital CIM accelerators are free
from analog signal precision and margin issues but at the cost of more peripheral circuits.
Among the DNNs, multiply and accumulate (MAC) operations [89] are frequent; hence, it
is focused on quite often. On-chip dedicated arithmetic units complete DNNs’ essential
calculations to reduce off-chip data access and achieve performance efficiency.
Micromachines 2022, 13, 1332 19 of 22

9. Conclusions
Modern deep submicron technological nodes present design and operational hurdles
to SRAMs. We have reviewed the design challenges by keeping the deep sub-micron and
FinFET technologies in focus. This is important in the context of emerging CIM applications
for ML and IoT devices. In this regard, we have introduced the SRAM cell configurations
with performance evaluation parameters. Overall, the SRAM cell’s hurdles can be classified
into five main categories. Each section highlights the mathematical parameters required to
evaluate a particular challenge’s severity, followed by the potential candidates for a solution.
The first two categories–the low voltage operation and leakage current–concentrate on
low power operations. The next two categories–process variations and soft errors–are
salient for the SRAM cell’s operational reliability. The last category is the security-sensitive
design, a major concern in current systems. Alongside the generalization of multiple
state-of-the-art solutions, it explains how to address design roadblocks.
Future SRAM cells should be more robust and performance-efficient to keep up
with the pace of microprocessor requirements. For future research, CIM needs extensive
exploration in the context of the in-memory digital domain computing as part of AI for
miniaturized electronic devices. These devices are power-limited; thus, computing needs
reliable and low-power operations. This study forms a foundation for the understanding
of SRAM challenges before exploring SRAM-based CIM for ML.

Author Contributions: W.G.: Conceptualization, methodology, software, validation, writing original

draft, editing, visualization, formal analysis, M.S.: Supervision, project administration, review and
editing, D.A.-K.: Supervision, visualization, review and editing. All authors have read and agreed to
the published version of the manuscript.
Funding: This research has received no external funding.
Data Availability Statement: Not applicable.
Conflicts of Interest: The authors declare no conflict of interest.

References
1. Available online: https://www.marketstudyreport.com/reports/global/unitedstates/european/union-and-china-non-volatile-
memory-market-research-report-2019-2025 (accessed on 16 December 2021).
2. Si, X.; Zhou, Y.; Yang, J.; Chang, M.-F. Challenges and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge
Devices. In Proceedings of the IEEE 14th International Conference on ASIC (ASICON), Kunming, China, 26–29 October 2021.
3. Shimeng, Y.; Xiaoyu, S.; Xiaochen, P.; Shanshi, H. Compute in Memories with Emerging Nonvolatile Memories: Prospects and
Challenges. In Proceedings of the IEEE Custom Integrated Circuit Conference (CICC), Boston, MA, USA, 22–25 March 2020.
4. Chou, C.C.; Lin, Z.J.; Tseng, P.L.; Li, C.F.; Chang, C.Y.; Chen, W.C.; Chih, Y.D.; Chang, T.Y.J. A N40 256Kx44 embedded RRAM
macro with SL pre-charge SA and low voltage current limiter to improve read and write performance. In Proceedings of the IEEE
International Solid State Circuit Conference (ISSCC), San Francisco, CA, USA, 11–15 February 2018.
5. Wu, J.Y.; Chen, Y.S.; Khwa, W.S.; Yu, S.M.; Wang, T.Y.; Tseng, J.C.; Chih, Y.D.; Diaz, C.H. A 40nm low power logic compatible
phase change memory technology. In Proceedings of the IEEE International Electron Devices Meeting (IEDM), San Francisco, CA,
USA, 1–5 December 2018.
6. Wei, L.; Alzate, J.G.; Arslan, U.; Brockman, J.; Das, N.; Fischer, K.; Ghani, T.; Golozonka, O.; Hentges, P.; Jahan, R.; et al.
A 7Mb STT-MRAM in 22FEL FinFET technology with 4ns read sensing time at 0.9V using write verify write scheme and offset
cancellation sensing techniques. In Proceedings of the IEEE International Solid-State Circuit Conference (ISSCC), San Francisco,
CA, USA, 17–21 February 2019.
7. Song, Y.J.; Lee, J.H.; Han, S.H.; Shin, H.C.; Lee, K.H.; Suh, K.; Jeong, D.E.; Koh, G.H.; Oh, S.C.; Park, J.H.; et al. Demonstration of
highly manufacturable STT-MRAM embedded in 28nm logic. In Proceedings of the IEEE International Electron Devices Meeting
(IEDM), San Francisco, CA, USA, 1–5 December 2018.
8. Weste, N.; Harris, D. CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed.; Pearson Education: London, UK, 2011.
9. Ishibashi, K.; Osada, K. Low Power and Reliable SRAM Memory Cell and Array Design; Springer: New York, NY, USA, 2011.
10. Weing, H. Compact Modelling and Short Channel Effects on nanowire MOS transistors. In Proceedings of the IEEE International
Conference on Integrated Circuits Design Technologies and Applications (ICICDT), Beijing, China, 21–23 November 2018.
11. Tsai, M.J. Investigation on 5nm Thick Hf0.5 Zr0.5 O2 Ferroelectric FinFET Dimension for sub 60mv/Decade Subthreshold slope.
IEEE J. Electron Devices Soc. 2019, 7, 1033–1037. [CrossRef]
Micromachines 2022, 13, 1332 20 of 22

12. Raskin, J.P. Fully Depleted SOI Technologies from Digital to RF and beyond. In Proceedings of the IEEE SOI-3D Subthreshold
Microelectronic Technology Unified Conference (S3S), Burlingame, CA, USA, 15–18 October 2018.
13. Turi, M.A.; Delgado-Frias, J.G. Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells with Reverse Biased FinFETs, Near
Threshold Operation and Power Gating. IEEE Trans. Circuit Syst. II Express Brief 2019, 67, 765–769. [CrossRef]
14. Pal, S.; Bose, S.; Ki, W.H.; Islam, A. Characterization of Half Select Free Write Assist 9T SRAM Cell. IEEE Tran. Electron. Devices
2019, 6, 4745–4752. [CrossRef]
15. Wang, M.; Yan, C.; Li, X.; Zhou, D.; Zeng, X. High Dimensional and Multiple-Failure-Region Importance Sampling for SRAM
Yield Analysis. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2017, 25, 806–819. [CrossRef]
16. Kan, S.; Ottavi, M.; Dworak, J. Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation.
In Proceedings of the IEEE International Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS),
Mherst, MA, USA, 12–14 October 2015.
17. Qazi, M.; Sinangil, M.; Chandrakasan, A. Challenges and Directions for Low Voltage SRAMs. IEEE Des. Test Comput. 2011,
28, 32–43. [CrossRef]
18. Samandari-Rad, J.; Hughey, R. Power/Energy minimization techniques for variability aware high performance 16nm 6T-SRAM.
IEEE Access 2016, 4, 594–613. [CrossRef]
19. Morifuji, E.; Patil, D.; Horowitz, M.; Nishi, Y. Power Optimization for SRAM and its scaling. IEEE Trans. Electron Devices 2017,
54, 715–722. [CrossRef]
20. Wieckowski, M.; Sylvester, D.; Blaauw, D.; Chandra, V.; Idgunji, S.; Pietrzyk, C.; Aitken, R. A black box method for stability
analysis of arbitrary SRAM cell structures. In Proceedings of the Design, Automation & Test in Europe (DATE), Dresden, Germany,
8–12 March 2010.
21. Bhattacharya, D.; Jha, N.K. Ultra High Density Monolithic 3-D FinFET SRAM with Enhanced Read Stability. IEEE Trans. Circuits
Syst.-I 2016, 63, 1176–1187. [CrossRef]
22. Singh, J.; Mohanty, S.P.; Pradhan, D.K. Robust SRAM Design and Analysis; Springer: New York, NY, USA, 2013.
23. Huynh-Bao, T.; Sakhare, S.; Yakimets, D.; Ryckaert, J.; Thean, A.V.Y.; Mercha, A.; Verkest, D.; Wambacq, P. A comprehensive
benchmark and optimization of 5nm lateral and vertical GAA 6T SRAM. IEEE Trans. Electron. Devices 2016, 63, 643–651. [CrossRef]
24. Mohapatra, E.; Dash, T.P.; Jena, J.; Das, S.; Maiti, C.K. Performance Analysis of Sub-10nm Vertically Stacked Gate All Around
FETs. In Proceedings of the IEEE VLSI Device Circuits and Systems (VLSIDCS), Kolkata, India, 18–19 July 2020.
25. Weber, O. FDSOI vs FinFET: Differentiating device features for ultra-low power and IoT applications. In Proceedings of the IEEE
International Conference on IC design and Technology (ICICDT), Austin, TX, USA, 23–25 May 2017.
26. Takeda, K.; Hagihara, Y.; Aimoto, Y.; Nomura, M.; Nakazawa, Y.; Ishii, T.; Kobatake, H. A Read-Static-Noise-Margin-Free SRAM
Cell for Low-VDD and High-Speed Applications. IEEE J. Solid-State Circuits 2006, 41, 113–121. [CrossRef]
27. Chang, L.; Fried, D.M.; Hergenrother, J.; Sleight, J.W.; Dennard, R.H.; Montoye, R.K.; Sekaric, L.; McNab, S.J.; Topol, A.W.;
Adams, C.D.; et al. Stable SRAM Cell Design for the 32 nmNode and Beyond. In Proceedings of the IEEE Digest of Technical
Papers and Symposium on VLSI Technology, Kyoto, Japan, 14–16 June 2005.
28. Oh, T.W.; Jeong, H.; Kang, K.; Park, J.; Yang, Y.; Jung, S.O. Power gated 9T SRAM cell for low energy operation. IEEE Trans. Very
Large Scale Integr. Syst. (VLSI) 2017, 25, 1183–1187. [CrossRef]
29. Chang, I.J.; Kim, J.J.; Park, S.P.; Roy, K. A 32 kb 10T Sub-threshold SRAM Array with Bit-Interleaving and Differential Read
Scheme in 90 nm CMOS. IEEE J. Solid-State Circuits 2009, 44, 650–658. [CrossRef]
30. He, Y.; Zhang, J.; Wu, X.; Si, X.; Zhen, S.; Zhang, B. A Half select Disturb free 11T SRAM cell with built in read/write assist
scheme for ultra-low voltage operation. IEEE Trans. Very Large Scale Integr. Syst. (VLSI) 2019, 27, 2344–2353. [CrossRef]
31. Sun, J.; Jiao, H. A 12T low power Standard cell based SRAM cell for ultra-low voltage operation. In Proceedings of the IEEE
International Conference on IC Design and Technology (ICICDT), Suzhou, China, 17–19 June 2019.
32. Choi, W.; Park, J. A Charge recycling assist technique for reliable and low power SRAM design. IEEE Trans. Circuits Syst. 2016,
63, 1164–1175. [CrossRef]
33. Chang, J.; Chen, H.Y.; Chan, G.; Cheng, H.; Wang, S.P.; Lin, Y.; Fujiwara, H.; Lee, R.; Liao, J.H.; Wang, W.P. A 5nm 135Mb SRAM
in EUV and High Mobility Channel FinFET Technology with Metal Coupling and Charge Sharing Write Assist Circuitry Schemes
for High Density and Low-VMIN Applications. In Proceedings of the IEEE International Solid-State Circuit Conference (ISSCC),
San Francisco, CA, USA, 16–20 February 2020.
34. Song, T.; Rim, W.; Park, S.; Kim, Y.; Yang, G.; Kim, H.; Baek, S.; Jung, J.; Kwon, B.; Cho, S.; et al. A 10nm FinFET 128 Mb
SRAM with assist adjustment system for power, performance and area optimization. IEEE J. Solid-State Circuits 2017, 52, 240–249.
[CrossRef]
35. Chang, M.F.; Chen, C.F.; Chang, T.H.; Shuai, C.C. A compact area low VDDmin 6T SRAM with improvement in cell stability, read
speed and write margin using a dual split control assist scheme. IEEE J. Solid-State Circuits 2017, 52, 2498–2514. [CrossRef]
36. Chang, M.F.; Chen, C.F.; Chang, T.H.; Shuai, C.C.; Wang, Y.Y.; Yamauchi, H. A 28nm 256kb 6T-SRAM with 280mV improvement
in VMIN using a dual-split-control assist scheme. In Proceedings of the IEEE International Conference on Solid State Circuits
(ISSCC), San Francisco, CA, USA, 22–26 February 2015.
37. Guo, Z.; Kim, D.; Nalam, S.; Wiedemer, J.; Wang, X.; Karl, E. A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed
PMOS TVC and stepped-WL for low-voltage applications. In Proceedings of the IEEE International Conference on Solid State
Circuits (ISSCC), San Francisco, CA, USA, 11–15 February 2018.
Micromachines 2022, 13, 1332 21 of 22

38. Karl, E.; Guo, Z.; Conary, J.W.; Miller, J.L.; Ng, Y.G.; Nalam, S.; Kim, D.; Keane, J.; Bhattacharya, U.; Zhang, K. A 0.6V 1.5GHz
84Mb SRAM design in 14nm FinFET CMOS technology. In Proceedings of the IEEE International Conference on Solid State
Circuits (ISSCC), San Francisco, CA, USA, 22–26 February 2015.
39. Song, T.; Jung, J.; Rim, W.; Kim, H.; Kim, Y.; Park, C.; Do, J.; Park, S.; Cho, S.; Jung, H.; et al. A 7nm FinFET SRAM using
EUV lithography with dual write-driver-assist circuitry for low-voltage applications. In Proceedings of the IEEE International
Conference on Solid State Circuits (ISSCC), San Francisco, CA, USA, 11–15 February 2018.
40. Dutta, T.; Pahwa, G.; Trivedi, A.R.; Sinha, S.; Agarwal, A.; Chauhan, Y.S. Performance evaluation of 7nm node negative capacitance
FinFET based SRAM. IEEE Electron. Devices Lett. 2017, 38, 1161–1164. [CrossRef]
41. Yang, L.; Zhu, J.; Chen, C.; Wang, Z.; Liu, Z.; Huang, Q.; Ye, L.; Huang, R. A novel Si-TFET based SRAM design for ultra-low power
0.3VDD applications. In Proceedings of the 15th IEEE International Conference on Asia and South Pacific Design Automation
(ASP-DAC), Taipei, Taiwan, 18–21 January 2010.
42. Calimera, A.; Macii, A.; Macii, E.; Poncino, M. Design Techniques and Architectures for Low Leakage SRAMs. IEEE Trans. Circuits
Syst. 2012, 59, 1992–2007. [CrossRef]
43. Azizi, N.; Najm, F.N.; Moshovos, A. Low-leakage asymmetrical SRAM. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2003,
11, 701–715. [CrossRef]
44. Pasandi, G.; Mehta, R.; Pedram, M.; Nazarian, S. Hybrid Cell Assignment and Sizing for Power, Area, Delay Product Optimization
of SRAM Arrays. IEEE Trans. Circuits Syst.-II 2019, 66, 2047–2051. [CrossRef]
45. Agarwal, A.; Li, H.; Roy, K. DRG-cache: A data retention gated ground cache for low power. In Proceedings of the IEEE Design
Automation Conference (DAC), New Orleans, LA, USA, 10–14 June 2002.
46. Elakkumanan, P.; Narasimhan, A.; Sridhar, R. NC-SRAM—A low-leakage memory circuit for ultra deep submicron designs.
In Proceedings of the IEEE International Conference on System-on-Chip (SoC), Portland, OR, USA, 17–20 September 2003.
47. Liao, W.; Basile, J.M.; He, L. Microarchitecture-level Leakage reduction with Data retention. IEEE Trans. Very Large Scale Integr.
(VLSI) Syst. 2005, 12, 1324–1328. [CrossRef]
48. Kim, C.H.; Roy, K. Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors. In Proceedings of the
International Symp. on Low Power Electronics and Design (ISLPED), Monterey, CA, USA, 12–14 August 2002; pp. 251–254.
49. Wang, T.; Cui, X.; Ni, Y.; Yu, D.; Cui, X. Evolution of Dynamic Adjusting Threshold Voltage Scheme for Low Power FinFET
circuits. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2018, 26, 1922–1928. [CrossRef]
50. Mohammed, M.U.; Nizam, A.; Ali, L.; Chowdhury, M.H. A Low Leakage SRAM Bitcell Design Based on MOS Graphene Nano
Ribbon FET. In Proceedings of the IEEE International Symp. on Circuits and Systems (ISCAS), Sapporo, Japan, 26–29 May 2019.
51. Srinivasa, S.; Aziz, A.; Shukla, N.; Li, X.; Sampson, J.; Datta, S.; Kulkarni, J.P.; Narayanan, V.; Gupta, S.K. Correlated material
enhanced SRAM with robust low power operation. IEEE Trans. Electron Devices 2016, 63, 4744–4752. [CrossRef]
52. Rahma, M.A.; Anis, M. Nanometer Variation-Tolerant SRAM: Circuit and Statistical Design for Yield; Springer: New York, NY,
USA, 2013.
53. Karl, E.; Wang, Y.; Ng, Y.G.; Guo, Z.; Hamzaoglu, F.; Bhattacharya, U.; Zhang, K.; Mistry, K.; Bohr, M. A 4.6 GHz 162 Mb
SRAM design in 22 nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. In Proceed-
ings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA,
19–23 February 2012; pp. 230–232.
54. International Technological Roadmap for Semiconductor (ITRS). 2015. Available online: http://www.itrs2.net/itrs-reports.html
(accessed on 3 June 2022).
55. Nautiyal, V.; Nukala, N.; Bohra, F.A.; Dwivedi, S.; Dasani, J.; Singh, S.; Singla, G.; Kinkade, M. Logic based row redundancy
technique designed in 7nm FinFET technology for embedded SRAM. In Proceedings of the IEEE 19th International Symp. on
Quality Electronic Design (ISQED), Santa Clara, CA, USA, 13–14 March 2018.
56. Mohammad, B.; Rab, M.T.; Mohammad, K.; Suleman, M.A. Dynamic cache resizing for high yield SOC. In Proceedings of the
IEEE International Conference on IC Design and Technology (ICICDT), Austin, TX, USA, 18–20 May 2009.
57. Zimmer, B.; Chiu, P.F.; Nikolić, B.; Asanović, K. Reprogrammable redundancy for SRAM based cache Vmin reduction in 28nm
RISC-V processor. IEEE J. Solid-State Circuit 2017, 52, 2589–2600. [CrossRef]
58. Qazi, M.; Tikekar, M.; Dolecek, L.; Shah, D.; Chandrakasan, A. A loop flattening and spherical sampling: Highly efficient model
reduction technique for SRAM yield analysis. In Proceedings of the Design Automation and Test in Europe (DATE), Dresden,
Germany, 8–12 March 2010.
59. Sun, S.; Feng, Y.; Dong, C.; Li, X. Efficient SRAM failure prediction via Gibbs sampling. IEEE Trans. Comput. Aided Des. Integr.
Circuit Syst. 2012, 31, 1831–1844. [CrossRef]
60. Chhabra, A.; Srivastava, M.; Gupta, P.R.; Dhori, K.J.; Triolet, P.; Di Gilio, T.; Bansal, N.; Sujatha, B. Temperature based adaptive
memory subsystem in 28nm UTBB FDSOI. In Proceedings of the IEEE International Symp. on Circuits and Systems (ISCAS),
Montreal, QC, Canada, 22–25 May 2016.
61. Kim, T.T.H.; Le Ba, N. Design of temperature aware low voltage SRAM with self-adjustable sensing margin enhancement for high
temperature applications upto 300 ◦ C. IEEE J. Solid-State Circuits 2014, 49, 2534–2546. [CrossRef]
62. Kumar, V.; Kumar Shrivatava, R.; Padaliya, M.M. A temperature compensated read assist for low Vmin and high-performance
high density 6T SRAM cell in 7nm technology. In Proceedings of the IEEE 31st International Conference on VLSI design and 17th
International Conference on Embedded Systems, Pune, India, 6–10 January 2018.
Micromachines 2022, 13, 1332 22 of 22

63. Cojbasic, R.; Leblebici, Y. Design of High Temperature SRAM for Reliable Operation Beyond 250 ◦ C. In Proceedings of the IEEE
International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24–27 May 2015.
64. Fang, Y.P.; Oates, A.S. Characterization of single bit and multiple cell soft errors event in planer and FinFET SRAM. IEEE Trans.
Device Mater. Reliab. 2016, 16, 132–137. [CrossRef]
65. Fang, Y.P.; Oates, A.S. Neutron-induced charge collection simulation of bulk FinFET SRAMs compared to planar SRAMs. IEEE
Trans. Device Mater. Reliab. 2011, 11, 551–554. [CrossRef]
66. Fang, Y.P.; Oates, A.S. Muon Induced Soft Errors in the SRAM Circuits in the Terrestrial Environment. IEEE Trans. Devices Mater.
Reliab. 2015, 15, 115–122. [CrossRef]
67. Yoshimoto, S.; Okumura, S.; Nii, K.; Kawaguchi, H.; Yoshimoto, M. Multiple-cell-upset tolerant 6T SRAM using NMOS centered
cell layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 2013, E96-A, 1579–1585. [CrossRef]
68. Alouani, I.; Elsharkasy, W.M.; Eltawil, A.M.; Kurdahi, F.J.; Niar, S. AS8 SRAM: Asymmetric SRAM architecture for soft error
hardening enhancement. J. Inst. Eng. Technol. (IET) Circuits Devices Syst. 2017, 11, 89–94. [CrossRef]
69. Shah, J.S.; Nairn, D.; Sachdev, M. A 32kb Macro with 8T Soft errors Robust, SRAM cell in 65nm CMOS. IEEE Trans. Nucl. Sci.
2015, 62, 1367–1374. [CrossRef]
70. Mostafa, H.; Anis, M.; Elmasry, M. A bias dependent model for impact of process variations on SRAM soft Errors immunity. IEEE
Trans. Very Large Scale Integr. 2011, 19, 2130–2134. [CrossRef]
71. Liu, S.; Xiao, L.; Li, J.; Zhou, Y.; Mao, Z. Low redundancy matrix-based codes for adjacent errors correction with parity
sharing. In Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA,
14–15 March 2017.
72. Gracia-Morán, J.; Saiz-Adalid, L.J.; Gil-Tomas, D.; Gil-Vicente, P.J. Improving Error Correction Codes for Multiple Cells Upsets in
Space Applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2018, 26, 2132–2142. [CrossRef]
73. Liu, S.; Reviriego, P.; Xiao, L. Evaluating Direct Compare for Double Error Correction Codes. IEEE Trans. Device Mater. Reliab.
2017, 17, 802–804. [CrossRef]
74. Giterman, R.; Keren, O.; Fish, A. A 7T security oriented SRAM bitcell. IEEE Trans. Circuits Syst. 2019, 66, 1396–1400. [CrossRef]
75. Cakir, C.; Bhargava, M.; Mai, K. 6T SRAM and 3T DRAM data retention and reminisce characterization in 65nm bulk CMOS.
In Proceedings of the IEEE Custom Integrated Circuit Conference (CICC), San Jose, CA, USA, 9–12 September 2012.
76. Pan, X.; Bacha, A.; Rudolph, S.; Zhou, L.; Zhang, Y.; Teodorescu, R. NVCool: When Non Volatile Cache Meet Cold Boot Attack.
In Proceedings of the 36th IEEE International Conference on Computer Design (ICCD), Orlando, FL, USA, 7–10 October 2018.
77. Yap, M.; Wei, T.C.; Narang, V. In Situ Delayering in Atomic Force Microscope for sub 20nm Technology Devices. In Proceedings
of the IEEE International Symp. on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 16–19 July 2018.
78. Giterman, R.; Vicentowski, M.; Levi, I.; Weizman, Y.; Keren, O.; Fish, A. Leakage power attack resilient symmetrical 8T SRAM cell.
IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2018, 26, 2180–2184. [CrossRef]
79. Ho, W.G.; Chong, K.S.; Kim, T.T.H.; Gwee, B.H. A secure data toggling SRAM for confidential data protection. IEEE Trans. Circuits
Syst. 2019, 66, 4186–4199. [CrossRef]
80. Chandras, A.; Bhaaskaran, V.K. Sensing schemes of sense amplifier for single ended SRAM. In Proceedings of the IEEE
International Conference on Next Electronic Technologies: Silicon to Software (ICNETS2), Chennai, India, 23–25 March 2017.
81. Duan, M.; Zhang, J.F.; Ji, Z.; Zhang, W.D.; Vigar, D.; Asenov, A.; Gerrer, L.; Chandra, V.; Aitken, R.; Kaczer, B. Insight into Electron
Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging. IEEE Tran. Electron Devices
2016, 13, 3642–3648. [CrossRef]
82. Ahmad, S.; Iqbal, B.; Alam, N.; Hasan, M. Low leakage fully half select free Robust SRAM cells with BTI reliability analysis. IEEE
Trans. Device Mater. Reliab. 2018, 18, 337–349. [CrossRef]
83. Zhang, Y.; Piao, Y.; Huo, M.; Wang, T.; Ma, G.; Liu, C.; Ma, J.; Guo, K.; Qi, C. Design and Verification of SRAM Self-Detection
Repair Based on ECC and BISR Circuit. In Proceedings of the IEEE 26th Symposium on Physical and Failure Analysis of Integrated
Circuits, Hangzhou, China, 2–5 July 2019.
84. Guler, A.; Jha, N.K. Three Dimensional Monolithic FinFET based 8T SRAM cell Design for Enhanced Read Time and Low Leakage.
IEEE Tran. Very Large Scale Integr. Syst. (VLSI) 2019, 27, 899–912. [CrossRef]
85. Krasich, M. How to Estimate and Use MTTF/MTBF would the real MTBF be stand up please? In Proceedings of the IEEE
International Symp. on Annual Reliability and Maintainability, Fort Worth, TX, USA, 26–29 January 2009.
86. Sze, V.; Chen, Y.H.; Yang, T.J.; Emer, J.S. Efficient Processing of Deep Neural Networks: A Tutorial and Survey. Proc. IEEE 2017,
105, 2295–2329. [CrossRef]
87. Lin, Z.; Zhan, H.; Li, X.; Peng, C.; Lu, W.; Wu, X.; Chen, J. In-Memory Computing with Double Word Lines and Three Read Ports
for Four Operands. IEEE Trans. Very Large Scale Integr. Syst. 2020, 28, 1316–1320. [CrossRef]
88. Bose, S.K.; Mohan, V.; Basu, A. A 75kb SRAM in 65nm CMOS for In-memory Computing based Neuromorphic Image Denoising.
In Proceedings of the IEEE International Symposium on Circuit and Systems (ISCAS), Seville, Spain, 12–14 October 2020.
89. Yu, S.; Jiang, H.; Huang, S.; Peng, X.; Lu, A. Compute-in-Mmeory Chips for Deep Learning: Recent Trends and Prospects. IEEE
Circuit Syst. Mag. 2021, 3, 31–56. [CrossRef]