ALC5686
ALC5686
ALC5686
ALC5686-CGT
Datasheet
Rev. 0.10
25 February 2019
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REVISION HISTORY
Revision Release Date Summary
0.10 2019/2/25 Preliminary version release.
Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
3. FEATURES ......................................................................................................................................................................... 3
List of Tables
TABLE 1. DIGITAL I/O PINS ........................................................................................................................................................... 11
TABLE 2. ANALOG I/O PINS .......................................................................................................................................................... 12
TABLE 3. REFERENCE PINS............................................................................................................................................................ 12
TABLE 4. POWER/GND PINS ......................................................................................................................................................... 13
TABLE 5. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................... 16
TABLE 6. POWER/GROUND OPERATON CONDITIONS..................................................................................................................... 16
TABLE 7. STATIC CHARACTERISTICS............................................................................................................................................. 17
TABLE 8. ANALOG PERFORMANCE CHARACTERISTICS ................................................................................................................. 18
List of Figures
FIGURE 1. FUNCTION BLOCK........................................................................................................................................................... 6
FIGURE 2. POWER BLOCK................................................................................................................................................................ 7
FIGURE 3. ANALOG MIXER PATH .................................................................................................................................................... 8
FIGURE 4. DIGITAL MIXER PATH .................................................................................................................................................... 9
FIGURE 5. QFN48 PIN ASSIGNMENT ............................................................................................................................................. 10
FIGURE 6. SYSTEM CONNECTION OF USB TYPE-C HEADSET ........................................................................................................ 14
FIGURE 7. SYSTEM CONNECTION OF USB TYPE-C TO 3.5MM DONGLE ......................................................................................... 15
FIGURE 8. PACKAGE DIMENSION................................................................................................................................................... 21
1. General Description
The ALC5686 is a highly-integrated USB audio solution which is specifically designed for high-end USB
type-C headset/headphone and other USB-to-3.5mm jack audio applications. The ALC5686 mainly
combines USB 2.0/ADC 3.0 digital audio interface, I2S/I2C interfaces, embedded flash for saving more
PCB size, and stereo Hi-Fi quality headphone amplifiers. The ALC5686 features a stereo low power
cap-free Class-G headphone amplifier with 124dB SNR and 95dB THD+N performance, providing
longer battery life and Hi-Fi listening experiences.
In terms of audio jack detection features, the embedded Jack detection function can automatically detect
whether the accessory is a headset (4 segments) or a headphone (3 segments) and plug-in/plug-out status.
Meanwhile, the build-in global headset function can automatically sense and support both OMTP and
CTIA headset pinouts with automatic switch for microphone and ground signals. On top of that, the
ALC5686 features auto impedance sense function which can recognize the jack impedance into 9 sections
from 0Ohm to >50kOhm load, distinguishing between the headset and line-in. Besides, using 3-button,
4-button, or even multi-button headsets are also detected and fully supported through the ALC5686. All
the features shown above meet the latest Google Wired Audio Headset Specification. These features
make ALC5686 also a best solution for USBC to 3.5mm jack audio adapter.
Besides, ALC5686 integrates high efficient DC-DC buck converter for power of the system with wide
input voltage, 3.0V~5.0V. The buck converter will automatically switch between PWM and PFM modes
while chip operating with different power loading for better efficiency.
2. System Applications
USB or USB Type-C handset & headphone
3. Features
USB 2.0 interface for the audio codec
Support USB FS and HS Mode
USB audio input / output interface
Support PCM streams on USB
Non-crystal design
Support full-speed and high-speed transfer mode
Support UAC1.0/2.0 and ADC3.0 with LPM/L1 feature
External flash supported
Audio data supports up to 32-bits data length and 8k~384k sampling rate
Ultra low power consumption when jack unplug on USB to 3.5mm dongle application
VBUS < 100uA
MICBIAS1/2
Multi-outputs MICBIAS: 2.7V/2.4V/2.25V/1.8V
Low noise design for better recoding quality
Parametric 12 bands (6+6 bands) equalizer shared for playback or record path
6 bands (1*1st LPF + 1*1st HPF + 3*2nd BPF + 1*Biquad Filter)
Sidetone function
Others:
Zero detection and soft volume for pop noise suppression
Power management and enhanced power saving
4. Function Block
4.1. Function Block
I2S_ADCDAT
I2S_DACDAT
I2S_LRCK
I2S_BCLK
I2S Interface
SLEEVE_SENSE
RING2_SENSE
0/13/20/30/35/40/44/50/52dB ADC DAC
DACL
SLEEVE_GND Volume Realtek Volume HPO_L
CTIA/OMTP MIC Digital Signal Headphone
RING2_GND Boost
ADC High High CPVREF
SW Pass
Processing Pass Amp
IN1P_SLEEVE Filter Filter
DACR HPO_R
IN1P_RING2
MIC_CAP
I2C
k
SCL
SDA Interface
e
Low Power JD_1
JD JD_2
t
MCU USB ADC
GPIO8/UART_RX/I2S_LRCK/PWM1_OUT Multi
l
GPIO9/UART_TX/I2S_BCLK/PWM2_OUT Function
3.0 MICBIAS1
ROM Cache SRAM MICBIAS
GPIO10/UART_RTS/I2S_DACDAT
a
Pin (56KB) (2KB) (4KB) MICBIAS2
GPIO11/UART_CTS/I2S_ADCDAT
e XTAL XTI
FLASH
R
FLASH_CS Oscillator XTO
USB 2.0
(256KB)
APHY
DM
RREF
DP
MICVDD
VDD_IO
DCVDD
DGND
DV33
AV18
DV33 VBUS
LDO LDO_ VOUT_SWR
Digital I/O LDO
_33 IO MICVDD MICBIAS
LDO_
USB APHY
AV18
VOUT_SWR CPVDD
LDO
Digital Core/MCU
Digital CPP1
VBUS DC-DC CPN1
Buck Converter CPP2
PGND Headphone
Charge Pump CPN2
SW CPVEE
VOUT_SWR CPVPP
VOUT_SWR
AGND
DACGND
LDO_ADDA_O
AGND2
VREF
Rev. 0.10
ALC5686
Headphone Amp
Fil te r &
HPO_L
DACL Gain
0/13/20/30/35/40/44/50/52dB
Dig it al Vo lu me
IN1P_SLEEVE
Fil te r &
Input Buf BST1
8
Gain ADC Digital Block
IN1P_RING2 CBJ
0 ~ -18dB
Dig it al Vo lu me
-3d B/Ste p 0 ~ -2 3.25 dB (-1.5d B/st ep)
Fil te r &
HPO_R
DACR Gain
4.3. Analog Audio Mixer Path
RECMIX
USB I/F I2S I/F
Rev. 0.10
ALC5686
UAC1_DAC_0
IF1_DAC_0
Div2
UAC1_DAC_0
Stereo1_ADC_Mixer_L
ADC Decimation
boost
Wind
VOL Interpolation DACL1
Filter filter VOL Gain
EQ Filter
Stereo1_ADC_Mixer_L EQ VOL 6-Band
6-Band 1*LPF(1st)
1*LPF(1st) DACR1
1*HPF(1st) Gain DACL
ADC 1*HPF(1st) 3*BPF(2n d)
ADC 3*BPF(2n d)
9
UAC1_DAC_1
SideTone
IF1_DAC_1
Div2
UAC1_DAC_1
Stereo1_ADC_Mixer_L
Stereo1_ADC_Mixer_R
UAC1_DAC_0
UAC1_DAC_1
0dB/+12dB 32steps with 1.5dB/step
ADC HPF Gain VOL SideTone
UAC OUT UAC1_DAC_0
UAC OUT UAC1_DAC
UAC1_DAC_1
Endpoint G
IF1_ADC_R
IF1_ADC_L
4.4. Digital Mixer Path
IF1_DAC_0
IF1_DAC_1
USB Bus USB 2.0
UAC1_ADC Selection
LRLR
LLRR
Controller
IF1_DAC_0
ADCDAT1
DACDAT1
UAC1_ADC2 IF1_DAC_1
LRCK1
BCLK1
ALC5686
Datasheet
5. Pin Assignment
VOUT_SWR
MICBIAS1
MICBIAS2
MICVDD
DCVDD
AGND
PGND
RREF
VBUS
DV33
JD_1
DM
SW
DP
48 47 46 45 44 43 42 41 40 39 38 37 36 35
JD_2 1 34 XTLI
SLEEVE_SENSE 2 33 XTLO
RING2_SENSE 3 32 VDD_IO
IN1P_SLEEVE 4 31 SDA
IN1P_RING2 5 30 SCL
RING2_GND 6 29 I2S_BCLK/PWM2_OUT/UART_TX/GPIO9
SLEEVE_GND 7 28 I2S_LRCK/PWM1_OUT/UART_RX/GPIO8
DACGND 8 ALC5686 27 FLASH_CS
MIC_CAP 9 xxxxxxx ywwvs 26 I2S_ADCDAT/UART_CTS/GPIO11
DACREF 10 (Top View) 25 I2S_DACDAT/UART_RTS/GPIO10
11 12 13 14 15 16 17 18 19 20 21 22 23 24
AGND2
VREF
LDO_ADDA_O
HPO_L
HPO_R
CPVREF
HPVDD
CPVPP
CPVEE
CPVDD
CPP1
CPN1
CPN2
CPP2
EPAD: DGND
6. Pin Description
6.1. Digital I/O Pins
Table 1. Digital I/O Pins
Name Type Pin Description Characteristic Definition
Differential type signal
Default state: weakly pull-low
DP I/O 36 USB data plus
Full Speed mode: 120MHz
High Speed mode: 480MHz
Differential type signal
Default state: weakly pull-low
DM I/O 37 USB data minus
Full Speed mode: 120MHz
High Speed mode: 480MHz
SCL I/O 30 Master I2C Serial Clock Open Drain
SDA I/O 31 Master I2C Serial Data Open Drain
Output: VOL=0.1*VDD_IO,
I2S interface synchronous signal VOH=0.9*VDD_IO
I2S_LRCK/PWM1_OU PWN Generator Input: Schmitt trigger
I/O 28
T/UART_RX/GPIO8 UART receiver data VIL= 0.35*VDD_IO
GPIO function VIH=0.65*VDD_IO
Default Status: Output Type
Output: VOL=0.1*VDD_IO,
I2S interface serial bit clock VOH=0.9*VDD_IO
I2S_BCLK/PWM2_OU PWN Generator Input: Schmitt trigger
I/O 29
T/UART_TX/GPIO9 UART transmitter data VIL= 0.35*VDD_IO
GPIO function VIH=0.65*VDD_IO
Default Status: Output Type
Output: VOL=0.1*VDD_IO,
2
I S interface serial data input V OH=0.9*VDD_IO
I2S_DACDAT/UART_ Input: Schmitt trigger
I 25 UART request to send
RTS/GPIO10 VIL= 0.35*VDD_IO
GPIO function VIH=0.65*VDD_IO
Default Status: Input Type (Floating)
Output: VOL=0.1*VDD_IO,
2
I S interface serial data output V OH=0.9*VDD_IO
I2S_ADCDAT/UART_ Input: Schmitt trigger
O 26 UART clear to send
CTS/GPIO11 VIL= 0.35*VDD_IO
GPIO function VIH=0.65*VDD_IO
Default Status: Output Type
FLASH_CS I 27 Flash chip selection Pull high 100k to VDD_IO
7. Function Description
7.1. System Connection
7.1.1. USB Type-C Headset
VOUT_SWR
4.7uF
4.7uF 2.2uF 2.2uF 2.2uH 1uF 1uF 1uF
MICVDD
LDO_ADDA_O
DCVDD
AV18
VOUT_SWR
SW
VBUS
D3V3
VDD_I/O
LDO
LDO LDO_ _AV18 1uF
_DV33 IO VREF
LDO
4.7uF
_ADDA
LDO DACREF
_DIG
Buck 2.2uF
Converter CPVPP
CPP1
2.2uF
CPN1
LDO CPP2
VBUS
VBUS _MICVDD
2.2uF
CPN2
2.2uF
CPVEE
USB DP
DP USB 2.0
Type-C DM
DM
Controller
Connector
2.2K
ALC5686
MICBIAS2
2.2uF
IN1P_SLEEVE
SLEEVE_GND Headset
SLEEVE_SENSE
6.25k/1% RING2_GND
RREF Headset Interface
RING2_SLEEVE
HPO_L
HPO_R
10k/5% FLASH_CS Flash
VDD_IO
Memory CPVREF
EPAD(DGND)
DACGND
AGND2
AGND
PGND
4.7uF
4.7uF 2.2uF 2.2uF 2.2uH 1uF 1uF 1uF
MICVDD
LDO_ADDA_O
DCVDD
AV18
VOUT_SWR
SW
VBUS
D3V3
VDD_I/O
LDO
LDO LDO_ _AV18 1uF
_DV33 IO VREF
LDO
4.7uF
_ADDA
LDO DACREF
_DIG
Buck 2.2uF
Converter CPVPP
CPP1
2.2uF
CPN1
LDO CPP2
VBUS
VBUS _MICVDD
2.2uF
CPN2
2.2uF
CPVEE
USB DP
DP USB 2.0
Type-C DM
DM
Controller
Connector
2.2K
ALC5686 MICBIAS1
IN1P_RING2
RING2_SENSE
2.2uF
CITA, OMTP or TRS Device
w/ Jack Detection
RING2
RING2_GND
L
HPO_L
6.25k/1% CPVREF GND
RREF JD1/JD2 VBUS
DET
1M R
HPO_R
SLEEVE
SLEEVE_GND
SLEEVE_SENSE or
DACGND
AGND2
AGND
PGND
8. Electrical Characteristics
8.1. Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings
Parameter Symbol Min Typ Max Units
Power Supplies
USB Power VBAT -0.3 - 71 V
o
Operating Ambient Temperature Ta -25 - +85 C
o
Storage Temperature Ts -55 - +125 C
ESD Protection
Human Body Model (HBM) All Pins Pass +/-3500V
Note:
1. VBUS =5V with 3.5% duty cycle power bouncing up to 7V is acceptable.
2. VBUS is the power source of the whole chip’s power rail.
9. Package Information
9.1. Mechanical Dimensions
o r
k f
t e l
l i a
e a t ek
R e t n
i d a n
n f P
C o