Week 5
Week 5
Bindu Agarwalla
1
STACK
0
.
2k -1
STACK [Assumption: The machine is byte addressable
and each element in the stack occupies 4Bytes]
Push Operation 0
• SP always points to the top element, so .
to push a newitem, first, it has to be
updated to the location, where a new
element can be pushed. SP=1976 19 Current top
• As stack grows downward in the 1980 -12 element
memory, so first SP is decremented,
then the NEWITEM is pushed. 1984 23
2k -1
19 NEWITEM
STACK [Assumption: The machine is byte addressable
and each element in the stack occupies 4Bytes]
Push Operation 0
• If stack stack starts in memory from .
2000, then the initial value of SP
should be 2004, then only the 1st
element will be pushed at correct SP=1976 19 Current top
location. element
1980 -12
1984 23
1988 88 Stack
1992
1996
2000 56 Bottom
element
.
2k -1
19 NEWITEM
STACK [Assumption: The machine is byte addressable
and each element in the stack occupies 4Bytes]
Pop Operation 0
• SP always points to the top element, so .
to pop an element, first, it has to be
popped off, then the SP need to be
updated to the next top element.
• As stack grows downward in the SP=1980 -12 Current top
memory, so SP is incremented, after element
the top item is popped off. 1984 23
1988 88 Stack
Move (SP), ITEM 1992
ADD #4,SP 1996
↓ 2000 56 Bottom
Move (SP)+, ITEM element
.
2k -1
-12 ITEM
Limitation of Link Register
and use of stack for subroutine
Linkage
Bindu Agarwalla
6
STACK[Assumption: the stack is from 2000 to 1500]
SafePush Operation
In a full stack, push operation should not be
SAFEPUSH Compare #1500, SP done. So, if the value of SP is 1500 or less than
1500, that means already the stack is full. Hence,
Branch <= 0 FULLERROR compare operation gives either 0 or a negative
value after the operation. If SP is 1500, then the
Move NEWITEM, -(SP) next push operation will be done at 1496, which
is not the part of stack.
SafePop Operation
Return
2000
PC 1004
Link 1004
Call Return
Limitation??
No support for Nesting of Functions.
Limitation of Link Register
and use of stack for subroutine
Linkage
Bindu Agarwalla
10
Limitation of Link Register
Nesting of functions/subroutines is not supported.
Solution
Using Stack: To support nesting of functions.
Assumptions:
Parameters are passed through general purpose registers.
Returning values through general purpose registers.
Example:
We are going to add N numbers stored in consecutive memory locations starting from
the symbolic address NUM1 using a function. the function is going to return the
summation result to the caller.
Limitation of Link Register
Nesting of functions/subroutines is not supported.
Stack as Subroutine Linkage Method
Calling program
1000 Move N, R1
1000 Move N, R1
Solution:
Parameters are passed onto the stack, before calling the function.
MOVE 16(SP), R1
MOVE 20(SP), R2 SP=1980 [R2]
CLEAR R0 1984 [R1]
MOVE 16(SP), R1
MOVE 20(SP), R2 1980 [R2]
CLEAR R0 1984 [R1]
MOVE 16(SP), R1
MOVE 20(SP), R2
CLEAR R0
LOOP Add (R2)+, R0
1992 1012
Decrement R1
1996 14 10
Branch > 0 LOOP
Move R0, 20(SP) 2000 RESULT OF
SUMMATION
MoveMultiple (SP)+, R0-R2
RETURN 2004 28
Stack as Subroutine Linkage Method[Parameter
Passing and returning value using stack
MOVE 16(SP), R1
MOVE 20(SP), R2
CLEAR R0
LOOP Add (R2)+, R0
Decrement R1
1996 10
14
Branch > 0 LOOP
2000 Result of summation
MoveMultiple (SP)+, R0-R2
RETURN 2004 28
Stack as Subroutine Linkage Method[Parameter
Passing and returning value using stack]
Calling program
29
Numerical 2
Suppose a program (or a program task) takes 1 billion instructions to execute on a
processor running at 2 GHz. Suppose also that 50% of the instructions execute in 3 clock
cycles, 30% execute in 4 clock cycles, and 20% execute in 5 clock cycles. What is the
execution time for the program or task?
Solution
Total Number instructions=N=109
S=CPI=3.7
R = 2GHz
So, T= (S x N)/R
= (3.7 x 109)/(2 x 109) sec= 1.85 sec
Basic Performance Equation
The basic performance equation, which is fundamental to measuring
computer performance, measures the CPU time, is as follows.
CPU Time To execute a program = T= time/program
Solution
Total Number instructions=N=10+5+5=20
Total cycles=7*10+11*5+6*5=70+55+30=155
S=CPI=155/20
R = 8GHz
So, T= (S x N)/R
= (155/20) x 20)/(8 x 109) sec= 19.375 x10-9 sec = 19.375 nsec.
Numerical 2
A program is running on an 8MHz processor. Assume that 50% instructions perform an
ALU operation, 30% instructions perform memory operation and 20% instructions
perform Branching. Further assume that instructions performing an ALU operation take 4
clock cycles, instructions performing memory operation take 9 clock cycles and
instructions performing Branching take 7clock cycles. What is the total time taken by the
program?
Solution
Total Number instructions=N=100
S=CPI=6.1
R = 8MHz
So, T= (S x N)/R
= (6.1 x 102)/(8 x 106) sec= 76.25 μ sec
Numerical 2
A program is running on an 8MHz processor. Assume that 50% instructions perform an
ALU operation, 30% instructions perform memory operation and 20% instructions
perform Branching. Further assume that instructions performing an ALU operation take 4
clock cycles, instructions performing memory operation take 9 clock cycles and
instructions performing Branching take 7clock cycles. What is the total time taken by the
program?
Solution
Total Number instructions=N=100
S=CPI=6.1
R = 8MHz
So, T= (S x N)/R
= (6.1 x 102)/(8 x 106) sec= 76.25 μ sec
Big Endian and
Little Endian Representation
35
Big Endian and Little Endian Concept
Little and big endian are two ways of storing multibyte data-types ( int, float,
etc). For Single Byte no ordering is required.
In byte ordering, the "big end" byte is called the "high-order byte" or the
"most significant byte".
The term ‘endian’ as derived from ‘end’ may lead to confusion. The end
denotes which end of the number comes first rather than which part comes at
the end of the sequence of bytes.
The basic endian layout can be seen in the table below:
40
Big Endian and Little Endian Concept
Example: Represent the integer 14342 in Big Endian and Little Endian
machines.
00 00 00 00 00 00 38 06
BIG ENDIAN
GATE Question On
Big Endian and Little Endian Representation
44
GATE 2021
If the numerical value of a 2-byte unsigned integer on a little endian computer
is 255 more than that on a big endian computer, which of the following
choices represent(s) the unsigned integer on a little endian computer?
a.0x6665
0x6566
b. 0x0001 0x00FF
c. 0x4243 0x6665
d. 0x0100
So, option a is correct
Solution: Let’s take the option a.
Little Endian= 0x6665
So, the original number= 0x6566
So, the big endian= 0x6566 , little endian= 0x6665
Given , Little endian=255 + Big endian
255= 1111 1111 =0xFF
GATE 2021
If the numerical value of a 2-byte unsigned integer on a little endian computer
is 255 more than that on a big endian computer, which of the following
choices represent(s) the unsigned integer on a little endian computer?
a.0x6665
0x0100
b. 0x0001 0x00FF
c. 0x4243 0x01FF
d. 0x0100
49
GATE 2018
A processor has 16 integer registers (R0, R1, … , R15) and 64 floating point
registers (F0, F1, … , F63). It uses a 2-byte instruction format. There are four
categories of instructions: Type-1, Type-2, Type-3, and Type 4. Type-1
category consists of four instructions, each with 3 integer register operands
(3Rs). Type-2 category consists of eight instructions, each with 2 floating
point register operands (2Fs). Type-3 category consists of fourteen
instructions, each with one integer register operand and one floating point
register operand (1R+1F). Type-4 category consists of N instructions, each
with a floating point register operand (1F).
(A) 32
(B) 64
(C) 256
(D) 512
GATE 2018
# of integer registers= 16, i.e., 4(24) bits are required to represent a integer
register.
# of fp registers= 64, i.e., 6(26) bits are required to represent a fp register.
4 4 4 4
int reg int reg
Type-1
4 6 6
fp reg fp reg
Type-2
6 4 6 Type-3
int reg fp reg
10 6 Type - 4
fp reg
GATE 2018
No of Type-1 instructions is : 4 x 212
Given, N x 26 = 211
N= 211/26 =25
N=32
GATE 2020
A processor has 64 registers and uses 16-bit instruction format. It has two types
of instructions: I-type and R-type. Each I-type instruction contains an opcode, a
register name, and a 4-bit immediate value. Each R-type instruction contains an
opcode and two register names. If there are 8 distinct I-type opcodes, then the
maximum number of distinct R-type opcodes is _____.
# of registers= 64, i.e., 6(26) bits are required to represent a register.
6 6 4 I-Type
Reg Imm
4 6 6 R - Type
Reg Reg
Let, N no of R-Type opcodes are possible
N x 212= 216- 8 x 26 x 24
N x 212= 216- 23 x 26 x 24
N = 24- 21 =14
Numerical 3
The content of register R1is 10110011. What will be the decimal value after execution
of following instruction. [Assume the number is represented in 2's complement format]
AShiftL #2, R1
0 1 0 1 1 0 0 1 1 R1
AShiftL#2, R1
1 0 1 1 0 0 1 1 0 R1
0 1 1 0 0 1 1 0 0 R1
Here, R1 contains -77 before the shift operation, and after the AshiftL 2 times,
it contains -11
Numerical 4
Execute the following instruction where Ro is of 8 bits and its content is
11001011.
i)Lshift L #2, Ro ii) Ashift R #1, Ro
0 1 1 0 0 1 0 1 1 R0
LshiftL#2, R0
1 1 0 0 1 0 1 1 0 R0
1 0 0 1 0 1 1 0 0 R0
Here, R0 contains -43 before the shift operation, and after the AshiftR 2 times,
it contains -11
Thank You