Addressing Modes

Bindu Agarwalla

1
 Addressing Modes
Consider the following program segment. Here R1, R2 and R3 are the
general purpose registers. Instruction Operation MOV
R1, (3000) R1←M[3000] LOOP: MOV R2, (R3)
R2←M[R3] ADD R2, R1 R2←R1+R2 MOV (R3), R2
M[R3] ←R2 INC R3 R3←R3+1 DEC R1
R1←R1-1 BNZ LOOP Branch on not zero HALT
Stop Assume that the content of memory location 3000 is 10 and the
content of the register R3 is 2000. The content of each of the
memory locations from 2000 to 2010 is 100. The program is loaded
from the memory location 1000. All the numbers are in decimal.
Assume that the memory is word addressable. How many number of
memory references for accessing the data in executing the program
completely?
 Addressing Modes
The addressing mode refers to the way in which the operand of an
instruction is specified.

Implied Mode: In this mode the operands are specified implicitly in the
definition of the instruction.

Ex. COM // Complement accumulator

No of memory references to execute this instruction is??

ONE
 Addressing Modes
Immediate Mode: In this mode, the operand is specified as part of the
instruction itself.
Ex: MOV #200, R1
Here the value 200 is moved to the register R1.
# is used to indicate an immediate operand.

No of memory references to execute the above instruction is??

ONE
 Addressing Modes
Register Mode: In this mode, the operand is specified as the content of a
general purpose register.
Ex: MOV R1,R2

No of memory references to execute the above instruction is??

ONE
 Addressing Modes
Direct Mode
In this mode, the operand is there in the memory, the address of the
operand is specified in the instruction only.

Ex: MOV NUM , R2

MOV 2000, R2
Note: The address can be specified either as a numeric value or as a
symbolic one.
R2

56

2000 56 NUM
No of memory references to execute the above
instruction is??

two
Memory
 Addressing Modes
Register Indirect Mode

In this mode, the operand is there in the memory, whose address is

specified as the content of a register.
Ex: MOV (R1), R2 // R2← mem[R1]

R1 R2
1000 56

1000 56
No of memory references to execute the above
instruction is??

two
Memory
 Addressing Modes
Memory Indirect Mode: In this mode, the operand is there in the memory, whose
address is specified as the content of another memory location in the instruction.
i.e., the address of the address of the operand is specified in the instruction.
Ex: MOV (500), R2 // R2← mem[mem[500]]
or,
MOV (num), R2 // R2← mem[R1]

R2
500 1000 num
56

1000 56
No of memory references to execute the above
instruction is??

three
Memory
 Problem
Program to add N numbers stored in memory location starting from
NUM1 LOCATION

MOVE N, R1
MOVE #NUM1, R2
CLEAR R0
LOOP ADD (R2), R0
ADD #4, R2

DECREMENT R1
BRANCH >0 LOOP
MOVE R0, SUM

H/ W: A=*B into assembly language code

 Index Mode
In this mode, the operand is there in the memory, whose address is the
sum of the offset and content of index register. Offset is specified in the
address of the instruction. offset represents relative displacement. i.e.,
how far the operand is located from the base.

Ex: MOV 20(R1), R2 // R2← mem[20+[R1]]

Note: In the effective address generation, index register content is not modified. It
is only used in the process.

R1 R2
1000 1000
78

No of memory references to execute the above

78 instruction is??
1020
two
Memory
 Index Mode: Where to use??

N n
LIST student id
LIST+4 test 1 Student 1
LIST+8 test 2
LIST+12 test 3
student
Student 2
test 1
test 2
test 3
.
.
If the 1st student data is stored in memory from location 1000, then the next
student data will found at location 1016.
 Problem
Program to add the average of score of three tests for a class having
N number of students.

MOVE #LIST, R0
CLEAR R1
CLEAR R2
CLEAR R3
MOVE N, R4

LOOP ADD 4(R0), R1

ADD 8(R0), R2
ADD 12(R0), R3 MOVE R1, SUM1
ADD #16, R0 MOVE R2, SUM2
Decrement R4 MOVE R3, SUM3
BRANCH > 0 LOOP
 Addressing Modes
Index Mode:

Another varaiants:
1. (Ri,Rj)
EA=[Ri] +[Rj]

2.
X(Ri,Rj)
EA=X+[Ri] +[Rj]
 Addressing Modes
Relative Mode: In this mode, the operand is there in the memory, whose address
is the sum of the offset and content of index register. Offset is specified in the
address of the instruction. offset represents relative displacement. i.e., how far the
operand is located from the base.
Ex: Branch > 0 LOOP

R2
500 1000 num
56

1000 56
No of memory references to execute the above
instruction is??

three
Memory
 Relative Mode
In this mode, the effective address is generated using offset and the
contents of PC Program Counter.
Ex: Branch > 0 LOOP

MOVE N, R1
MOVE #NUM1, R2
Here, when the branch instruction is
CLEAR R0 executed, that time, the value of PC
will be 1016(address of the next
1000: LOOP ADD (R2), R0
instruction), so from that value of PC,
1004 ADD #4, R2 we need to set PC at 1000, to jump to
the branch target instruction(add
1008 DECREMENT R1 instruction). So -16 will be added with
1016 to get the value 1000. -16 is
1012 BRANCH >0 LOOP represented as offset in the label of the
1016 MOVE R0, SUM branch instruction. here it is LOOP.
i.e., LOOP is repreented as -16.
 Autoincrement mode
In this mode, the operand is there in the memory. The effective address of the operand
is the contents of a register specified in the instruction. After accessing the operand,
the contents of the register is automatically incremented to point to the next item in a
list.

ADD (R2)+, R0

No of memory references to execute the above instruction is??

TWO
 Autodecrement mode
In this mode, the operand is there in the memory. The effective address of the operand
is the contents of a register specified in the instruction. Before accessing the operand,
the contents of the register is automatically decremented to point to the operand in a
list.

ADD -(R2), R0

No of memory references to execute the above instruction is??

TWO
 Problem
Program to add N numbers stored in memory location starting from
NUM1 LOCATION

MOVE N, R1
MOVE #NUM1, R2
CLEAR R0
LOOP ADD (R2)+, R0

DECREMENT R1
BRANCH >0 LOOP
MOVE R0, SUM
 Addressing Modes

Name Assemble syntax Addressin functio

• The different r g n
ways in which Immediate #Value O erand = Value
the location of p
an operand is Register Ri E = Ri
specified in an A
Absolute (Direct) LOC E = LOC
instruction are A
referred to as Indirect (Ri ) E = [Ri ]
addressing (LOC) A = [LOC
E
modes. A ]
Index X(R i) E = [Ri ] + X
A
Basewith index (Ri ,Rj ) E = [Ri ] + [Rj ]
A
Basewith index X(R i,Rj ) E = [Ri ] + [Rj ] + X
and offse A
t
Relative X(PC) E = [PC + X
A ]
Autoincrement (Ri ) E = [Ri ] ;
+ AIncrement Ri
Autodecrement − (Ri ) Decrement R i ;
E = [Ri]
A
 Assembler Directives
These are not executable statements, they are the directives/commands used by the
assembler, while translating a assembly language program to machine language
program.
Examples:

EQU:
SUM EQU 200

It informs the assembler that wherever SUM is used, should be replaced by the value
200.
DATAWORD:
NUM DATAWORD 200

END:
END START

RESERVE
NUM RESERVE 100
ORIGIN RETURN
ORIGIN 200
 Numericals
What is A two-word instruction is stored in a location A. The operand part of
instruction holds B. If the addressing mode is relative, the operand is available
in which location?

A relative mode branch type instruction is stored in memory at an address 750. The
branch is made to an address 500. What should be the value of the relative address field of
the instruction?
 Assembly Language Instruction
Label Operation Operand(s) comment

An instruction is stored at location 200 with it’s address field having the value 10. A
processor register R10 contains the value 210 which is also used as index register.
Evaluate the effective address of the operand if the addressing mode of the instruction is
(i)direct;(ii)register direct;(iii)register indirect;(iv)indexed.

How many memory references are required to execute the following

instructions?
i)ADD (R1) , R3 where R3 is the destination
ii)SUB #600 , R5 where R5 is the destination
 Numericals
An instruction is a 24 bit instruction. It is a byte addressable memory. The PC
contains 300. Which one of the following is a legal PC value:

a. 400 (b) 500 (c) 600 (d) 700

Register R1 and R2 of a computer contains the decimal value100 and 200. What are the
effective address of memory operand in each of the following instruction?
i)LOAD 20 (R2), R1
ii)MOVE 300, R5
iii)ADD (R1), R2
iv)MUL (R1)+, R5
 Numericals
a)A machine has a 32-bit architecture, with 1-word long instructions. It has 60
registers, each of which is 32 bits long. It needs to support 45 instructions,
which have an immediate operand in addition to two register operands.
Assuming that the immediate operand is an unsigned integer, what is the
maximum value of the immediate operand?
 Numericals
A two-word instruction is stored in memory at an address designated by the symbol P.
The address field of the instruction (stored at P+1) is designated by the symbol Q. The
operand used during the execution of the instruction is stored at an address symbolized
by EA. An index register contains the value X. State how EA is calculated from the
other addresses if the addressing mode of the instruction is direct, indirect, relative, and
indexed.
 Numericals
Write the number of memory references required for executing the following
instructions:
i)ADD R1,(R2)+
ii)SUB #10,R2
iii)MOV R1, 20(R3,R4)
iv)AND R1,R2
v)Increment A
 Numericals
An instruction is kept in memory at an address 300 and the memory address 301 occupies
the address field of the instruction which is shown below. The Opcode is used to add the
content of accumulator with an operand. The content of accumulator is 100 and the
content register R5 is 400. Find out the content of accumulator and Effective address of
operand if the addressing mode is
(i) immediate (ii) direct (iii) register direct (iv) indirect (v) register indirect
Address Instruction
300 Opcode Mode

301 500

400 700

401 456

500 600

600 800
 Numericals
A general purpose register organization computer has a 16 bit instruction
consisting of opcode, source register and a destination register. It supports 7 no of
arithmetic operations and 6 no of logical operations. Find the total number of
maximum registers present in the system.

Consider a processor with 64 registers that supports twelve instructions. Each instruction
has five distinct fields, namely, opcode, two source register fields, one destination register
field, and a twelve-bit immediate value. Each instruction must be stored in memory in a
byte-aligned fashion. If a program has 100 instructions, What is the amount of memory
(in bytes) consumed by the program?
 Numericals
A two word instruction LOAD is stored at location 1000 with its address field at location
1001. The address field has the value 2000 and the value stored at 2000 is 5000 and at
5000 is 6500. The words stored at 2200, 3002 are 3500, 4000 respectively. An index
register has value 200. Evaluate the effective address and operand if addressing mode of
the instruction is as follows:
I. Memory Indirect Addressing Mode
II. Relative Addressing Mode
III. Index Addressing Mode
 Numericals
Write the equivalent instructions for Zero Address Organization and One
Address Organization of the following instructions:
MOV P, R1
SUB Q, R1
DIV R, R1
MUL S, R1
MOV R1, X
 Numericals
Both of the following statements cause the value 150 to be stored in location
2000
ORIGIN 2000
DATAWORD 150
And
Move #150,2000
Explain the difference.
 Numericals
Match each of the high level language statements given on the left hand side
with the most natural addressing mode from those listed on the right hand side.

1. A[1] = B[J]; a) Indirect addressing

2. while [*A++]; b) Indexed, addressing
3. int temp = *x; c) Autoincrement

Match columns:
A B
Indirect Relocatable code
Index Passing array as a parameter
Base Register Array
Auto increment while (*A++)
 Home Work
A program is requiredfor the task C[i]=A[i] x B[i] Write a program for this task
on a computer that supports one address instructions. Assume thatC,A[i]and
B[i]are located in main memory and the values is stored in main memory
location N.
 Instruction Set
An extensive set of instructions are provided to carry out various computational task.

According to the operation carried out by the computer , the instructions are classified into
3 categories:

1. Data Transfer Instruction

2. Data Manipulation Instruction

a. Arithmetic Instruction
b. Logical Instruction

c. Shift Instruction

3. Program Control Instruction

Types of Instructions
• Data Transfer Instructions
Name Mnemonic
Data value is not
Load LD modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Types of Instructions
• Data Transfer Instructions
Name Mnemonic
Data value is not
Load LD modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Types of Instructions
• Data Transfer Instructions
Name Mnemonic
Data value is not
Load LD modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
Data Manipulation Instructions
• Arithmetic Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Negate NEG
Data Manipulation Instructions
• Logical & Bit Manipulation

Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Complement carry COMC
Enable interrupt EI
Disable interrupt DI
 Data Manipulation Instructions
AND:
is used to reset some specific bit position in a register , keeping all
other bits intact( unchanged).
R1 0 1 0 1 1 0 0 1

Let say, we want to change the bit position 4th to 0 , without distrubing all other bits. Then
we need to AND all other bits with 1 and 4th bit with 0. As, X AND 1=X
and X AND 0=0

0 1 0 1 1 0 0 1

AND 1 1 1 1 0 1 1 1

0 1 0 1 0 0 0 1

AND #F7H, R1
 Data Manipulation Instructions
OR:
is used to SET some specific bit position in a register , keeping all
other bits intact( unchanged).
R1 0 1 0 1 1 0 0 1

Let say, we want to change the bit position 3rd to 1 , without distrubing all other bits. Then
we need to OR all other bits with 0 and 4th bit with 1. As, X OR 1=1
and X OR 0=X

0 1 0 1 1 0 0 1

OR 0 0 0 0 0 1 0 0

0 1 0 1 1 1 0 1

OR #04, R1
Data Manipulation Instructions
XOR:
is used to CLEAR the contents of a register .

R1 0 1 0 1 1 0 0 1

As. X XOR X=0

0 1 0 1 1 0 0 1

XOR 0 1 0 1 1 0 0 1

0 1 0 1 1 0 0 1

XOR R1, R1
 Problems
SETC:
CF ← 1

CLRC:

CF ← 0

COMC:

CF ← CF

EI

IF ← 1

DI:

IF ← 0
Data Manipulation Instructions
• Shift
Name Mnemonic
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right through carry RORC
Rotate left through carry ROLC
 Logical Left Shift Instruction
SHL: Logical left shift for unsigned numbers.
Provide a means for shifting blocks of bits within a register or memory.

C 0

The contents of the OPERAND are shifted left by the number of bits specified in the source
operand of the instruction. The vacated bits are filled with zeros. The shifted bits are passed
through the C flag, and then dropped. Left Shifting an operand is equivalent to multiplying
the operand by 2 (bit postions shifted)

R1 0 0 0 1 0 0 0 0 0

SHL #2, R1
0 0 1 0 0 0 0 0 0
R1
Logical Right Shift Instruction
SHR: Logical right shift for unsigned numbers.
Provide a means for shifting blocks of bits within a register or
memory.
0 REGISTER C

The contents of the OPERAND are shifted right by the number of bits specified in the source
operand of the instruction. The vacated bits are filled with zeros. The shifted bits are passed
through the C flag, and then dropped. Right Shifting an operand is equivalent to dividing the
operand by 2 (bit postions shifted)

R1 0 0 0 1 0 0 0 0 0

SHR #2, R1
0 0 0 0 0 1 0 0 0
R1
Arithmetic Left Shift Instruction
SHLA: Arithmetic left shift for signed numbers.
Provide a means for shifting blocks of bits within a register or
memory.
C 0

The contents of the OPERAND are shifted leftt by the number of bits specified in the source
operand of the instruction. The vacated bits are filled with zeros. The shifted bits are passed
through the C flag, and then dropped. Leftt Shifting an operand is equivalent to multiplying
the operand by 2 (bit postions shifted)

R1 0 0 0 1 0 0 0 0 0

SHL #2, R1
0 0 1 0 0 0 0 1 0 R1

SHLA affects the Overflow flag. V= Rn-2 XOR Rn-1 . i.e., the Overflow flag will be 1 if the
sign changes after the shift operation, else it will be 0.
Arithmetic Right Shift Instruction
SHRA: Arithmetic right shift for signed numbers.
Provide a means for shifting blocks of bits within a register or
memory.
0 REGISTER C

The contents of the OPERAND are shifted right by the number of bits specified in the source
operand of the instruction. The vacated bits are filled by the previous sign bit. The shifted bits
are passed through the C flag, and then dropped. Right Shifting an operand is equivalent to
dividing the operand by 2 (bit postions shifted)

R1 1 0 0 1 0 0 1 0 0

SHRA #1, R1
1 1 0 0 1 0 0 1 0
R1

Here, R1 contains -110 before the shift operation, and after the SHRA,
it contains -55
Arithmetic Right Shift Instruction
Example 1

R1 1 1 0 0 1 0 0 1 0

SHRA #1, R1

R1 1 1 1 0 0 1 0 0 1
Here, R1 contains -55 before the shift operation, and after the SHRA, it
contains -28
Example 2

R1 1 1 1 1 1 0 0 1

SHR #1, R1
R1 1 1 1 1 1 1 0 0 1
Here, R1 contains -7 before the shift operation, and after the SHRA, it
contains -4
Arithmetic Right Shift Instruction
Example 3

R1 0 0 0 0 1 1 1 1 0

SHRA #1, R1

R1 0 0 0 0 0 1 1 1 1

Here, R1 contains +15 before the shift operation, and after the SHRA, it
contains +7
 Representing Signed No in 2’s Complement Method
For a +ve Number, to represent in the 2’s complement method, sign bit should be made
0, i.e., the MSb should be 0 and for the magnitude part, just write the binary of the
number.
Example: + 14 in 8 bits:
MSb will be 0, then the binary of 14 in 7 bits, i.e., 0001110
So, +14= 00001110
For a -ve Number, to represent in the 2’s complement method, sign bit should be made
1, i.e., the MSb should be 1 and for the magnitude part, just take the 2’s complement of
the binary of the number. TThe 2’s complement of a binary can be taken by copying
the bits of the binary from the LSb till the 1st 1 is found, then all the remaining bits are
flipped.

Example: - 14 in 8 bits:
MSb will be 1,
then the binary of 14 in 7 bits, i.e., 0001110
Next take the 2’s complement of 0001110
So, start copying from LSb, 01 then flip all the remaining bits,
hence the result will be 1110010
So, -14= 11110010
 Rotate Right Instruction (ROR)
The bits of the destination are rotated right. The number of bits rotated is determined
by the source operand. The bits rotated out of the least significant bit of the operand go
to both the carry bit and the most significant bit of the operand.
 Rotate Left Instruction (ROL)
The bits of the destination are rotated left. The number of bits rotated is determined
by the source operand. The bits rotated out of the most significant bit of the operand go to
both the carry bit and the least significant bit of the operand.
 Rotate Right through Carry Instruction (ROR)
The bits of the destination are rotated right. The number of bits rotated is determined
by the source operand. The bits rotated out of the least significant bit of the operand go
to the carry bit and the previous carry bit goes to the most significant bit of the operand.
 Rotate Left through carryInstruction
(ROL)
The bits of the destination are rotated left. The number of bits rotated is determined
by the source operand. The bits rotated out of the most significant bit of the operand go to
both the carry bit and the previous carry bit goes to the least significant bit of the operand.
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL
Return RET
Compare (Subtract) CMP
Test (AND) TST
 Program Control Instructions
Call: is used to call a subroutine.
1000: Call P1
1004: Next Instruction
1. Stack[top]← [PC] // Return address, i.e., 1004 is stored onto the stack.
and then
2. PC← ADDRESS OF THE SUBROUTINE // Here it is represented by P1

Return: is used to return from a subroutine.

PC← Stack[top]// Return address, i.e., 1004 is restored from the stack.
 Program Control Instructions
Compare: is used to compare two numbers.
CMP src, dst
performs the operation: [dst] -[src]
Sets the condition code flags based on the result obtained.

Neither of the operands is changed.

 Program Control Instructions
Test: is used to check a particular bit position value of an operand.
TEST #bit position, operand
performs non-destructive AND operation.
Sets the condition code flags based on the result obtained.

Neither of the operands is changed.

 Register Transfer Notation
• Identify a location by a symbolic name standing for its hardware binary
address (LOC, R0,…)
• Contents of a location are denoted by placing square brackets around the
name of the location (R1←[LOC], R3 ←[R1]+[R2])
• Register Transfer Notation (RTN)
 Condition Codes
• Condition code flags
• Condition code register / status register
• N (negative)
• Z (zero)
• V (overflow)
• C (carry)
• Different instructions affect different flags
 Conditional Branch Instructions

• Example:
– A: 1 1 1 1 0 0 0 0 A: 11110000
– B: 0 0 0 1 0 1 0 0
+(−B): 1 1 1 0 1 1 0 0
11011100

C=1 Z=0
S=1
V=0
 Basic Performance Equation

• T – processor time required to execute a program that has been prepared in

high-level language
• N – number of actual machine language instructions needed to complete the
execution (note: loop)
• S – average number of basic steps needed to execute one machine instruction. Each
step completes in one clock cycle
• R – clock rate
• Note: these are not independent to each other

How to improve T?
Thank You