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ClassTest Part5

The document describes a 4-bit gray to binary converter using a basic FPGA 4-input LUT. It provides a truth table for the conversion and notes that only 2 LUTs are required to implement the logic. Assuming each LUT has a 5ns intrinsic delay, the total delay for the conversion would be 5ns since the LUTs operate in parallel. For a 6-input LUT, the total conversion delay would remain unchanged at 5ns.

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52 views2 pages

ClassTest Part5

The document describes a 4-bit gray to binary converter using a basic FPGA 4-input LUT. It provides a truth table for the conversion and notes that only 2 LUTs are required to implement the logic. Assuming each LUT has a 5ns intrinsic delay, the total delay for the conversion would be 5ns since the LUTs operate in parallel. For a 6-input LUT, the total conversion delay would remain unchanged at 5ns.

Uploaded by

Pooja S
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Class Test – Part 5

Given a basic FPGA 4-Input LUT as below, and assuming that you can
connect wires across the LUTs through interconnect, create a 4bit gray
to binary converter.

a> Create a truth table.

b> If each LUT takes 5ns intrinsic delay, what would be the total delay for the conversion.

c> How many LUTs are required.

d> Assume you had a 6bit LUT. Then what would be the total delay for the conversion.

Hint :: B0 = g0; B(i) = g(i) xor B(i-1).


B0 = g0; B(i) = g(i) xor B(i-1).

a> Truth Table


g2 g1 g0 b2 b1 b0

0 0 0 0 0 0

0 0 1 0 1 1

0 1 0 1 1 0

0 1 1 1 0 1

1 0 0 1 0 0

1 0 1 1 1 1

1 1 0 0 1 0

1 1 1 0 0 1

The logic would look like the below. For this there is need for only 2 LUT’s. (3 with pass through is also
correct answer). The g0  b0 can be implemented through simple interconnect.

b>
Since the LUT’s would be in parallel, the intrinsic delay of the full conversion will also be 5ns.

c> For a 6 input LUT there would be no change in total delay of conversion for this example.

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