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Chapter 4 - Ring Counter

The document describes a ring counter circuit using D flip-flops. A ring counter is a circuit that produces a rotating sequence of output pulses, where only one output is high at any given time. The circuit consists of 4 D flip-flops connected in a loop such that the output of one flip-flop feeds the input of the next. With an initial state of 1000, each clock pulse shifts the high state to the next flip-flop in sequence, rotating from 1000 to 0100 to 0010 and back to 1000, repeating the sequence. The document includes diagrams illustrating the output sequences over multiple clock cycles.

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Minh Phú
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54 views5 pages

Chapter 4 - Ring Counter

The document describes a ring counter circuit using D flip-flops. A ring counter is a circuit that produces a rotating sequence of output pulses, where only one output is high at any given time. The circuit consists of 4 D flip-flops connected in a loop such that the output of one flip-flop feeds the input of the next. With an initial state of 1000, each clock pulse shifts the high state to the next flip-flop in sequence, rotating from 1000 to 0100 to 0010 and back to 1000, repeating the sequence. The document includes diagrams illustrating the output sequences over multiple clock cycles.

Uploaded by

Minh Phú
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

Lecture:
DIGITAL SYSTEMS
Chapter 4:
Ring Counter

Assoc. Prof. Nguyen Thanh Hai, PhD


1
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Ring Counter
Ring Counter Using FF-D
1
D 1 PRE Q1 D 2 PRE Q D 3 PRE Q D 4 PRE Q
2 3 4

CLK CLK CLK CLK


CK
CLR Q1 CLR Q2 CLR Q3 CLR Q 4

According to this circuit, Q1=D2, Q2=D3, Q3=D4 1000


and Q4=D1 and assume that outputs Q1Q2Q3Q4
of 4 FFs-D are 1000. Thus at time no Ck, the
output Q1=D2=1, Q2=D3=0, Q3=D4=0, 0001 0100
Q4=D1=0; when Ck1 is 1st CK of FF1-D, make the
output Q1=D2=0, Q2=D3=1, Q3=D4=0,
Q4=D1=0; Ck2 making the output Q1=D2=0,
0010
Q2=D3=0, Q3=D4=1, Q4=D1=0; Ck3 making the
output Q1=D2=0, Q2=D3=0, Q3=D4=0, Q4=D1=1
and next CK, recounting as in figure. 2
Assoc. Prof Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Ring Counter
1 2

CLk
1000
Q1

Q2 0100
0001
Q3

Q4
0010
0100 0001 0100 0001
1000 0010 1000 0010
Cycle-1 Cycle- 2

In order to draw the output waveforms, Q1Q2Q3Q4 corresponding to 1000,


at Ck1, Q1=D2=1 shift through FF2, we obtain Q2=1 and D3=1, we have
0100; CK2, obtain 0010; CK3, we have 0001 and CK4 we have 1000,
complete 1 cycle. In figure, we represent 2 cycles.
3
Assoc. Prof Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Ring Counter
1 2 16
Clock

Q1

Q2

Q3

Q4

00000001 11110000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0

1000

0001 0100

4
0010
Assoc. Prof Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Ring Counter

The End

5
Assoc. Prof Nguyen Thanh Hai, PhD

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