EX NO: 01-a Date:

Study on ARM Cortex M series Controller

starter kit
Aim:
 To learn about the core features, general characteristics and applications of ARM processors using
ARM7 LPC2148 starter kit.

Theory:
The ARM7 LPC2148 starter kit is based on a 32/16 Bit ARM7TDMI-s CPU with real time Emulation
and Embedded Trace support, That combines with the microcontroller with embedded high speed 512KB flash
memory.

Features:

 32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.
 28 bit wide interface/accelerator enables high speed 60 MHz operation.
 In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.
 Single flash sector or full chip erase in 400 ms & programming of 256 bytes in 1 ms.
 Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip
 Real Monitor software and high speed tracing of instruction execution.
 USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM. In addition, the
LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA.
 One or two (LPC2141/2 vs LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog inputs,
with conversion times as low as 2.44 s per channel.
 Single 10-bit D/A converter provides variable analog output.
 Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM
unit (six outputs) and watchdog.
 Low power real-time clock with independent power and dedicated 32 kHz clock input.
 Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 Kbit/s), SPI and SSP
with buffering and variable data length capabilities.
 Vectored interrupt controller with configurable priorities and vector addresses.
 Up to nine edge or level sensitive external interrupt pins available.
 60 MHz maximum CPU clock available from on-chip PLL with settling time of 100s.
 On-chip integrated oscillator operates with an external crystal range from 1 MHz to 30 MHz and with
an external oscillator up to 50 MHz.
  Power saving modes include Idle and Power-down.
 Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional
power optimization.
 Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out Detect (BOD) or
Real-Time Clock (RTC).
 Single power supply chip with Power-On Reset (POR) and BOD circuits:
 CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.
 Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

On-board Peripherals:
 8-Nos. of Point LED’s (Digital Outputs)  Two UART for serial port communication
 8-Nos. of Digital Inputs (slide switch) through PC
 2 Lines X 16 Character LCD Display  Serial EEPROM
 I2C Enabled 4 Digit Seven-segment display  On-chip Real Time Clock with battery backup
 128x64 Graphical LCD Display  PS/2 Keyboard interface(Optional)
 4 X 4 Matrix keypad  Temperature Sensor
 Stepper Motor Interface  Buzzer(Alarm Interface)
 2 Nos. Relay Interface  Traffic Light Module
General Block Diagram

Power Supply:

 The external power can be AC or DC, with a voltage between (9V/12V, 1A output) at 230V AC input.
 The ARM board produces +5V using an LM7805 voltage regulator, which provides supply to the
peripherals.
 LM1117 Fixed +3.3V positive regulator used for processor & processor related peripherals.
General Block Diagram of LPC2148

Port Pins:

Port 0(P0.0 to P0.31): Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of
the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The
operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins P0.24, P0.26
and P0.27 are not available
Port 1(P1.0 to P1.31): Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The
operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 0 through 15 of
port 1 are not available.

Pin Details of LPC2148

On-chip flash program memory

The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory
system respectively. This memory may be used for both code and data storage. Programming of the flash
memory may be accomplished in several ways. It may be programmed In System via the serial port. Due to
the architectural solution chosen for an on-chip boot loader, flash memory available for user’s code on
LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively. The LPC2141/42/44/46/48
flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention.
On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit,
16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM
respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can
also be used as a general purpose RAM for data storage and code storage and execution.

10-bit ADC

The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital converters. These
converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six
channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2148 is 14.10 bit
successive approximation analog to digital converter. Measurement range of 0 V to VREF (2.5 V ≤ V REF
≤VDDA). Each converter capable of performing more than 400000 10-bit samples per second. Every analog
input has a dedicated result register to reduce interrupt overhead. Burst conversion mode for single or multiple
inputs.

10-bit DAC

The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output
voltage is the VREF voltage.

USB 2.0 device controller

The USB is a 4-wire serial bus that supports communication between a host and a number (127 max)
of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based
protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All
transactions are initiated by the host controller. The LPC2148 is equipped with a USB device controller that
enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface
engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream
and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. A DMA controller (available
in LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM.

UARTs
The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive data
lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface. Compared to
previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate
generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200
with any crystal frequency above 2 MHz.
I2C-bus serial I/O controller
The LPC2141/42/44/46/48 each contain two I2C-bus controllers. The I2C-bus is bidirectional, for inter-
IC control using only two wires: a Serial Clock Line (SCL), and a Serial DAta line (SDA). Each device is
recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a
transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data
transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus
master connected to it. The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s
(Fast I2C-bus).

SPI serial I/O controller

The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface,
designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single
slave can communicate on the interface during a given data transfer. During a data transfer the master always
sends a byte of data to the slave, and the slave always sends a byte of data to the master.

General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally
supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on
four match registers. It also includes four capture inputs to trap the timer value when an input signal
transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or
match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. The
LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is
equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as
regular timer capture inputs, or used as external interrupts.

Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it
enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails
to ‘feed’ (or reload) the watchdog within a predetermined amount of time
Real-time clock
The RTC is designed to provide a set of counters to measure time when normal or idle operating
mode is selected. The RTC has been designed to use little power, making it suitable for battery powered
systems where the CPU is not running continuously (Idle mode).
Pulse width modulator
The PWM is based on the standard timer block and inherits all of its features, although only the PWM
function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral
clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur,
based on seven match registers. The PWM function is also based on match register events. The ability to
separately control rising and falling edge locations allows the PWM to be used for more applications. For
instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual
control of all three pulse widths and positions. Two match registers can be used to provide a single edge
controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge controlled PWM
outputs require only one match register each, since the repetition rate is the same for all PWM outputs.
Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle,
when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges
controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the
two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers
each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs,
specific match registers control the rising and falling edge of the output. This allows both positive going PWM
pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the
falling edge occurs prior to the rising edge).

Mark Allocation

Experiment Conduction

Viva Voce

Total

Result:
Thus the ARM 7 LPC2148 starter kit has studied successfully.