32 Vedic

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.01.2023 00:31:21
// Design Name:
// Module Name: 16bit_vedic
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module modi_vedic32(
input [31:0] A,B,
output [63:0]M
);
wire [31:0]w1,w2,w3,w4;
wire [31:0]sum1,sum2;
wire cout1,cout2;
wire [31:0]temp;
wire [15:0]orout,sum3;
vedic_16x16 v1(A[15:0],B[15:0],w1);
vedic_16x16 v2(A[15:0],B[31:16],w2);
vedic_16x16 v3(A[31:16],B[15:0],w3);
vedic_16x16 v4(A[31:16],B[31:16],w4);
adder_32bits a1(w2,w3,1'b0,sum1,cout1);
assign temp={w1[31:16],w4[15:0]};
adder_32bits a2(temp,sum1,1'b0,sum2,cout2);
assign orout=(sum1[15:0])|(sum2[15:0]);
carry_select_adder_16bit a3(orout,w4[31:16], 1'b0, sum3, cout);
assign M={sum3,sum2,w1[15:0]};
endmodule
module ha(a, b, sum, carry);

// a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry=a&b;
assign sum=a^b;
endmodule
module vedic_2x2(a,b,c);
input [1:0]a;
input [1:0]b;
output [3:0]c;
wire [3:0]c;
wire [3:0]temp;
//stage 1
// four multiplication operation of bits accourding to vedic logic done using and
gates
assign c[0]=a[0]&b[0];
assign temp[0]=a[1]&b[0];
//stage two
// using two half adders
ha z1(temp[0],temp[1],c[1],temp[3]);
ha z2(temp[2],temp[3],c[2],c[3]);
endmodule
///////////////////////////////////////////////////////////////////////////////////
/////////////////////////
module half_adder(x,y,s,c);
input x,y;
output s,c;
assign s=x^y;
assign c=x&y;
endmodule // half adder
module full_adder(x,y,c_in,s,c_out);
input x,y,c_in;
output s,c_out;
assign s = (x^y) ^ c_in;
assign c_out = (y&c_in)| (x&y) | (x&c_in);
endmodule // full_adder
///////////////////////////////////////////////////////////////////////////////////
///////////////////////////
module add_4_bit(input1,input2,answer);
parameter N=4;
input [N-1:0] input1,input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for(i=0;i<N;i=i+1)
begin: generate_N_bit_Adder
if(i==0)
half_adder f(input1[0],input2[0],answer[0],carry[0]);
else
full_adder f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
parameter N=6;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for(i=0;i<N;i=i+1)
if(i==0)
else
end
endgenerate
endmodule
input [3:0]a;
input [3:0]b;
output [7:0]c;
wire [3:0]q0;
wire [3:0]q1;
wire [3:0]q2;
wire [3:0]q3;
wire [7:0]c;
wire [3:0]temp1;
wire [5:0]temp2;
wire [5:0]temp3;
wire [5:0]temp4;
wire [3:0]q4;
wire [5:0]q5;
wire [5:0]q6;
// using 4 2x2 multipliers
vedic_2x2 z1(a[1:0],b[1:0],q0[3:0]);
vedic_2x2 z2(a[3:2],b[1:0],q1[3:0]);
vedic_2x2 z3(a[1:0],b[3:2],q2[3:0]);
vedic_2x2 z4(a[3:2],b[3:2],q3[3:0]);
// stage 1 adders
assign temp1 ={2'b0,q0[3:2]};
add_4_bit z5(q1[3:0],temp1,q4);
assign temp3 ={q3[3:0],2'b0};
add_6_bit z6(temp2,temp3,q5);
assign temp4={2'b0,q4[3:0]};
// stage 2 adder
add_6_bit z7(temp4,q5,q6);
// fnal output assignment
assign c[1:0]=q0[1:0];
assign c[7:2]=q6[5:0];
endmodule
parameter N=8;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for(i=0;i<N;i=i+1)
if(i==0)
else
end
endgenerate
endmodule
parameter N=12;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for(i=0;i<N;i=i+1)
if(i==0)
else
end
endgenerate
endmodule
input [7:0]a;
input [7:0]b;
output [15:0]c;
wire [15:0]q0;
wire [15:0]q1;
wire [15:0]q2;
wire [15:0]q3;
wire [15:0]c;
wire [7:0]temp1;
wire [11:0]temp2;
wire [11:0]temp3;
wire [11:0]temp4;
wire [7:0]q4;
wire [11:0]q5;
wire [11:0]q6;
vedic_4x4 z1(a[3:0],b[3:0],q0[15:0]);
vedic_4x4 z2(a[7:4],b[3:0],q1[15:0]);
vedic_4x4 z3(a[3:0],b[7:4],q2[15:0]);
vedic_4x4 z4(a[7:4],b[7:4],q3[15:0]);
// stage 1 adders
add_8_bit z5(q1[7:0],temp1,q4);
// stage 2 adder
assign c[3:0]=q0[3:0];
assign c[15:4]=q6[11:0];
endmodule
parameter N=16;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for(i=0;i<N;i=i+1)
if(i==0)
else
end
endgenerate
endmodule
parameter N=24;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for(i=0;i<N;i=i+1)
if(i==0)
else
end
endgenerate
endmodule
input [15:0]a;
input [15:0]b;
output [31:0]c;
wire [15:0]q0;
wire [15:0]q1;
wire [15:0]q2;
wire [15:0]q3;
wire [31:0]c;
wire [15:0]temp1;
wire [23:0]temp2;
wire [23:0]temp3;
wire [23:0]temp4;
wire [15:0]q4;
wire [23:0]q5;
wire [23:0]q6;
vedic_8x8 z1(a[7:0],b[7:0],q0[15:0]);
vedic_8x8 z2(a[15:8],b[7:0],q1[15:0]);
vedic_8x8 z3(a[7:0],b[15:8],q2[15:0]);
vedic_8x8 z4(a[15:8],b[15:8],q3[15:0]);
// stage 1 adders
add_16_bit z5(q1[15:0],temp1,q4);
//stage 2 adder
assign c[7:0]=q0[7:0];
assign c[31:8]=q6[23:0];
endmodule

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`timescale 1ns / 1ps

module ha(a, b, sum, carry);

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