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Tutorial 1

This document contains 7 tutorial questions about cache memory design and analysis. It covers topics like determining the number of blocks, bits required for tags and data arrays in direct-mapped caches, calculating tag, index and offset bits based on cache and memory properties, finding tag sizes and memory sizes given cache parameters, and labeling example address traces as hits or misses in direct-mapped caches.

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Muhammad Harith B. Badzli
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19 views2 pages

Tutorial 1

This document contains 7 tutorial questions about cache memory design and analysis. It covers topics like determining the number of blocks, bits required for tags and data arrays in direct-mapped caches, calculating tag, index and offset bits based on cache and memory properties, finding tag sizes and memory sizes given cache parameters, and labeling example address traces as hits or misses in direct-mapped caches.

Uploaded by

Muhammad Harith B. Badzli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Tutorial 1

1. For a byte-addressable machine with 16-bit addresses with a cache with the following
characteristics:
• It is direct-mapped
• Each block holds one byte
• The cache index is the four least significant bits
(i) How many blocks does the cache hold?
(ii) How many bits of storage are required to build the cache (e.g., for the data array, tags, etc.)?

2. You have been asked to design a cache with the following properties:
• Data words are 32 bits each
• A cache block will contain 2048 bits of data
• The cache is direct mapped
• The address supplied from the CPU is 32 bits long
• There are 2048 blocks in the cache
• Addresses are to the word = 32 bits
Determine the number of tag, index and offset bits.

3. Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main
memory is 128 KB. Find (i) Number of bits in tag (ii) Tag directory size.
4. Consider a direct mapped cache of size 512 KB with block size 1 KB. There are 7 bits in the tag.
Find: (i) Size of main memory (ii)Tag directory size.

5. Consider a direct mapped cache with block size 4 KB. The size of main memory is 16 GB and
there are 10 bits in the tag. Find: (i) Size of cache memory (ii) Tag directory size.

6. Assuming a direct mapped cache with 16 cache line with each 4 word blocks, label the following
references as a hit or a miss and show the contents of the cache after each cycle. Assume that the
cache is initially empty. The referenced addresses in decimal are 20, 17, 1, 4, 8, 5, 56,89,100, 120,
100, 104, 108, 8, 4.

7. Given the following series of address references given as word addresses in hexadecimal: 0×4,
0×5C, 0×7, 0×92, 0×1E, 0×5F, 0×B0, 0×5D, 0×91, 0×108 and 0×6. Assuming a direct-mapped cache
with a word size of 32 bits and address of 11 bits has a cache with 16 blocks and a block size of 2
words. Indicate whether the reference is a hit (H) or miss (M). Assume the cache is initially

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