Laboratory Uvm - Info

LABORATORY
uvm_info
UVM reporter class name is uvm_report_server.The macro `uvm_info is a wrapper
around the uvm_report_info, it can be used to send messages to the report server,
while displaying the message to the console.
`uvm_info(“DEMO”, “Hello World”, UVM_NONE)
ID MESSAGE VERBOSITY
uvm_factory
UVM factory class name is uvm_factory. The factory is used to manufacture
(create) UVM objects and components.
All UVM objects and components in a UVM testbench must be registered into the
factory and created using factory.
uvm_configuration_db
UVM provides uvm_config_db,which is a class that provides a convenience
interface on top of the uvm_resource_db to simplify the basic interface that is used
for configuring uvm_component instances.
uvm_reporting
This Lab shows how to use uvm reporting macros for displaying messages,
warnings, errors, and fatal reports.
uvm_sformatf
This Lab shows how to use uvm reporting macros for printing variables in the console
using $sformatf, variables can be printed in different formats, such as, binary,
decimal, and, hexadecimal.
uvm_verbosity
HIGH
FULL
DEBUG
poo_inheritance
This Lab shows how class inheritance can be used to extend an existing class, by
adding new features, this feature is widely used in UVM testbench, thus, it is
important to understand its behavior and advantages.
poo_inheritance_virtual
This Labs shows how methods of parent class, can be redefined within a child
class by declaring methods in parent class as virtual. Virtual methods are used to
apply polymorphism dynamically (i.e. at run-time). NOTE: Constructor function
must always be non-virtual function.
Task run
Virtual task run

uvm_class_factory
This Lab shows how objects can be created dynamically, for this, a factory class can
be used; in this lab, a basic class called factory was created (created as example,
factory is already created within UVM package), where input argument "cat" is used
to select which type of user (child-class) is intended to be created, whether
hardware-tag or software-tag.
uvm_transaction_item_1
This lab presents how transactions in UVM must be declared.
uvm_transaction_item_3
This lab presents a transaction item created within an uvm_test object.
uvm_transaction_item_do_copy
This lab presents how uvm_objectcan be copied and cloned from another
uvm_object.
UVM_TLM_blocking_4 (put)
This lab presents a multiple TLM blocking put ports.
UVM_TLM_nonbloking
This lab presents a simpleTLM nonblockingport to transfer a transactions item.
This means that producer does not waits for the consumer to finish the operation.
UVM_TLM_bloking_get_1
This lab presents a simple TLM blocking port to transfer a transaction using get
port.
uvm_fifo
UVM_config_object_1
UVM_factory_override_1
UVM_VIF_1_verif
UVM_VIF_1_rtl
UVM_VIF_agent_verif
UVM_VIF_agent_rtl
UVM_simple_tb_1
UVM_simple_tb_rtl
…
UVM_VIF_agent_2
UVM_VIF_agent_2_rtl
ASSIGMENTS
Assignment 1. This assignment consists of displaying four variables in the console,

three 4-state and one 2-state variables in hexadecimal format using UVM reporting
macros.
Data tipe States
bit “0”, “1”
logic “0”, “1”, “x”, “z”
Assignment 2. This assignment consists of generating random stimulus for the input
ports of the following module using class-based coding. Use a class method to print
the values in hex. Hint: use randomize() class method.
Assignment 3.
Assignment 4.
Assignment 5.
Assignment 6.
This Lab shows how to create an uvm verification components by extending
uvm_component class.
Assignment 7.
This Lab shows how to create an uvm verification components by extending
uvm_test class.
Assignment 8.
1 2
3 4
5 6
7
Assignment 9.
This lab presents a simple TLM blocking port to transfer a transactions item. This
means that producer waits for the completion of the operation.
Assignment: Modify the code, so 10 transactions are generated and send through
blocking put port. This lab introduces phase objections.
Assignment 10.
Assignment 11.
Create the following testbench using nonblocking get port for transmitting
transactions for the following DUT.
Assignment 12.
Create a testbench using tlm_fifo class for connecting a producer and a consumer,
but, instead of transmitting int variables, transactions must be transmitted (you
decide the architecture of the transactions)
Assignment 13.
Instead of creating a new class subscriber2 extending uvm_component, reuse the
class subscriber1 (use inheritance and polymorphism). And presents how
uvm_analysis_port class can be used to transfer sequence items data type.

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LABORATORY

Virtual task run

Assignment 1. This assignment consists of displaying four variables in the console,

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