Smic Confidential: Semiconductor Manufacturing International Corporation

Semiconductor Manufacturing International Corporation
Doc. No.: Doc. Title: 0.18um V3E BCD Doc.Rev: Tech Dev.
TD-BC18-DM-2004 1.8V/5V/6V/9V/12V/16V/20V/24V/30V/35V 0 Rev:
/40V Platform Device Introduction and Character V1.20_REV
Design Manual
0
Document Level: (For Engineering & Quality Document/工程暨品质文件专用)

 Level 1 - Manual  Level 2 - Procedure/SPEC/Report  Level 3 - Operation Instruction
Security Level: Security A - Top Secret  Security B - SMIC Confidential
 Security C - SMIC Restricted  Security D - SMIC Internal
Document Change History
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Doc. Tech Dev. Effective Author Change Description
Rev. Rev. Date
TI
0 V1.20_REV 2022-03-09 Mary Shi Initiate
0
EN
ID
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IC
SM
The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in
whole or in part without prior written permission of SMIC.
Doc. No.: Doc. Title: 0.18um V3E BCD Doc.Rev: Tech Dev Page No.:
TD-BC18-DM-2004 1.8V/5V/6V/9V/12V/16V/ 0 Rev:V1.2 1 / 281
20V/24V/30V/35V /40V 0_REV0
Platform Device
Introduction and Character
Design Manual
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION
0.18um V3E BCD 1.8V/5V/6V/9V/12V/16V/20V/24V/30V/35V /40V Platform Device Introduction
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and Character Design Manual
TI
EN
Version V1.20_REV0
ID
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SMIC Confidential – Do Not Copy

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IC
SM
According to: SMIC Document Control Procedure; Attachment No.: QR-QUSM-02-2001-023; Rev.:2 2017-11-02
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
CONTENTS
1. TITLE: .............................................................................................................................................8
2. PURPOSE: ........................................................................................................................................8
3. SCOPE: ............................................................................................................................................8
4. NOMENCLATURE: ............................................................................................................................8
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5. REFERENCE:....................................................................................................................................8
6. RESPONSIBILITY: .............................................................................................................................8
7. SUBJECT CONTENT: ........................................................................................................................9
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7.1. INTRODUCTION ...............................................................................................................................9
7.1.1. Document Overview...............................................................................................................9

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7.1.2. Process Overview ..................................................................................................................9
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7.1.3. Supported Potentials ..............................................................................................................9

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7.1.4. 0.18um Tech. Seal Ring and Scribe Lane ............................................................................10

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7.2. DEVICE CHARACTERIZATION SUMMARY ....................................................................................... 11
7.2.1. LV/MV devices characterization summary .......................................................................... 11

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7.2.1.1. 1.8V NMOS (n18_ckt) ................................................................................................ 11

7.2.1.2. 1.8V PMOS (p18_ckt) .................................................................................................16
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7.2.1.3. 1.8V native NMOS (nnt18_ckt) ..................................................................................20

7.2.1.4. 5V NMOS (n50_ckt) ...................................................................................................23
7.2.1.5. 5V PMOS (p50_ckt) ....................................................................................................27
7.2.1.6. 5V native NMOS (nnt50_ckt) .....................................................................................32
7.2.1.7. 1.8V and 5V in HVBN pocket .....................................................................................35
7.2.2. LDMOS/DEMOS devices characterization summary .........................................................41
7.2.2.1. 5V NLDMOS (D4) (nld5g5_sa_iso_hvbn_ckt) ..........................................................42

7.2.2.2. 6V NLDMOS (nld6g5_sa_iso_hvbn_ckt) ...................................................................46
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7.2.2.3. 9V NLDMOS (nld9g5_gs_iso_hvbn_ckt) ...................................................................50

7.2.2.4. 9V NDEMOS (nde9g5_gs_iso_hvbn_ckt) ..................................................................55
7.2.2.5. 12V NLDMOS (nld12g5_gs_iso_hvbn_ckt) ...............................................................59
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7.2.2.6. 12V NDEMOS (nde12g5_gs_iso_hvbn_ckt) ..............................................................63
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7.2.2.10.
7.2.2.11.
EN
24V NLDMOS (nld24g5_gs_iso_hvbn_ckt) ...............................................................80
30V NLDMOS (nld30g5_gs_iso_hvbn_ckt) ...............................................................85
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7.2.2.13. 35V NLDMOS (nld35g5_rox_gs_ckt) ........................................................................92
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7.2.2.14. 40V NLDMOS (nld40g5_rox_gs_ckt) ........................................................................97

7.2.2.15. 5V PDEMOS (pde5g5_sa_hvbn_ckt) ........................................................................102
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7.2.2.16. 6V PDEMOS (pde6g5_sab_hvbn_ckt) ......................................................................106

7.2.2.17. 9V PDEMOS (pde9g5_gs_hvbn_ckt) ....................................................................... 110
7.2.2.18. 12V PDEMOS (pde12g5_gs_hvbn_ckt) ................................................................... 115
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7.2.2.19. 16V PDEMOS (pde16g5_gs_hvbn_ckt) ...................................................................120

SM

7.2.2.23. 35V PDEMOS (pde35g5_sti_hvbn_ckt) ...................................................................138
7.2.2.24. 40V PDEMOS (pde40g5_sti_hvbn_ckt) ...................................................................140
7.2.3. Bipolar Transistor characterization data summary...........................................................143
7.2.3.1. 1.8V vertical PNP (pnp18a100_ckt) ..........................................................................143

7.2.3.2. 1.8V vertical PNP (pnp18a25_ckt) ............................................................................146
7.2.3.3. 1.8V vertical PNP (pnp18a4_ckt) ..............................................................................148
20V/24V/30V/35V /40V 0_REV0
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Design Manual
7.2.3.4. 5V vertical PNP (pnp50a100_poly_ckt) ....................................................................150

7.2.3.5. 5V vertical PNP (pnp50a25_poly_ckt) ......................................................................153
7.2.3.6. 5V vertical NPN (npn50a100_sab_ckt ) ....................................................................154
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7.2.3.7. 5V vertical NPN (npn50a25_sab_ckt ) ......................................................................157
7.2.3.8. HV lateral PNP (pnphva100_poly_ckt ) ....................................................................160
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7.2.3.9. HV lateral PNP (pnphva25_poly_ckt ) ......................................................................161
7.2.3.10. HV vertical NPN (npnhva100_poly_ckt ) .................................................................163
7.2.3.11.
7.2.3.12.
EN
HV vertical NPN (npnhva25_poly_ckt ) ...................................................................166
HVBN ISO lateral PNP (pnphvbniso100_poly_ckt ) ................................................169
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7.2.3.13. HVBN ISO lateral PNP (pnphvbniso25_poly_ckt ) ..................................................171
7.2.3.14. High Beta vertical NPN (npnhbeta100_poly_ckt) .....................................................173
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7.2.3.15. High Beta NPN (npnhbeta100_sab100_ckt) .............................................................175

7.2.3.16. High Beta NPN (npnhbeta100_sab25_ckt) ...............................................................177
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7.2.3.17. High Beta NPN (npnhbeta100_sab4_ckt) .................................................................180
7.2.4. Diode characterization data summary ..............................................................................182

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7.2.4.1. 1.8V N+/Pwell diode (ndio18) ..................................................................................182

7.2.4.2. 1.8V P+/N-well diode (pdio18) .................................................................................185
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7.2.4.5. 1.8V N-well/Psub diode (nwdio18) ...........................................................................190
7.2.4.6. 5V N+/Pwell diode (ndio50) .....................................................................................192
7.2.4.7. 5V P+/Nwell Diode (pdio50).....................................................................................195
7.2.4.8. 5V Nwell/Psub Diode (nwdio50) ..............................................................................198
7.2.4.9. 5V Pwell/HVBN Diode (pwhvbndio50)....................................................................199
7.2.4.10. HV Pwell/HVBN Diode (pwhvbndiohv) ...................................................................200
7.2.4.11. 5V HVBN/Psub Diode (hvbnpsubdio50) ..................................................................201
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Design Manual
7.2.4.12. HVBN/Psub Diode (hvbnpsubdio) ............................................................................202

7.2.4.13. Zener Diode (5.5V) ....................................................................................................203
7.2.4.14. Schottky Diode (30V) ................................................................................................205
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7.2.5. ESD PNP characterization data summary ........................................................................207
7.2.5.1. 9V ESD Protection.....................................................................................................208
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7.2.5.2. 12V ESD Protection...................................................................................................210
7.2.5.3.
7.2.5.4.
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16V ESD Protection...................................................................................................212
20V ESD Protection...................................................................................................214
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7.2.5.5. 24V ESD Protection...................................................................................................216
7.2.5.6. 30V ESD Protection...................................................................................................218
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7.2.5.7. 35V ESD Protection...................................................................................................220

7.2.5.8. 40V ESD Protection...................................................................................................221
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7.2.6. ESD MOS characterization data summary........................................................................224
7.2.6.1. 1.8V N GGMOS (n1d8_esd_ckt) ..............................................................................224

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7.2.6.2. 1.8V P GDMOS (p1d8_esd_ckt) ...............................................................................226

7.2.6.3. 1.8V ESD N+/Pwell Diode (ndio1d8_esd) ................................................................227
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7.2.6.4. 1.8V ESD P+/Nwell Diode (pdio1d8_esd) ................................................................228

7.2.6.5. 5V N GGMOS (n5_esd_ckt) .....................................................................................228
7.2.6.6. 5V N GRMOS ...........................................................................................................230
7.2.6.7. 5V P GDMOS (p5_esd_ckt) ......................................................................................230
7.2.6.8. 5V ESD N+/Pwell Diode (ndio5_esd) .......................................................................231
7.2.6.9. 5V ESD P+/Nwell Diode (pdio5_esd) .......................................................................232
7.2.6.10. 6V P GDMOS (p6_esd_ckt) ......................................................................................232
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Design Manual
7.2.7. Capacitor characterization data summary ........................................................................233
7.2.7.1. MIM location options ................................................................................................233

7.2.7.2. 1.0fF MIM .................................................................................................................237
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7.2.7.3. 2fF MIM ....................................................................................................................238
7.2.7.4. MOM .........................................................................................................................239
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7.2.7.5. Top metal MOM ........................................................................................................241
7.2.7.6. 1.8V NMOS Varactor ................................................................................................241
7.2.7.7. EN
5V NMOS Varactor ...................................................................................................243
7.2.7.8. 5V NMOS Varactor in HVBN ...................................................................................245
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7.2.8. Resistor characterization data summary ...........................................................................246
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7.2.8.1. 1K ohm/sq P- Poly HRI w/o silicide .........................................................................247

7.2.8.2. 3K ohm/sq P- Poly HRI w/o silicide .........................................................................249
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7.2.8.3. P+ Poly w/o silicide ...................................................................................................251

7.2.8.4. P+ Poly w/i silicide ....................................................................................................253
7.2.8.5. N+ Poly w/o silicide ..................................................................................................255
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7.2.8.6. N+ Poly w/i silicid .....................................................................................................257

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7.2.8.7. P+ DIFF w/o silicide ..................................................................................................259

7.2.8.8. P+ DIFF w/i silicide...................................................................................................262
7.2.8.9. N+ DIFF w/o silicide .................................................................................................263
7.2.8.10. N+ DIFF w/i silicide ..................................................................................................265
7.2.8.11. NW diff(under AA) ....................................................................................................266
7.2.8.12. NW diff(under STI) ...................................................................................................267
7.2.8.13. 5V NW diff(under AA) ..............................................................................................269
7.2.8.14. 5V NW diff(under STI) .............................................................................................270
7.2.8.15. M1 Resistor (rm1)......................................................................................................272
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Design Manual
7.2.8.16. M2 Resistor (rm2)......................................................................................................272

7.2.8.17. M3 Resistor (rm3)......................................................................................................273
7.2.8.18. M4 Resistor (rm4)......................................................................................................274
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7.2.8.19. M5 Resistor (rm5)......................................................................................................275
7.2.8.20. TM_8K (rtm_8k) .......................................................................................................276
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7.2.8.21. TM_9K (rtm_9k) .......................................................................................................277
7.2.8.22. TM_33K (rtm_33k) ...................................................................................................280
7.2.8.23. EN
TM_40K (rtm_33k) ...................................................................................................280
7.2.9. MVN to MVP BV ................................................................................................................281

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8. ATTACHMENT: NA ......................................................................................................................281
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20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
1. Title:
0.18um V3E BCD 1.8V/5V/6V/9V/12V/16V/20V/24V/30V/35V /40V Platform Device
Introduction and Character Design Manual
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2. Purpose:
This design manual defines the 0.18um V3E BCD technology and provides 0.18um V3E BCD all
TI
devices typical characterization data
3. Scope:
All SMIC TD/Fabs
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4. Nomenclature:
ID
LDMOS: Channel length fix |Vgs| ≤5V.
DEMOS: Channel length changeable, |Vgs| ≤5V.
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5. Reference:
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Reference documents Reference Tech

Item Reference documents title
No version
0.18um V3E BCD
0.18um V3E BCD 1.8V/2.5V/5V/6V/9V/12V/16V/20
TD-BC18-SP-2006 V1.20_REV2
IC
spice model V/24V/30V/35V/40V SPICE

Model
0.18um V3E BCD
SM
0.18um V3E BCD TD-BC18-DR-201

1.8V/5V/6V/9V/12V/16V/20V/24V V1.20_REV0
design rule 0
/30V/35V/40V Design Rule
6. Responsibility:
TD is responsible for this design manual maintenance before the technology is transferred to FAB; Fab/PIE
is responsible for this design manual maintenance after the technology is transferred to FAB.
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7. Subject Content:
7.1. Introduction
7.1.1. Document Overview
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Following is a brief overview of the contents:
Section 7.2, Device Characterization summary -Describes the devices available in the process,
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layout, cross section, device symbol, spice data vs PCM spec, operating potentials,
characterization curve.
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Section 7.3, Isolation-Identify the rules for isolation
7.1.2. Process Overview

ID
0.18um V3E BCD is a 0.18um process to cover 0.18um BCD V3 and 0.152um PMU suitable
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for all Power IC applications at or below 40V.

1 FEOL : 1.8/5V+HV low-Ron LDMOS
2 BEOL: follow 0.15um CT/VIA/metal cover 1.8/5V shrink requirement.
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1.8V kept as 1.8/5V baseline ( 84% shrink) , IO 5V N/P MOS Lg shrink to 0.5/0.45um from
BL 0.6 / 0.5 um.
3 Pure-5V process: parasitic 2.5/3.3V for standard-cell.
4 Parasitic LVT 1.8/5V CMOS in 1.8V/5V/HV process.
IC
The process features thin/thick gate oxide and complementary MOSFETs with 1.8V/5V and
LDMOS structure with 5V/6V/9V/12V/16V/20V/24V/30V/35V/40V. The basic process
includes 6 layers of metal.
SM
7.1.3. Supported Potentials
0.18um V3E BCD is designed for operation up to 40V. The allowed operating voltages for
each device are outlined in detail under the device descriptions found in Section 2, Device
characterization summary. Any deviations from the allowed potentials given for each device,
even momentary spikes, take the device out of the operating region that SMIC has qualified.
Therefore, any deviations are at the customer's risk.
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Design Manual
7.1.4. 0.18um Tech. Seal Ring and Scribe Lane
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TI
EN
ID
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20V/24V/30V/35V /40V 0_REV0
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Design Manual
7.2. Device Characterization summary
7.2.1. LV/MV devices characterization summary
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Vtgm Vtlin Vtsat Idlin Idsat IOFF BV Ron
Device name
(V) (V) (V) (μA/μm) (μA/μm) (pA/μm) (V) (mΩ*mm2)
n18_ckt - 0.41 0.37 77.30 593.74 23 6.05 0.387
TI
p18_ckt - -0.49 -0.43 -38.30 -242.49 -10 -6.05 1.514
nnt18_ckt - 0.04 0.02 40.49 342.54 - 6.61 NA
n50_ckt
p50_ckt
0.80
-0.74
0.74
-0.77
0.60
-0.71
62.22
-18.06
EN
602.01
-295.66
0.13
0.35
12.02
-9.96
1.446
4.709
nnt50_ckt 0.08 0.094 0.13 22.63 416.82 - 12.52 NA
ID
7.2.1.1. 1.8V NMOS (n18_ckt)
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1) Device description
Device description 1.8V NMOS
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Model name n18_ckt

Terminal count 4
Terminal definition DGSB
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SLDD NLL
DLDD NLL
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2) Operation voltage range

Voltage (V) Max. tolerance
|Vgs| 1.8 +10%
|Vds| 1.8 +10%
|Vbs| 1.8 +10%
3) Device symbol
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4) Layout
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ID
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5) Cross section
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IC
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6) Device curve
Vtlin Vtsat Idlin Idsat IOFF BV Pitch Ron

Device name
(V) (V) (μA/μm) (μA/μm) (pA/μm) (V) (um) (mΩ*mm2)
n18_ckt 0.41 0.37 150 593.74 23 6.05 0.58 0.387
C-V curve
1) Fitting Cgg vs Vgs of n18_ckt W/L/M=50um/50um/1 at temp=25C
2) Fitting Cgc vs Vgs of n18_ckt W/L/M =400um/0.5um/40 at temp=25C
20V/24V/30V/35V /40V 0_REV0
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Design Manual
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EN
IDVG and ISUB
ID
NF
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IC
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DC-SOA
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Design Manual
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EN
Noise
ID
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Design Manual
Mismatch
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EN
ID
NF
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Design Manual
7.2.1.2. 1.8V PMOS (p18_ckt)
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Device description 1.8V PMOS
Model name p18_ckt
Terminal count 4
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SLDD PLL
DLDD PLL EN
ID
|Vgs| 1.8 +10%
NF
|Vds| 1.8 +10%

|Vbs| 1.8 +10%
3) Device symbol
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IC
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4) Layout
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Design Manual
5) Cross-section
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6) Device curve
EN
Idlin IOFF Pitch Ron
ID
Vtlin Vtsat Idsat BV
Device name (μA/μm (pA/μm (um) (mΩ*mm2)
(V) (V) (μA/μm) (V)
) )
NF
p18_ckt -0.49 -0.43 -38.30 -242.49 -10 -6.05 0.58 1.514

CO
C-V curve
1) Fitting Cgg vs Vgs of p18_ckt W/L/M=50um/50um/1 at temp=25C
2) Fitting Cgc vs Vgs of 1.8V p18_ckt W/L/M =400um/0.5um/40 at temp=25C
IC
SM
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Design Manual
IDVG
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EN
ID
DC-SOA
NF
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IC
SM
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Design Manual
Noise
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EN
Mismatch
ID
NF
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Design Manual
7.2.1.3. 1.8V native NMOS (nnt18_ckt)
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Device description 1.8V native NMOS
Model name nnt18_ckt
Terminal count 4
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Terminal definition D G S B
SLDD NLL
DLDD NLL

EN
ID
|Vgs| 1.8 +10%
|Vds| 1.8 +10%
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|Vbs| 1.8 +10%
3) Device symbol
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IC
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4) Layout
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Design Manual
5) Cross-section
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6) Device curve
EN
ID
Vtlin Vtsat Idlin Idsat IOFF BV
Device name
(V) (V) (μA/μm) (μA/μm) (pA/μm) (V)
nnt18_ckt 0.04 0.02 40.49 342.54 17.71 6.61
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IDVD
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IC
SM
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Design Manual
IDVG
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EN
ID
Noise
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Design Manual
7.2.1.4. 5V NMOS (n50_ckt)
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Device description 5V NMOS
Model name n50_ckt
TI
Terminal count 4
SLDD
NLDD
NLH
NLH
EN
ID

NF
|Vgs| 5 +10%
|Vds| 5 +10%
|Vbs| 5 +10%
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3) Device symbol
IC
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4) Layout
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Design Manual
5) Cross-section
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6) Device curve
EN
ID
Vtsa Pitch Ron
Vtgm Vtlin Idlin Idsat IOFF BV
Device name t (um) (mΩ*mm
(V) (V) (μA/μm) (μA/μm) (pA/μm) (V) 2)
(V)
NF
n50_ckt 0.80 0.74 0.60 62.22 602.01 0.13 12.02 0.9 1.446
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C-V curve
Fitting Cgg vs Vgs of n50_ckt W/L/M=50um/50um/1 at temp=25C
IC
SM
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Design Manual
IDVG and ISUB
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EN
ID
NF
DC-SOA
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IC
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Design Manual
TLP-SOA
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EN
ID
Noise
NF
CO
IC
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Mismatch
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Design Manual
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TI
EN
7.2.1.5. 5V PMOS (p50_ckt)
ID
NF
Device description 5V PMOS

Model name p50_ckt
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Terminal count 4
SLDD PLH
IC
DLDD PLH

SM

|Vgs| 5 +10%
|Vds| 5 +10%
|Vbs| 5 +10%
3) Device symbol
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Design Manual
4) Layout
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5) Cross-section
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ID
NF
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6) Device curve
Device Vtgm Vtlin Vtsat Idlin Idsat IOFF BV Pitch Ron
name (V) (V) (V) (μA/μm) (μA/μm) (pA/μm) (V) (um) (mΩ*mm2)
p50_ckt -0.74 -0.77 -0.71 -18.06 -295.66 0.35 -9.96 0.85 4.709
IC
SM
C-V curve
1) Fitting Cgg vs Vgs of p50_ckt W/L/M=50um/50um/1 at temp=25C
2) Fitting Cgc vs Vgs of p50_ckt W/L/M=5000um/0.45um/1 at temp=25C
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IDVG and ISUB
EN
ID
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CO
IC
DC-SOA
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
TLP SOA
EN
ID
NF
CO
IC
Mismatch
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.1.6. 5V native NMOS (nnt50_ckt)
AL
Device description 5V native NMOS
Model name nnt50_ckt
Terminal count 4
TI
Terminal definition D G S B
SLDD NA
DLDD NA

EN
ID
|Vgs| 5 +10%
|Vds| 5 +10%
NF
|Vbs| 5 +10%
3) Device symbol
CO
IC
SM
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Cross-section
AL
TI
6) Device curve
EN
ID
Vtgm Vtlin Vtsat Idlin Idsat IOFF BV
Device name
(V) (V) (V) (μA/μm) (μA/μm) (pA/μm) (V)
nnt50_ckt 0.08 0.094 0.13 22.63 416.82 0.24 12.52
NF
IDVD
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
IDVG
AL
TI
EN
Noise
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Mismatch
AL
TI
EN
ID
NF
CO
IC
SM
7.2.1.7. 1.8V and 5V in HVBN pocket
1) 1.8V NMOS in HVBN pocket
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
PWH to
NWH
D1 D2 D3 D4 EN
*ISO6 0um 16V 15V 11V 54V
ID
*ISO12 1.6um 25V 15V 11V 54V
*ISO30 2um 40V 15V 11V 54V
*ISO40 5um 54V 15V 11V 54V
NF
2) 1.8V PMOS in HVBN pocket

CO
IC
SM
PWH to
D1 D2
NWH
*ISO6 0um 16V 54V
3) 1.8V PMOS in HVBN pocket 7 terminal
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Note: NW 和 HVBN 中间的 psub 非常薄，不能耐压，所以 NW 和 HVBN 必须同电位
PWH to NWH D1 D2 D3 D4 D5
EN
*ISO6 0um 16V 15V 15V 54V 10.5V
ID
*ISO12 1.6um 25V 15V 15V 54V 10.5V
*ISO30 2um 40V 15V 15V 54V 10.5V
NF
*ISO40 5um 54V 15V 15V 54V 10.5V

CO
4) 1.8V Fully PMOS

IC
SM
B1
PWH to NWH D1 D2 D3 D4 D5 D6
(P+/NW/PWHT)
*ISO6 0um 16V 15V 15V 54V 10.5V
*ISO12 1.6um 25V 15V 15V 54V 10.5V
*ISO30 2um 40V 15V 15V 54V 10.5V
*ISO40 5um 54V 15V 15V 54V 10.5V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) 1.8V Native in HVBN pocket
AL
TI
EN
PWH to NWH D1 D2 D3
ID
*ISO6 0um 16V 15V 54V
*ISO12 1.6um 25V 15V 54V
NF
*ISO30 2um 40V 15V 54V

*ISO40 5um 54V 15V 54V
CO
6) 5V NMOS in HVBN pocket

IC
SM
PWH to NWH D1 D2 D3 D4
*ISO6 0um 16V 16V 42V 54V
*ISO12 1.6um 25V 16V 42V 54V
*ISO30 2um 40V 16V 42V 54V
*ISO40 5um 54V 16V 42V 54V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7) 5V PMOS in HVBN pocket
AL
TI
EN
ID
PWH to NWH D1 D2
*ISO6 0um 16V 54V
NF
*ISO12 1.6um 25V 54V

*ISO30 2um 40V 54V
*ISO40 5um 54V 54V
CO
8) 5V PMOS in HVBN pocket 7 terminal

IC
SM
*ISO6 0um 16V 16V 16V 42V 54V
*ISO12 1.6um 25V 16V 16V 42V 54V
*ISO30 2um 40V 16V 16V 42V 54V
*ISO40 5um 54V 16V 16V 42V 54V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
9) 5V Fully PMOS
AL
TI
EN
ID
PWH to B1
D1 D2 D3 D4 D5 D6 D7
NWH (P+/NWH/PWHT)
*ISO6 0um 16V 16V 16V 18 27.5 54V 10.5V 10.5V
NF
*ISO12 1.6um 25V 16V 16V 18 27.5 54V 10.5V 10.5V

*ISO30 2um 40V 16V 16V 18 27.5 54V 10.5V 10.5V
*ISO40 5um 54V 16V 16V 18 27.5 54V 10.5V 10.5V
CO
10) 5V Native in HVBN pocket

IC
SM
*ISO6 0um 16V 16V 42V 54V 15V
*ISO12 1.6um 25V 16V 42V 54V 15V
*ISO30 2um 40V 16V 42V 54V 15V
*ISO40 5um 54V 16V 42V 54V 15V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.2. LDMOS/DEMOS devices characterization summary
Vtsat Idsat Ron

Pitch Vtgm Vtlin (V) Idlin (μA/μm) IOFF BV
Device name
(um) (V) (V) (μA/μm) (pA/μm) (V) (mΩ*mm2)
AL
nld5g5_sa_iso_hvbn_ckt 0.84 1.48 1.18 - 69 - 0.047 12.9 1.18
nld6g5_sa_iso_hvbn_ckt 0.94 1.46 1.2 - 63.6 - 0.059 13.8 1.5
nld9g5_gs_iso_hvbn_ckt 1.33 1.43 1.29 - 43 - 0.069 19.8 2.9
TI
3T 2.10 -
nde9g5_gs_iso_hvbn_ckt 0.92 0.92 25 390 0.1 20.1 NA
4T 2.44
nld12g5_gs_iso_hvbn_ckt
nde12g5_gs_hvbn_ckt
1.53
3T 2.20
1.41
0.92
1.26
0.92
-
-
EN 40
22
-
375
0.081
0.1
21.8
22
3.6
NA
4T 2.54
ID
NF
nde20g5_gs_iso_hvbn_ckt 3.82 0.95 1 - 15.9 298 0.04 34 NA

nld24g5_gs_iso_hvbn_ckt 2.68 1.37 1.2 - 24 - 0.108 38 10.5
nld30g5_gs_iso_hvbn_ckt 3.23 1.34 1.18 - 19.5 - 0.175 41 16.6
CO
nde30g5_gs_iso_hvbn_ckt 4.92 0.95 1 - 12.35 281 0.06 38.5 NA

nld35g5_rox_gs_ckt 3.44 0.88 0.78 - 13 - 0.19 54 26
nld40g5_rox_gs_ckt 3.84 0.87 0.76 - 12 - 0.29 55 32
pde5g5_sa_hvbn_ckt 0.83/1.43 -0.75 -0.7 -0.63 -20.75 -303.9 -0.3 -9.2 3.7
IC
3T 1.48
pde6g5_sab_hvbn_ckt -0.92 -1.06 -1.04 -16.5 -260 -0.3 -11 7.6
4T 1.82
SM
3T 1.78
pde9g5_gs_hvbn_ckt -0.82 -1.00 -0.60 -10 -250 -0.3 -17.6 15
4T 2.12
3T 1.88
pde12g5_gs_hvbn_ckt -0.82 -1.02 -0.99 -9 -245 -0.3 -22.5 20
4T 2.22
3T 2.33
pde16g5_gs_hvbn_ckt -0.92 -1.03 -0.82 -7.0 -225 -0.3 -31.2 30
4T 2.67
3T 2.53
pde20g5_gs_hvbn_ckt -0.92 -0.87 -0.78 -6.7 -220 -0.3 -34.2 35
4T 2.87
3T 2.98
pde24g5_gs_hvbn_ckt -0.92 -1.05 -0.78 -6 -210 -0.3 -40.4 45.6
4T 3.32
3T 4.23
pde30g5_gs_hvbn_ckt -0.92 -1.1 -0.81 -4.4 -185 -0.3 -45 89.6
4T 4.57
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.2.1. 5V NLDMOS (D4) (nld5g5_sa_iso_hvbn_ckt)
AL
Device description 5V NLDMOS
Model name nld5g5_sa_iso_hvbn_ckt
TI
Terminal count 6
Terminal definition d g s b hvbn psub
SLDD
DLDD
NA
NA
EN
ID
|Vgs| 5 +10%
NF
|Vds| 5 +10%
3) Device symbol
CO
IC
SM
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Cross-section
AL
TI
Parasitic Diode
Diode D1 D2 D3
EN D4 D5 D6
BV 25V 25V 42V 54V 40V 40V
ID
PWH to PWH to PWH to NDRF=0.1
Space
NWH=1.6um NWH=1.6um um
NF
6) Device curve (D4, LB=D2)

All numbers are for a device with Width=40um, length=0.2um
Pitch Vtgm Vtlin Idlin IOFF BV Ron
CO
Device name
nld5g5_sa_iso_hvbn_ckt 0.84 1.48 1.18 69 0.047 12.9 1.18
IC
Ron-Vgs Curve
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA
AL
TI
EN
Idlin
ID
Vdmax (V) @ t 0.1%=0.2yrs
Vg (V)
(△idlin≥10%)
NF
0 11
1.25 6.3
2.5 6.2
CO
4 5.8
5.5 5.5
IC
Self-protection
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
FOM
Idlin Pitch Ron W Qgg Qgd Qgg*Ron Qgd*Ron
(μA/μm) (um) (mΩ*mm2) (um) (nC) (nC) (nC*mΩ) (mC*Ω)
69 0.84 1.18 40000 0.31 0.089 11.304 3.223
AL
TI
EN
ID
NF
7.2.2.2. 6V NLDMOS (nld6g5_sa_iso_hvbn_ckt)

CO
Model name nld6g5_sa_iso_hvbn_ckt
IC
Terminal count 6
SLDD NA
SM
DLDD NA

|Vgs| 5 +10%
|Vds| 6 +10%
3) Device symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
4) Layout
EN
ID
NF
CO
5) Cross-section
IC
SM
Parasitic Diode
Diode D1 D2 D3 D4 D5 D6
BV 25V 25V 42V 54V 40V 40V
Space
6) Device curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Device name
nld6g5_sa_iso_hvbn_ckt 0.94 1.46 1.2 63.6 0.059 13.8 1.5
AL
Ron-Vgs Curve
TI
EN
ID
NF
DC SOA curve
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
NF
HCI SOA
CO
IC
SM
Idlin
Vg (V)
(△idlin≥10%)
0 10.75
1.25 6.53
2.5 7.59
4 6.3
5.5 4.96
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Self-protection
AL
TI
EN
ID
FOM
NF
(μA/μm) (um) (mΩ*mm2) (um) (nC) (nC) (nC*mΩ) (nC*mΩ)

63.6 0.94 1.5 40000 0.366 0.106 14.387 4.169
CO
IC
SM
7.2.2.3. 9V NLDMOS (nld9g5_gs_iso_hvbn_ckt)
Model name Nld9g5_gs_iso_hvbn_ckt
Terminal count 6
SLDD NA
NLDD NA
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

|Vgs| 5 +10%
|Vds| 9 +10%
AL
3) Device symbol
TI
EN
ID
4) Layout
NF
CO
IC
5) Cross-section
SM
Parasitic Diode
BV 25V 25V 42V 54V 40V 40V
Space
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
6) Device curve
Device name
nld9g5_gs_iso_hvbn_ckt 1.33 1.43 1.29 43 0.069 19.8 2.9
AL
Ron-Vgs Curve
TI
EN
ID
NF
CO
DC SOA curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
TLP SOA curve
EN
ID
NF
CO
IC
SM
HCI SOA
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Idlin
Vg (V)
(△idlin≥10%)
0 18
AL
1.25 15.18
2.5 10.4
4 14.74
TI
5.5 9.4
Self-protection EN
ID
NF
CO
IC
FOM
SM

43 1.33 2.9 20000 0.176 0.036 20.465 4.186
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.2.4. 9V NDEMOS (nde9g5_gs_iso_hvbn_ckt)
Device description 9V NDEMOS
AL
Model name nde9g5_gs_iso_hvbn_ckt
Terminal count 6
TI
SLDD NA
DLDD NA

EN
ID
|Vgs| 5 +10%
|Vds| 9 +10%
NF
3) Device symbol
CO
IC
SM
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Cross-section
3T
AL
TI
4T EN
ID
NF
Parasitic Diode/BJT
CO
BV 25V 25V 42V 54V 40V 40V
Space
IC
6) Device curve
SM

Pitch Vtgm Vtlin Idlin Idsat IOFF BV
Device name
(um) (V) (V) (μA/μm) (μA/μm) (pA/μm) (V)
nde9g5_gs_iso_hvbn_ckt 3T 2.1/4T 2.44 0.92 0.92 25 390 0.1 20.1
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Ron-Vgs Curve (3T)
AL
TI
DC SOA curve
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
HCI SOA
NF
CO
IC
SM
Idlin
Vg (V)
(△idlin≥10%)
0 19
1.25 12.43
2.5 11.97
4 12
5.5 11.28
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
Model name nld12g5_gs_iso_hvbn_ckt
Terminal count 6
TI
SLDD NA
DLDD NA EN
ID
|Vgs| 5 +10%
NF
|Vds| 12 +10%
3) Device symbol
CO
IC
SM
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Cross-section
AL
TI
EN
Parasitic Diode
ID
BV 25V 25V 42V 54V 40V 40V
NF
Space
6) Device curve
CO

Device name
IC
SM
Ron-Vgs curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA curve
AL
TI
EN
ID
Idlin
DC ≥ 0.2yr
Vg (V) Vbd
Vdmax_T0.1
NF
0 23 29
1.25 14.9 28
2.5 18 25.4
CO
4 17 21.5
5.5 11 17.3
IC
Self-protection
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
FOM
40 1.53 3.6 20000 0.203 0.0535 25.375 6.693
AL
TI
EN
ID
NF
CO

IC
Terminal count 6
SM
SLDD NA
DLDD NA

|Vgs| 5 +10%
|Vds| 12 +10%
3) Device symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
4) Layout
EN
ID
NF
5) Cross-section
CO
3T
IC
SM
4T
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Parasitic Diode
BV 25V 25V 42V 54V 40V 40V
Space
AL
6) Device curve
All numbers are for a device with Width=40u length m, =0.45um
TI
Device name
nde12g5_gs_hvbn_ckt 3T 2.2/4T 2.54 0.92 0.92 22 EN375 0.1 22
ID
Ron-Vgs Curve (3T)
NF
CO
IC
SM
DC SOA curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
TLP SOA curve
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA curve
AL
TI
EN
ID
Idlin
DC ≥ 0.2yr
Vg (V) Vbd/V
Vdmax_T0.1
NF
0 22 27.5
1.25 20 26
CO
2.5 19.6 25
4 14 22
5.5 18 22.5
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Terminal count 6
SLDD
DLDD
NLH
NLH
EN
ID
|Vgs| 5 +10%
NF
|Vds| 16 +10%
3) Device symbol
CO
IC
SM
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Cross-section
AL
TI
Parasitic Diode
EN
ID
BV 40V 40V 42V 54V 40V 40V
NF
Space
NWH=2um NWH=2um um
6) Device curve
CO

Device name
IC
SM
Ron-Vgs Curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA curve
AL
TI
Idlin
EN
DC ≥ 0.2yr
ID
Vg (V) Vbd/V
Vdmax_T0.1
0 26.5 40
NF
1.25 20.1 40
2.5 25 37
4 27 38
CO
5.5 20 40
Self-protection
IC
SM
FOM
32 1.98 6.3 20000 0.221 0.046 34.531 7.212
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
7.2.2.8. 20V NLDMOS (nld20g5_gs_iso_hvbn_ckt) EN
ID

NF
Model name Nld20g5_gs_iso_hvbn_ckt

Terminal count 6
CO
SLDD NLH
DLDD NLH
IC

SM

|Vgs| 5 +10%
|Vds| 20 +10%
3) Device symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
4) Layout
AL
TI
5) Cross-section
EN
ID
NF
CO
IC
Parasitic Diode
SM
BV 40V 40V 42V 54V 40V 40V

Space
NWH=2um NWH=2um um
6) Device curve
Device name
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Ron-Vgs Curve
AL
TI
EN
DC SOA curve
ID
NF
CO
IC
SM
TLP SOA curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
HCI SOA curve
NF
CO
IC
SM
Idlin
DC ≥ 0.2yr
Vg (V)
Vdmax_T0.1
0 34.8
1.25 24
2.5 27
4 26
5.5 20.8
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Self-protection
D18V3E RF39 HT0215#15 20V GS

NLDMOS ESD TW Vs. IT2
10
AL
8 y = -通用格式x - -通用格式
It2 (A)
6 R² = -通用格式
4
TI
2
0
5000 10000 15000 20000
Total Width (um)
EN
FOM
ID
NF
29 2.18 7.7 20000 0.2 0.054 34.483 9.270

CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Terminal count 6
SLDD
DLDD
NLH
NLH
EN
ID

NF
|Vgs| 5 +10%
|Vds| 20 +10%
CO
3) Device symbol
IC
SM
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Cross-section
AL
TI
Parasitic Diode
Diode D1 D2 D3
EN D4 D5 D6
BV 40V 40V 42V 54V 40V 40V
ID
Space
NWH=2um NWH=2um um
NF
6) Device curve (4T)

CO

Device name
nde20g5_gs_iso_hvbn_ckt 3.82 0.95 1 15.9 298 0.04 34
IC
Ron-Vgs Curve
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA
AL
TI
EN
ID
Idlin
Vg (V)
(△idlin≥10%)
NF
0 27
1.25 25
2.5 27
CO
4 27
5.5 25
IC

SM
Device description 24 NLDMOS

Terminal count 6
SLDD NLH
DLDD NLH
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

|Vgs| 5 +10%
|Vds| 24 +10%
3) Device symbol
AL
TI
EN
4) Layout
ID
NF
CO
5) Cross-section
IC
SM
Parasitic Diode
BV 40V 40V 42V 54V 43V 40V
Space
NWH=2um NWH=2um um
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
6) Device curve
Device name
nld24g5_gs_iso_hvbn_ckt 2.68 1.37 1.2 24 0.108 38 10.5
AL
Ron-Vgs curve
TI
EN
ID
NF
CO
DC SOA curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
TLP SOA curve
ID
NF
CO
IC
SM
HCI SOA curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Idlin
DC ≥ 0.2yr
Vg (V)
Vdmax_T0.1
0 34.8
1.25 30
AL
2.5 32
4 28
5.5 22.4
TI
Self-protection
EN
ID
NF
CO
IC
FOM
SM

24 2.68 10.5 20000 0.205 0.047 42.708 9.792
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
Terminal count 6
d g s b hvbn psub
TI
Terminal definition
SLDD NLH
DLDD NLH

EN
ID
|Vgs| 5 +10%
NF
|Vds| 30 +10%
3) Device symbol
CO
IC
SM
4) Layout
5) Cross-section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Parasitic Diode
Diode D1 D2 D3
EN D4 D5 D6
BV 40V 40V 42V 54V 43V 40V
ID
Space
NWH=2um NWH=2um um
NF
6) Device curve
CO

Device name
nld30g5_gs_iso_hvbn_ckt 3.23 1.34 1.18 19.5 0.175 41 16.6
IC
Ron-Vgs curve
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA curve
AL
TI
Idlin
EN
DC ≥ 0.2yr
Vg (V) Vbd/V
ID
Vdmax_T0.1
0 40 52
1.25 40 52
NF
2.5 38 49
4 36 45
5.5 32 43
CO
Self-protection
IC
SM
FOM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

19.5 3.23 16.6 20000 0.213 0.050 54.615 12.849
AL
TI
EN
ID
NF

CO

Terminal count 6
IC
SLDD NLH
DLDD NLH
SM

|Vgs| 5 +10%
|Vds| 30 +10%
3) Device symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
5) Cross-section EN
ID
NF
CO
Parasitic Diode
IC
BV 40V 40V 42V 54V 40V 40V

SM
Space
NWH=2um NWH=2um um
6) Device curve (4T)

Device name
nde30g5_gs_iso_hvbn_ckt 4.92 0.95 1 12.35 281 0.06 38.5
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Ron-Vgs Curve
AL
TI
DC SOA curve
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
HCI SOA
NF
CO
IC
SM
Idlin
Vg (V)
(△idlin≥10%)
0 38
1.25 31.2
2.5 33.2
4 38
5.5 36.6
7.2.2.13. 35V NLDMOS (nld35g5_rox_gs_ckt)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Model name nld35g5_rox_gs_ckt
Terminal count 4
AL
Terminal definition dgsb
SLDD NA
TI
DLDD NA
|Vgs|
5 +10%
EN
|Vds| 35 +10%
ID
3) Device symbol
NF
CO
IC
4) Layout
SM
5) Cross-section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Parasitic Diode
Diode D1 D2 D3
BV 60V
PWH
60V
to PWH
54V EN
to PWH to DDN=0.1
Space
NWH=5um NWH=5um um
ID
NF
6) Device curve
Device name
(μA/μm) (pA/μm)
CO
(um) (V) (V) (V) (mΩ*mm2)

nld35g5_rox_gs_ckt 3.44 0.88 0.78 13 0.19 54 26
IC
Ron-Vgs curve
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
HCI SOA curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Idlin
EN
ID
Vg (V)
(△idlin≥10%)
0 55.6
NF
1.25 39.6
2.5 44.6
4 41.4
CO
5.5 35
IC
Self-protection
SM
FOM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
13 3.44 26 20000 0.224 0.027 86.154 10.354
AL
TI
EN
ID
7.2.2.14. 40V NLDMOS (nld40g5_rox_gs_ckt)
NF
Model name nld40g5_rox_gs_ckt
CO
Terminal count 4
Terminal definition dgsb
SLDD NA
IC
DLDD NA
SM

|Vgs| 5 +10%
|Vds| 40 +10%
3) Device symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
4) Layout
EN
ID
NF
CO
IC
5) Cross-section
SM
Parasitic Diode
Diode D1 D2 D3
BV 60V 60V 54V
Space PWH to NWH=5um PWH to NWH=5um PWH to DDN=0.1 um
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
6) Device curve
Device name
nld40g5_rox_gs_ckt 3.84 0.87 0.76 12 0.29 55 32
AL
Ron-Vgs curve
TI
EN
ID
NF
CO
DC SOA curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
TLP SOA curve
EN
ID
NF
CO
IC
HCI SOA curve

SM
Idlin
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Vg (V)
(△idlin≥10%)
0 63.2
1.25 40
2.5 53.5
AL
4 45.6
5.5 42
TI
Self-protection
EN
ID
NF
CO
FOM
IC

SM
12 3.84 32 20000 0.226 0.027 94.167 11.25
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.2.15. 5V PDEMOS (pde5g5_sa_hvbn_ckt)
AL
Device description 5V PDEMOS
Model name pde5g5_sa_hvbn_ckt
Terminal count 5
TI
Terminal definition d g s b psub
SLDD PLH
DLDD PLH EN
ID
|Vgs| -5 +10%
NF
|Vds| -5 +10%
3) Device symbol
CO
IC
SM
4) Layout
5) Cross-section
Only with N+ Body pick up AA ring, without N+ Body pick up AA
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
With N+ Body pick up AA ring and block
EN
ID
NF
Parasitic Diode
Diode D1 D2
CO
BV 25V 54V
PWH to
Space
NWH=1.6um
IC
6) Device Curve
SM
Vtli
Pitch Vtgm Vtsat Idlin Idsat IOFF BV Ron
n
Device name
(mΩ*mm
(μm) (V) (V) (V) (μA/μm) (μA/μm) (pA/μm) (V) 2)
pde5g5_sa_hvbn_ 0.83/1.4
-0.75 -0.7 -0.63 -20.75 -303.9 -0.3 -9.2 3.7
ckt 3
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Ron-Vgs Curve
AL
TI
DC SOA curve
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
HCI SOA curve
NF
CO
IC
SM
Idlin
DC ≥ 0.2yr
Vg (V)
Vdmax_T0.1
0 7.5
0.95 7.2
1.9 5.5
3.7 3.8
5.5 3.4
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Self-protection
AL
TI
EN
7.2.2.16. 6V PDEMOS (pde6g5_sab_hvbn_ckt)
ID
NF

Model name pde6g5_sab_hvbn_ckt
Terminal count 5
CO

SLDD PLH
DLDD PLH
IC

SM

|Vgs| -5 +10%
|Vds| -6 +10%
3) Device symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
5) Cross-section
3T
NF
CO
IC
4T
SM
Parasitic Diode
Diode D1 D2
BV 25V 54V
PWH to
Space
NWH=1.6um
6) Device Curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Pitch Vtgm Vtlin Vtsat Idlin Idsat IOFF
Ron BV
Device name 2
(μm) (V) (V) (V) (μA/μm) (μA/μm) (pA/μm) (V) (mΩ*mm )
pde6g5_sab_hvbn_ckt 3T1.48/4T1.82 -0.92 -1.06 -1.04 -16.5 -260 -0.3 -11 7.6
AL
TI
Ron-Vgs Curve
EN
ID
NF
CO
DC SOA curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
TLP SOA curve
EN
ID
NF
CO
IC
SM
HCI SOA curve
Idlin
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC ≥ 0.2yr
Vg (V) Vbd/V
Vdmax_T0.1
0 13 16
1.25 12 16
AL
2.5 7.4 15
4 6.6 14
5.5 6 12
TI
Self-protection
EN
ID
NF
CO
FOM
IC

SM
16.5 1.48 7.6 20000 0.13786 0.029 41.78 8.782
7.2.2.17. 9V PDEMOS (pde9g5_gs_hvbn_ckt)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Model name pde9g5_gs_hvbn_ckt
Terminal count 5
AL
SLDD PLH
DLDD PLH
TI
|Vgs|
|Vds|
-5
-9
+10%
+10%
EN
ID
3) Device symbol
NF
CO
IC
4) Layout
SM
5) Cross-section
3T
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
4T
EN
ID
NF
Parasitic Diode/BJT
CO
Diode D1 D2 D3 D4 B1
BV 25V 45V 54V 47V 51V
PWH to PDRF to
Space
NWH=1.6um NWH=0um
IC
6) Device Curve
SM

Pitch Vtgm Vtlin Vtsat Idlin Idsat IOFF BV Ron
Device name
(um) (V) (V) (V) (μA/μm) (μA/μm) (pA/μm) (V) (mΩ*mm2)
pde9g5_gs_hvbn_ckt 3T1.78/4T2.12 -0.82 -1.00 -0.60 -10 -250 -0.3 -17.6 18.0
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Ron-Vgs Curve
AL
TI
DC SOA curve
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
HCI SOA curve

NF
CO
IC
SM
Idlin
DC ≥ 0.2yr
Vg (V)
Vdmax_T0.1
0 12.1
1.25 15
2.5 13.2
4 13.6
5.5 12.6
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Self-protection
AL
TI
FOM
EN
ID
10 1.78 18.0 20000 0.24 0.07 120.00 35.20
NF
CO
IC
SM

Model name Pde12g5_gs_hvbn_ckt
Terminal count 5
SLDD PLH
DLDD PLH
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

|Vgs| -5 +10%
|Vds| -12 +10%
AL
3) Device symbol
TI
EN
ID
4) Layout
NF
CO
IC
SM
5) Cross-section
3T
4T
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Parasitic Diode
BV
Space
25V
PWH
45V
to PDRF to
EN
54V 47V 51V
NWH=1.6um NWH=0um
ID
6) Device Curve
NF

Device name
Pde12g5_gs_hvbn_ckt 3T1.88/4T2.22 -0.82 -1.02 -0.99 -9 -245 -0.3 -22.5 20
CO
Ron-Vgs Curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA curve
AL
TI
Idlin
EN
DC ≥ 0.2yr
ID
Vg (V) Vbd/V
Vdmax_T0.1
0 18 25
NF
1.25 22 30
2.5 18 27.5
4 15 22.5
CO
5.5 17.3 25
Self-protection
IC
SM
FOM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

9 1.88 20 20000 0.258 0.088 143.333 48.862
AL
TI
EN
ID
NF

Model name Pde16g5_gs_hvbn_ckt
CO
Terminal count 5
SLDD PLH
PLH
IC
DLDD

SM

|Vgs| -5 +10%
|Vds| -16 +10%
3) Device symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
3T
5) Cross-section EN
ID
NF
CO
4T
IC
SM
Parasitic Diode/BJT
BV 40V 45V 54V 47V 51V
PWH to PDRF to
Space
NWH=2um NWH=0um
6) Device Curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Device name
Pde16g5_gs_hvbn_ckt 3T2.33/4T2.67 -0.92 -1.03 -0.82 -7.0 -225 -0.3 -31.2 30
AL
Ron-Vgs Curve
TI
EN
ID
DC SOA curve
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
HCI SOA curve
NF
CO
IC
SM
Idlin
DC ≥ 0.2yr
Vg (V) Vbd/V
Vdmax_T0.1
0 27 42
1.25 26 41.5
2.5 26 42.5
4 27 40.5
5.5 25 39.5
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Self-protection
AL
TI
EN
ID
FOM
NF

7 2.33 30 20000 0.286 0.097 204.614 69.6
CO
IC
SM
Terminal count 5
SLDD PLH
DLDD PLH
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

|Vgs| -5 +10%
|Vds| -20 +10%
AL
3) Device symbol
TI
EN
ID
4) Layout
NF
CO
IC
SM
5) Cross-section
3T
4T
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Parasitic Diode/BJT
Diode
BV
D1
40V
D2
45V
EN D3
54V
D4
47V
B1
51V
Space PWH to NWH=2um PDRF to NWH=0um
ID
6) Device curve
NF

Device name
Pde20g5_gs_hvbn_ckt 3T2.53/4T2.87 -0.92 -0.87 -0.78 -6.7 -220 -0.3 -34.2 35
CO
Ron-Vgs Curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DC SOA curve
AL
TI
EN
ID
NF
CO
IC
TLP SOA curve

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HCI SOA curve
AL
TI
EN
ID
Idlin
DC ≥ 0.2yr
Vg (V)
Vdmax_T0.1
NF
0 27.6
1.25 24.8
2.5 26
CO
4 26
5.5 28
IC
Self-protection
SM
FOM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

6.7 2.53 35 20000 0.321 0.104 239.657 77.627
AL
TI
EN
ID
NF

Terminal count 5
CO

SLDD PLH
DLDD PLH
IC

SM
|Vgs| -5 +10%
|Vds| -24 +10%
3) Device symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
5) Cross-section
EN
3T
ID
NF
CO
4T
IC
SM
Parasitic Diode
BV 40V 45V 54V 47V 51V
Space PWH to NWH=2um PDRF to NWH=0um
6) Device curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Device name
Pde24g5_gs_hvbn_ckt 3T2.98/4T3.32 -0.92 -1.05 -0.78 -6 -210 -0.3 -40.4 45.6
Ron-Vgs Curve
AL
TI
EN
ID
DC SOA curve
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
HCI SOA curve

NF
CO
IC
SM
Idlin
DC ≥ 0.2yr
Vg (V)
Vdmax_T0.1
0 29
1.25 28.8
2.5 29.2
4 33.6
5.5 34
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Self-protection
AL
TI
EN
ID
FOM
NF

6 2.98 45.6 20000 0.396 0.137 329.867 114.467
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
Terminal count 5
TI
SLDD PLH
DLDD PLH EN
ID
|Vgs| -5 +10%
NF
|Vds| -30 +10%
3) Device symbol
CO
IC
SM
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Cross-section
3T
AL
TI
4T
EN
ID
NF
CO
Parasitic Diode/BJT
BV 40V 45V 54V 47V 51V
IC
PWH to PDRF to
Space
NWH=2um NWH=0um
SM
6) Device curve
Device name
Pde30g5_gs_hvbn_ckt 3T4.23/4T4.57 -0.92 -1.1 -0.81 -4.4 -185 -0.3 -45 89.6
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Ron-Vgs Curve
AL
TI
DC SOA curve
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
TLP SOA curve
AL
TI
EN
ID
HCI SOA curve

NF
CO
IC
SM
Idlin
DC ≥ 0.2yr
Vg (V) Vbd/V
Vdmax_T0.1
0 38 50
1.25 33 45
2.5 30 45
4 35 45
5.5 35 45
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Self-protection
AL
TI
EN
ID
FOM
NF

4.4 4.23 89.6 20000 0.472 0.154 536.364 175
CO
IC
SM
7.2.2.23. 35V PDEMOS (pde35g5_sti_hvbn_ckt)

This device HCI Idlin fail, not suggest use. Provide new structure pde35v in 2022/06.
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Model name pde35g5_sti_hvbn_ckt
Terminal count 5
AL
SLDD PLH
DLDD PLH
TI
|Vgs|
|Vds|
-5
-35
+10%
+10%
EN
ID
3) Layout
NF
CO
IC
SM
4) Cross section
3T
4T
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Parasitic Diode
Diode D1 D2 D3 D4
BV 54V >50V 54V 50V
Space PWH to NWH=5um
DDP
NWH=2um
to
EN
ID
5) Device curve
Device name
NF

3T3.045
Pde35g5_sti_hvbn_ckt -0.94 -1.06 -1.04 -3.8 -142 0.05 -46.8 85
/4T3.383
CO
Ron-Vgs Curve
IC
SM
7.2.2.24. 40V PDEMOS (pde40g5_sti_hvbn_ckt)

This device HCI Idlin fail, not suggest use. Provide new structure pde40v in 2022/06
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Model name Pde40g5_sti_hvbn_ckt
Terminal count 5
AL
SLDD PLH
DLDD PLH
TI
|Vgs|
|Vds|
-5
-40
+10%
+10%
EN
ID
3) Layout
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
4) Cross section
3T
AL
TI
4T
EN
ID
NF
CO
Parasitic Diode/BJT
Diode D1 D2 D3 D4
BV 54V >50V 54V 50V
IC
Space PWH to NWH=5um DDP to NWH=2um

SM
5) Device Curve
Device name
3T 3.145/
Pde40g5_sti_hvbn_ckt -0.91 -1 -0.97 -3.5 -176 0.05 -51 85.6
4T 3.485
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Ron-Vgs Curve
AL
TI
7.2.3. Bipolar Transistor characterization data summary
EN
Device HFE BVeco(V) BVebo(V) BVceo(V) BVcbo(V) Vbe(V) VA(V)
ID
pnp18a100_ckt 2.95 6.9 11 16 16 0.76 >500
pnp18a25_ckt 2.5 6.9 11 16 16 0.81 >500
NF
pnp18a4_ckt 2.5 6.9 11 16 16 0.8 >500

pnp50a100_poly_ckt 1.67 10.7 10.3 20 20 0.77 550
CO
pnp50a25_poly_ckt 1.62 10.4 10.1 19.3 19 0.85 480

npn50a100_sab_ckt 2.85 12.3 12.1 18 18 0.77 333
npn50a25_sab_ckt 3.1 12.5 12.2 18.4 18.4 0.82 333
IC
pnphva100_poly_ckt 34.5 11.9 14.8 20 19 0.76 20

pnphva25_poly_ckt 25 11.5 14.3 20 20 0.8 20
SM
npnhva100_poly_ckt 2.91 10.4 10 18 18 0.76 50

npnhva25_poly_ckt 3 10.2 10.1 18.2 18.1 0.83 50
pnphvbniso100_poly_ckt 25.2 12 15 43 38 0.8 5
pnphvbniso25_poly_ckt 25 13 14 41 39 0.8 5
npnhbeta100_poly_ckt 30 13 15 20 21 0.71 42
npnhbeta100_sab100_ckt 82 11 11.5 28 28 0.77 9
npnhbeta100_sab25_ckt 92 11 11.5 27.6 27.6 0.77 9
npnhbeta100_sab4_ckt 117.4 11 11.5 31 29.5 0.77 9
7.2.3.1. 1.8V vertical PNP (pnp18a100_ckt)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
1.8V vertical PNP (10X10)
Device description
(P+/PLL)_NW_PSUB
Model name pnp18a100_ckt
Terminal count 3
AL
Terminal definition E B C
Emitter LDD PLL
TI
2) Symbol
EN
ID
3) Layout
NF
CO
IC
4) Cross section
SM
Diode D1 D2 D3
BV 15V 10.5V 28.5V
Space PW to NW=0
5) WAT
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

pnp18a100_ckt 2.95 6.9 11 16 16 0.76 >500
AL
TI
EN
ID
NF
CO
6) Spice data Vs Si data

WAT Model
IC
area Ie(uA) -40C 25C 125C -40C 25C 125C

BETAPNP A67C1 PNP18 100 0.5 1.75 2.59 3.93 1.695 2.498 3.745
SM
BETAPNP A67C2 PNP18 100 1 1.75 2.59 3.93 1.696 2.5 3.748
BETAPNP A67C3 PNP18 100 2.5 1.72 2.56 3.86 1.696 2.5 3.747
VBE A67C PNP18 100 1 -0.8 -0.6 -0.4 -0.77 -0.64 -0.44
VBE A67C PNP18 100 0.5 -0.8 -0.6 -0.4 -0.75 -0.62 -0.42
VBE A67C PNP18 100 25 -0.8 -0.7 -0.6 -0.83 -0.72 -0.55
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
1.8V vertical PNP(5X5)
Device description
(P+/PLL)_NW_PSUB
TI
Terminal count 3
Emitter LDD PLL
2) Symbol
EN
ID
NF
3) Layout
CO
IC
SM
4) Cross section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Diode D1 D2 D3
BV
Space
15V
PW to NW=0
10.5V 28.5V EN
ID
5) WAT
NF
pnp18a25_ckt 2.5 6.9 11 16 16 0.81 >500

CO
IC
SM

WAT Model
area Ie(uA) -40C 25C 125C -40C 25C 125C
BETAPNP A67B1 PNP18 25 0.5 1.69 2.56 4 1.656 2.523 3.872
BETAPNP A67B2 PNP18 25 1 1.69 2.57 4 1.656 2.523 3.872
BETAPNP A67B3 PNP18 25 2.5 1.65 2.5 3.93 1.655 2.521 3.864
VBE A67B PNP18 25 1 -0.8 -0.7 -0.5 -0.79 -0.67 -0.48
VBE A67B PNP18 25 0.5 -0.8 -0.7 -0.5 -0.78 -0.65 -0.46
VBE A67B PNP18 25 25 -0.9 -0.8 -0.6 -0.86 -0.76 -0.59
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
1.8V vertical PNP (2X2)
Device description
NF
(P+/PLL)_NW_PSUB
Terminal count 3
CO
Emitter LDD PLL
2) Symbol
IC
SM
3) Layout
4) Cross section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Diode D1 D2 D3
BV 15V 10.5V 28.5V
Space PW to NW=0
EN
ID
5) WAT
NF
pnp18a4_ckt 2.5 6.9 11 16 16 0.8 >500

CO
IC
SM

WAT Model
area Ie(uA) -40 25 125 -40 25 125
BETAPNP A67A1 PNP18 4 0.5 1.69 2.67 4.35 1.677 2.637 4.138
BETAPNP A67A2 PNP18 4 1 1.69 2.67 4.35 1.675 2.634 4.133
BETAPNP A67A3 PNP18 4 2.5 1.63 2.61 4.25 1.672 2.627 4.112
VBE A67A PNP18 4 1 -0.82 -0.71 -0.54 -0.83 -0.72 -0.54
VBE A67A PNP18 4 0.5 -0.81 -0.7 -0.51 -0.81 -0.7 -0.51
VBE A67A PNP18 4 25 -0.89 -0.8 -0.65 -0.89 -0.8 -0.65
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
7.2.3.4. 5V vertical PNP (pnp50a100_poly_ckt)
EN
ID
NF
5V vertical PNP (10X10)

Device description
(P+/PLH)_NWH_PSUB
Model name pnp50a100_poly_ckt
CO
Terminal count 3
Emitter LDD PLH
IC
2) Symbol
SM
3) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
4) Cross Section
AL
TI
Diode D1 D2 D3
BV
Space
19V
PWH to NWH=0um
10.5V 55V
EN
5) WAT
ID
pnp50a100_poly_ckt 1.67 10.7 10.3 20 20 0.77 550
NF
CO
IC
SM
6) Mismatch
beta vbe diff
area 1/sqrt(area)
data model data model beta vbe
25e-12 0.2 3.44E-03 3.34E-03 8.59E-05 8.73E-05 -2.82% 1.64%
1.00E-10 0.1 2.68E-03 2.60E-03 6.47E-05 6.73E-05 -3.01% 3.92%
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.3.5. 5V vertical PNP (pnp50a25_poly_ckt)
AL
Device description 5V vertical PNP (5X5) (P+/PLH)_NWH_PSUB
Model name pnp50a25_poly_ckt
TI
Terminal count 3
Terminal definition EBC
Emitter LDD PLL
EN
2) Symbol
ID
NF
CO
3) Layout
IC
SM
4) Cross Section
Diode D1 D2 D3
BV 19V 10.5V 55V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) WAT
pnp50a25_poly_ckt 1.62 10.4 10.1 19.3 19 0.85 480
AL
TI
EN
6) Mismatch
ID
beta vbe diff
area 1/sqrt(area)
NF
25e-12 0.2 3.44E-03 3.34E-03 8.59E-05 8.73E-05 -2.82% 1.64%

1.00E-10 0.1 2.68E-03 2.60E-03 6.47E-05 6.73E-05 -3.01% 3.92%
CO
IC
SM
7.2.3.6. 5V vertical NPN (npn50a100_sab_ckt )
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5V vertical NPN (10X10)

Device description
(N+/NLH)_PWH_HVBN
Model name npn50a100_sab_ckt
AL
Terminal count 4
Terminal definition c b e psub
Emitter LDD NLH
TI
2) Symbol
EN
ID
3) Layout
NF
CO
IC
4) Cross Section
SM
Diode D1 D2 D3 D4 D5
BV 16V 11V 16V 40V 54V
Space PWH to NWH=0um PWH to NWH=0um
5) WAT
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
npn50a100_sab_ckt 2.85 12.3 12.1 18 18 0.77 333
AL
TI
EN
ID
NF
CO
6) Mismatch
beta vbe diff
area 1/sqrt(area)
IC
25e-12 0.2 4.50E-03 4.50E-03 2.21E-04 2.22E-04 0.01% 0.70%

1.00E-10 0.1 4.36E-03 4.35E-03 1.19E-04 1.19E-04 -0.20% -0.09%
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
7.2.3.7. 5V vertical NPN (npn50a25_sab_ckt )
NF
5V vertical NPN (5X5)

Device description
CO
(N+/NLH)_PWH_HVBN
Model name npn50a25_sab_ckt
Terminal count 4
IC
Emitter LDD NLH

SM
2) Symbol
3) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
4) Cross Section
AL
TI
BV
Space
16V
PWH to NWH=0um
11V 16V EN
PWH to NWH=0um
40V 54V
ID
5) WAT
NF
npn50a25_sab_ckt 3.1 12.5 12.2 18.4 18.4 0.82 333

CO
IC
SM
6) Mismatch
beta vbe diff
area 1/sqrt(area)
25e-12 0.2 4.50E-03 4.50E-03 2.21E-04 2.22E-04 0.01% 0.70%
1.00E-10 0.1 4.36E-03 4.35E-03 1.19E-04 1.19E-04 -0.20% -0.09%
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
7) Spice data Vs Si data EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.3.8. HV lateral PNP (pnphva100_poly_ckt )
AL
Device description HV lateral PNP (10x10) P+_NDRF_PWH
Model name pnphva100_poly_ckt
Terminal count 3
TI
Terminal definition cbe
LDD NA
EN
2) Symbol
ID
NF
CO
3) Layout
IC
SM
4) Cross Section
Diode D1 D2 D3
BV 18V 16V 40V
Space PWH to NDRF=0um
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) WAT
Pnphva100_poly_ckt 34.5 11.9 14.8 20 19 0.76 20
AL
TI
EN
ID
NF
CO
6) Mismatch
IC
beta vbe
area 1/sqrt(area)
data model data model
25e-12 0.2 7.01E-03 7.00E-03 1.15E-04 1.95E-04
SM
pnphva_poly
1.00E-10 0.1 7.11E-03 7.10E-03 5.23E-05 1.87E-04
7.2.3.9. HV lateral PNP (pnphva25_poly_ckt )
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Device description HV lateral PNP (5x5) P+_NDRF_PWH

Model name pnphva25_poly_ckt
Terminal count 3
AL
Terminal definition cbe
LDD NA
TI
2) Symbol
EN
ID
3) Layout
NF
CO
IC
4) Cross Section
SM
Diode D1 D2 D3
BV 18V 16V 40V
Space PWH to NDRF=0um
5) WAT
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Pnphva25_poly_ckt 25 11.5 14.3 20 20 0.8 20
AL
TI
EN
ID
NF
CO
6) Mismatch
beta vbe
IC
area 1/sqrt(area)
25e-12 0.2 7.01E-03 7.00E-03 1.15E-04 1.95E-04
SM
pnphva_poly
1.00E-10 0.1 7.11E-03 7.10E-03 5.23E-05 1.87E-04
7.2.3.10. HV vertical NPN (npnhva100_poly_ckt )
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
HV vertical NPN (10x10)

Device description
N+_PWH_HVBN)
Model name npnhva100_poly_ckt
AL
Terminal count 4
LDD NA
TI
2) Symbol
EN
ID
3) Layout
NF
CO
IC
SM
4) Cross Section
BV 16V 40V 11V 54V 40V
5) WAT
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
npnhva100_poly_ckt 2.91 10.4 10 18 18 0.76 50
AL
TI
EN
ID
NF
CO
IC
SM
6) Mismatch
beta vbe
area 1/sqrt(area)
25e-12 0.2 7.18E-03 7.18E-03 2.91E-04 2.98E-04
npnhva_poly
1.00E-10 0.1 3.62E-03 3.61E-03 8.23E-05 9.45E-05
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
7.2.3.11. HV vertical NPN (npnhva25_poly_ckt )
Device description HV NPN (5x5) (N+_PWH_HVBN)

Model name npnhva25_poly_ckt
Terminal count 4
LDD NA
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
3) Layout
TI
EN
ID
NF
4) Cross Section
CO
IC
SM
BV 16V 40V 11V 54V 40V

5) WAT
npnhva25_poly_ckt 3 10.2 10.1 18.2 18.1 0.83 50
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
6) Mismatch
area 1/sqrt(area)
beta
data
EN
model
vbe
data model
ID
25e-12 0.2 7.18E-03 7.18E-03 2.91E-04 2.98E-04
npnhva_poly
1.00E-10 0.1 3.62E-03 3.61E-03 8.23E-05 9.45E-05
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
7.2.3.12. EN
HVBN ISO lateral PNP (pnphvbniso100_poly_ckt )
ID
Device description HVBN ISO PNP (10*10) (P+_NDRF_PWH)
Model name pnphvbniso100_poly_ckt
NF
Terminal count 5
Terminal definition c b e hvbn psub
LDD NA
CO
2) Symbol
IC
SM
3) Layout
4) Cross Section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
Diode D1 D2 D3 D4 D5 D6 D7
TI
BV 40V 20V 40V 15V 40V 54V 40V
PWH to
NDRF=0.1um
EN
5) WAT
ID
pnphvbniso100_poly_ckt 25.2 12 15 43 38 0.8 5
NF
CO
IC
SM
6) Mismatch
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
beta vbe
area 1/sqrt(area)
25e-12 0.2 7.01E-03 7.00E-03 1.15E-04 1.95E-04
Pnphvbniso100_poly
1.00E-10 0.1 7.11E-03 7.10E-03 5.23E-05 1.87E-04
AL
TI
EN
ID
NF
7.2.3.13. HVBN ISO lateral PNP (pnphvbniso25_poly_ckt )
CO
Device description HVBN ISO PNP (5X5) (P+_NDRF_PWH)

Model name pnphvbniso25_poly_ckt
Terminal count 5
IC
Terminal definition c b e hvbn psub

LDD NA
SM
2) Symbol
3) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
4) Cross Section
EN
ID
NF
Diode D1 D2 D3 D4 D5 D6 D7
CO
BV 40V 20V 40V 15V 40V 54V 40V

PWH to
NDRF=0.1um
IC
5) WAT
SM
Pnphvbniso25_poly_ckt 25 13 14 41 39 0.8 5
6) Mismatch
beta vbe
area 1/sqrt(area)
25e-12 0.2 7.01E-03 7.00E-03 1.15E-04 1.95E-04
Pnphvbniso100_poly
1.00E-10 0.1 7.11E-03 7.10E-03 5.23E-05 1.87E-04
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
7.2.3.14. EN
High Beta vertical NPN (npnhbeta100_poly_ckt)
ID
Device description High Beta NPN (10X10) (N+_PDRF_HVBN)
Model name npnhbeta100_poly_ckt
NF
Terminal count 4
LDD NA
CO
2) Symbol
IC
SM
3) Layout
4) Cross Section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
Diode D1 D2 D3 D4
BV 47V 40V 21V 54V
Space PDRF to NWH=1um
5) WAT
PWH to NWH=2um EN
ID
npnhbeta100_poly_ckt 30 13 15 20 21 0.71 42
NF
CO
IC
SM
6) Mismatch
Silicon Model Ratio
Beta_mis 0.00552 0.0055 -0.37%
Vbe_mis 9.00E-05 9.022E-05 0.24%
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.3.15. High Beta NPN (npnhbeta100_sab100_ckt)
Device description High Beta NPN
AL
Model name npnhbeta100_sab100_ckt
Terminal count 4
TI
LDD NA
2) Symbol EN
ID
NF
3) Layout
CO
IC
SM
4) Cross Section
BV ~47V 40V 11.5V 28V 54V
Space PC to NWH=1um PWH to NWH=2um
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) WAT
npnhbeta100_sab100_ckt 82 11 11.5 28 28 0.77 9
(Q5T0, HL5180.A07)
AL
TI
EN
ID
NF
CO
IC
6) Mismatch
beta vbe diff
SM
Device area 1/sqrt(area)

1 0.5 1.40E-02 1.41E-02 1.13E-04 1.12E-04 -0.19% 5.64E-04
npnhbeta100_sab 1 0.2 1.02E-02 1.02E-02 6.49E-05 6.53E-05 0.33% -3.77E-04
1 0.1 4.11E-03 4.10E-03 4.82E-05 4.88E-05 0.32% -6.01E-04
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF

CO

IC
Terminal count 4
SM
LDD NA
2) Symbol
3) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
4) Cross Section
EN
ID
NF
CO
BV ~47V 40V 11.5V 28V 54V

5) WAT
IC

npnhbeta100_sab25_ckt 92 11 11.5 27.6 27.6 0.77 9
SM
(Q5T0, HL5180.A07)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
6) Mismatch
EN
beta vbe diff
Device area 1/sqrt(area)
ID
1 0.5 1.40E-02 1.41E-02 1.13E-04 1.12E-04 -0.19% 5.64E-04
NF

1 0.1 4.11E-03 4.10E-03 4.82E-05 4.88E-05 0.32% -6.01E-04
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID

NF

Terminal count 4
CO
LDD NA
2) Symbol
IC
SM
3) Layout
4) Cross Section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
BV ~47V 40V 11.5V 28V 54V
5) WAT
EN
ID
npnhbeta100_sab4_ckt 117.4 11 11.5 31 29.5 0.77 9
(Q5T0, HL5180.A07)
NF
CO
IC
SM
6) Mismatch
Device area 1/sqrt(area) beta vbe diff
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

1 0.5 1.40E-02 1.41E-02 1.13E-04 1.12E-04 -0.19% 5.64E-04
1 0.1 4.11E-03 4.10E-03 4.82E-05 4.88E-05 0.32% -6.01E-04
AL
TI
EN
ID
NF

CO
IC
SM
7.2.4. Diode characterization data summary
7.2.4.1. 1.8V N+/Pwell diode (ndio18)
Device description 1.8V N+/P-well diode
Model name ndio18
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Terminal count 2
Terminal definition pw nd
LDD NLL
2) Symbol
AL
TI
3) Layout
EN
ID
NF
CO
IC
4) Cross section
SM
Diode BV
D1 ~11V
5) Spice data Vs Si data:
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Parameters Unit TT FF SS
djs_ndio18 A/m^2 0 1.06E-07 -1.06E-07
djsw_ndio18 --- 0 5.00E-16 -5.00E-16
dn_ndio18 A/m 0 -1.02E-02 1.02E-02
AL
dcj_ndio18 F/ m^2 0 -4.84E-05 4.84E-05
dcjsw_ndio18 F/m 0 -3.98E-12 3.98E-12
TI
6) ESD characterization
ESD performance（Forward) 2KV HBM
1.8V diode Perimeter
D1 1.8V N+/PW diode 100

EN
Von (V)
0.7
It2(A)
1.905
Spec
Pass
D2 1.8V N+/PW diode 200 0.7 2.822 Pass
ID
NF
CO
IC
SM
7) CV/IV curve
ndio18 area=1.80E-08 m2, pj=0.00072 m CV/IV curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
7.2.4.2. 1.8V P+/N-well diode (pdio18)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Device description 1.8V P+/N-well diode
Model name pdio18
Terminal count 2
Terminal definition pd nw
AL
LDD PLL
2) Symbol
TI
EN
ID
3) Layout
NF
CO
IC
SM
4) Cross section
Diode BV
D1 ~11V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Model name pdio18
Terminal count 2
AL
LDD PLL
2) Symbol
TI
EN
ID
3) Layout
NF
CO
IC
SM
4) Cross section
Diode BV
D1 ~11V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

Model name pdio18
Terminal count 2
LDD PLL
AL
2) Symbol
TI
EN
ID
3) Layout
NF
CO
IC
4) Cross section
SM
Diode BV
D1 ~11V

djs_pdio18 A/m^2 0 4.98E-08 -4.98E-08
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
djsw_pdio18 --- 0 5.00E-16 -5.00E-16

dn_pdio18 A/m 0 -1.01E-02 1.01E-02
dcj_pdio18 F/ m^2 0 -5.35E-05 5.35E-05
dcjsw_pdio18 F/m 0 -4.95E-12 4.95E-12
AL
ESD performance（Forward) 2KV
TI
1.8V diode Perimeter HBM
Von (V) It2(A) Spec
D11 1.8V P+/NW diode 100 0.7 3.008 Pass
D12
D13
1.8V P+/NW diode
1.8V P+/NW diode
200
400
EN 0.7
0.7
3.303
4.286
Pass
Pass
D14 1.8V P+/NW diode 800 0.7 5.64 Pass
ID
NF
CO
IC
SM
7) CV/IV curve
pdio18 area=1.80E-08 m2, pj=0.00072 m CV/IV curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
7.2.4.5. 1.8V N-well/Psub diode (nwdio18)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Device description 1.8V N-well to Psub

Model name nwdio18
Terminal count 2
Terminal definition pw nw
LDD NA
AL
2) Symbol
TI
EN
ID
3) Layout
NF
CO
IC
4) Cross section
SM
Diode BV
D1 15V

djs_nwdio A/m^2 0 4.26E-07 -4.26E-07
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
djsw_nwdio --- 0 5.00E-16 -5.00E-16

dn_nwdio A/m 0 -1.01E-02 1.01E-02
dcj_nwdio F/ m^2 0 -7.25E-06 7.25E-06
dcjsw_nwdio F/m 0 -2.50E-11 2.50E-11
AL
6) CV curve
TI
EN
ID
NF
CO
IC
SM
7.2.4.6. 5V N+/Pwell diode (ndio50)
Device description 5V N+/Pwell Diode
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Model name ndio50

Terminal count 2
Terminal definition pw, nd
LDD NLH
AL
2) Symbol
TI
EN
3) Layout
ID
NF
CO
IC
4) Cross Section
SM
Diode BV
D1 ~11.5V
5V diode Perimeter HBM
Von (V) It2(A) Spec
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
D21 5V N+/PW diode 100 0.7 1.829 Pass

D22 5V N+/PW diode 200 0.7 2.786 Pass
D23 5V N+/PW diode 400 0.7 3.206 Pass
D24 5V N+/PW diode 800 0.7 4.468 Pass
AL
TI
EN
ID
NF
6) CV/IV curve
CO
ndio50 area=1.80E-08 m2, pj=0.00072 m CV/IV curve

IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
7.2.4.7. 5V P+/Nwell Diode (pdio50)
Device description 5V P+/Nwell Diode
Model name pdio50
Terminal count 2
Terminal definition pd,nw
LDD PLL
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
3) Layout
TI
EN
ID
NF
4) Cross Section
CO
IC
SM
Diode BV
D1 ~10.5V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

5V diode Perimeter HBM
Von (V) It2(A) Spec
D31 5V P+/NW diode 100 0.7 2.799 Pass
D32 5V P+/NW diode 200 0.7 3.355 Pass
AL
D33 5V P+/NW diode 400 0.7 4.266 Pass
D34 5V P+/NW diode 800 0.7 5.564 Pass
TI
EN
ID
NF
CO
6) CV/IV Curve
pdio50 area=1.80E-08 m2, pj=0.00072 m CV/IV curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
7.2.4.8. 5V Nwell/Psub Diode (nwdio50)

IC
SM
Device description 5V Nwell/Psub Diode

Model name nwdio50
Terminal count 2
Terminal definition pw, nw
LDD NA
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
3) Layout
AL
TI
EN
4) Cross Section
ID
NF
CO
IC
Diode BV Space
D1 16V PWH to NWH=0
SM
7.2.4.9. 5V Pwell/HVBN Diode (pwhvbndio50)
Device description 5V Pwell/HVBN Diode
Model name pwhvbndio50
Terminal count 2
Terminal definition pw, hvbn
LDD NA
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
3) Layout
TI
EN
ID
4) Cross Section
NF
CO
IC
SM
Diode D1 D2 D3 D4
BV 16V 16V 40V 54V
Space PWH to NWH=0 PWH to NWH=0
7.2.4.10. HV Pwell/HVBN Diode (pwhvbndiohv)
Device description HV Pwell/HVBN Diode
Model name pwhvbndio50
Terminal count 2
LDD NA
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
3) Layout
TI
EN
ID
NF
4) Cross Section
CO
IC
SM
Diode D1 D2 D3 D4
BV 40V 54V 40V 54V
7.2.4.11. 5V HVBN/Psub Diode (hvbnpsubdio50)
Device description 5V HVBN/Psub Diode
Model name hvbnpsubdio50
Terminal count 2
LDD NA
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
3) Layout
TI
EN
ID
NF
4) Cross Section
CO
IC
SM
Diode BV Space
D1 16V PWH to NWH=0
D2 54V
7.2.4.12. HVBN/Psub Diode (hvbnpsubdio)
Device description HVBN/Psub Diode
Model name hvbnpsubdio
Terminal count 2
LDD NA
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
3) Layout
TI
EN
ID
4) Cross Section
NF
CO
IC
SM
Diode BV Space
D1 54V PWH to NWH=5um
D2 54V
7.2.4.13. Zener Diode (5.5V)
1) Description
Device description N+/Pbody Zener Diode
Model name zddio
Terminal count 4
Terminal definition p n hvbn psub
LDD NLH
2) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
3) Layout
EN
ID
NF
4) Cross Section
CO
IC
SM
BV 40V 40V 5.5V 40V 54V
1) When positive P+(Anode) and NBL(NWH) short (suggest)

2) When negative(clamp) N+(Cathode) and NBL (NWH) short(suggest)
5) Reverse BV Curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
7.2.4.14. Schottky Diode (30V)
EN
ID
1) Description
Device description 30v Schottky Diode
NF
Model name sdmte30_hvbn_ckt

Terminal count 3
Terminal definition anode cathode psub
LDD NA
CO
2) Symbol
IC
SM
3) Layout
4) Cross Section
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
Diode D1 D2 D3
TI
BV 40V 40V 54V
Space PWH to NWH=2um PWH to NDRF=0um
5) Device curve
EN
ID
Junction area [email protected]
BV(v) [email protected](A)
100um2 (A)
-40C 41.0 6.65E-13 3.5E-04
NF
25C 44.2 3.20E-10 4.1E-04

175C 49.0 1.90E-06 1.7E-03
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
7.2.5. ESD PNP characterization data summary

CO
ESD design window ESD 2KV HBM ESD 4KV HBM ESD 8KV HBM
Device
IC
Area Area Area

Vop+1.5V BV-1.5V Vtri (V) It2(A) It2(A) It2(A)
(um2) (um2) (um2)
9V 10.5 18 14.2 2.3 59*110 3.5 77*110 6.5 124*110
SM
12V 13.5 19 15.0 2.4 81*110 3.5 101*110 6.5 149*110

16V 17.5 26 20.5 2.4 58*110 3.5 77*110 6.7 132*110
20V 21.5 34 25.0 2.5 53*110 3.5 79*110 6.6 151*110
24V 25.5 36 29.0 2.6 66*110 3.6 105*110 6.6 223*110
30V 31.5 40 36.2 2.5 145*110 3.6 195*110 6.6 344*110
35V 36.5 52 42.0 2.4 90*110 3.6 124*110 6.5 209*110
40V 41.5 55 48.0 2.4 162*110 3.6 271*110 6.5 533*110
1. SMIC provides ESD device for 0.18BCD V3E high voltage 6V~40V application for 2KV/4KV/8KV
HBM target.
2. ESD design window is defined based on normal operation and device breakdown voltage, customer
need consult SMIC if chip operates at overdrive or any special operation condition.
nd nd
3. ESD parameter: trigger voltage (Vt1); holding voltage (Vh); 2 breakdown voltage (Vt2); 2
breakdown current (It2).
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
4. It2 level and HBM ESD correlation: HBM voltage (KV)~It2 (A)*1.5Kohm.
ESD protection window : (Operating Voltage+⧍, Breakdown Voltage -⧍) ⧍: 1.5V
AL
TI
EN
ID
NF
7.2.5.1. 9V ESD Protection

CO
1) 9V ESD Device cross section

(-) (+)
IC
PGR b c e c b PGR
SP SN SP SP SP SN SP
SM
PBODY PBODY
WP WN WP
P-sub
(-) (+)
PGR b c e c b PGR
PBODY PBODY
WP WN WP
P-sub
2) 9V ESD Device IV CV curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
3) 9V ESD Device parameter
NF
25C25C/125C 125C
9V ID Capcitor
Vtri(V) Finger Y(um) BV(v) Ioff(pA) BV(v) Ioff(nA)
PNP @18V (1.1VOP)pF
CO
9V02 14.2 9 100 1.7 14.8 14.4 15.9 3.0 1.47

9V05 14.2 12 100 2.2 14.2 7.65 15.8 3.3 1.76
9V08 14.2 24 100 4.5 14.1 12.9 15.6 5.0 2.95
IC
4) 9V ESD Device TLP result

SM
Estimated size (*KV ESD_HBM: 1500Ω *IT2)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
9V PNP Vtri(V) Total W (um) Finger Cell size (um2) Wf (um) IT2(A) @ 18V
2KV 14.2 2160 12 59*110 90 2.3
4KV 14.2 3240 18 77*110 90 3.5
8KV 14.2 5940 33 124*110 90 6.5
AL
Notice：
1. 2K, 4KV, 8KV size is calculated base on test data
TI
2. Process: SMIC 0.18BCD V3E platform
3. 9V ESD protection: using PNP for HV 9V ESD protection
4. Cell size include Psub ring
EN
ID
NF
(-) (+)
CO
PGR b c e c b PGR
PBODY PBODY
WP WN WN WN WP
IC
HVBN
P-sub
SM
(-) (+)
PGR b c e c b PGR
PBODY PBODY
WP WN WN WN WP
HVBN
P-sub
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
25C 125C 25C/125C

Capcitor
12V Finge Y(um ID @ Ioff(pA
Vtri(V) BV(v) BV(v) Ioff(nA) (1.1VOP)p
PNP r ) 19V )
CO
F
Z3_DC1 15 24 100 4.6 14.1 18.8 15.4 16.9 3.4
Z3_AC1 15 48 100 10 14.1 34.7 15.3 29.6 5.8
Z3_BC1 15 96 100 20 14.1 66.5 15.2 55.8 10.7
IC

SM
Estimated size (*KV ESD_HBM: 1500Ω *It2)
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
12V PNP Vtri(V) Total W(um) Finger Cell size (um2) Wf (um) It2(A) @19V
2KV 15 2700 15 81*110 90 2.4
4KV 15 3600 20 101*110 90 3.5
8KV 15 5760 32 149*110 90 6.5
AL
Notice：
TI
EN
ID
NF
(-) (+)
CO
PGR b c SAB e SAB c b PGR

PDRF
PDRF
IC
WP WN WP WN WP WN WP
HVBN
SM
P-sub
(-) (+)

PDRF
PDRF
HVBN
P-sub
2) 16V ESD IV CV curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
25C 125C 25C/125C
NF
ID
Capcitor
16V PNP Vtri(V) Finger Y(um) @ BV(v) Ioff(pA) BV(v) Ioff(nA)
(1.1VOP)pF
26V
CO
12NA16b 20.5 16 100 4.44 20.1 13.6 20.8 5.64 3.08

12NA17b 20.5 20 100 5.41 20.1 16.4 20.7 6.63 3.67
12NA18b 20.5 24 100 6.77 20.1 18.4 20.8 7.32 4.22
IC

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
16V PNP Vtri(V) Total W(um) Finger Cell size (um2) Wf (um) It2(A) @26V
2KV 20.5 1440 8 58*110 90 2.4
4KV 20.5 2160 12 77*110 90 3.5
8KV 20.5 4320 24 132*110 90 6.7
AL
Notice：
TI

EN
ID
NF
(-) (+)
CO

PDRF
PDRF
IC
HVBN
P-sub
SM
(-) (+)

PDRF
PDRF
HVBN
P-sub
2) 20V ESD IV CV curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
25C 125C
25C/125C
NF
20V ID @ Capcitor
Vtri(V) Finger Wf(um) BV(v) Ioff(pA) BV(v) Ioff(nA)
PNP 19V (1.1VOP)pF
12NA26a 25 16 90 4.2 25.1 25.5 26.0 6.5 2.92
CO
12NA27a 25 20 90 5.31 25.1 32.1 26.1 7.7 3.43

12NA28a 25 24 90 6.37 25.1 40.0 26.2 9.2 3.98
IC

SM

20V PNP Vtri(V) Total W(um) Finger Cell size (um2) Wf(um) It2(A)@34V
2KV 25 1080 6 53*110 90 2.5
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
4KV 25 1980 11 79*110 90 3.5

8KV 25 4500 25 151*110 90 6.6
Notice：
AL
Cell size include Psub ring
TI
1) 24V ESD Device cross section EN

ID
(-) (+)
NF

PDRF
PDRF
CO
HVBN
P-sub
IC
(-) (+)
SM

PDRF
PDRF
HVBN
P-sub
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
25C 125C 25C/125C

NF
ID
24V Capcitor
Vtri(V) Finger Y(um) @ BV(v) Ioff(pA) BV(v) Ioff(nA)
PNP (1.1VOP)pF
36V
CO
NA31a 29 16 100 3.66 29.0 10.8 30.4 8.4 2.82

NA32a 29 20 100 4.26 28.9 13.0 30.4 9.9 3.33
NA33a 29 24 100 4.65 28.9 15.5 30.3 11.2 3.85
IC

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
24V PNP Vtri(V) Total W(um) Finger Cell size(um2) Wf (um) It2(A)@36V
2KV 29 1440 8 66*110 90 2.6
4KV 29 2700 15 105*110 90 3.6
8KV 29 6480 36 223*110 90 6.6
AL
Notice：
TI

EN
ID
NF
(-) (+)
CO

PDRF
PDRF
IC
HVBN
P-sub
SM
(-) (+)

PDRF
PDRF
HVBN
P-sub
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
Tested data: (TLP 10ns rise time/100ns pulse width)
NF
25C 25C/125C 125C

30V ID @ Capcitor
Vtr(V) Finger Y(um) BV(v) Ioff(pA) BV(v) Ioff(nA)
CO
PNP 40V (1.1VOP)pF

NA66 35.7 16 100 1.95 34.7 540.0 37.0 40.1 2.75
NA67 35.7 20 100 2.15 34.5 540.0 37.3 45.4 3.27
NA68 35.7 24 100 2.63 34.7 765.0 37.0 48.1 3.78
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
2KV 35.7 3600 20 145*110 90 2.5
4KV 35.7 5040 28 195*110 90 3.6
8KV 35.7 9360 52 344*110 90 6.6
AL
Notice：
TI

EN
ID
(-) (+)
NF
PGR b c e c b PGR
CO
P-sub
IC
(-) (+)
SM
PGR b c e c b PGR
P-sub
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
25C 125C 25C/125C

ID
35V Capcitor
Vtr(V) Finger Y(um) @ BV(v) Ioff(pA) BV(v) Ioff(nA)
PNP (1.1VOP)pF
52V
AL
35B01 42 25 130 6.51 41.6 37.6 45.5 18.2 3.47
35B02 42 30 130 7.6 41.5 45.1 45.3 20.5 4.02
35B03 42 35 130 9.4 41.5 51.5 45.4 22.8 4.57
TI
EN
ID
NF
CO
IC

SM
2KV 42 2160 12 90*110 90 2.4

4KV 42 3240 18 124*110 90 3.6
8KV 42 5940 33 209*110 90 6.5
Notice：
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
(-) (+)
PGR b c e c b PGR
AL
TI
P-sub
(-) (+)
PGR
b c e c b PGR
EN
ID
NF
P-sub
CO
IC

SM
25C 125C 25C/125C

ID
40V Capcitor
Vtri(V) Finger Y(um) @ BV(v) Ioff(pA) BV(v) Ioff(nA)
PNP (1.1VOP)pF
55V
40A01 48 17 100 1.75 50.2 36.3 54.2 17.1 3.45
40A02 48 18 100 2.04 50.2 41.4 54.1 19.0 3.98
40A03 48 19 100 2.26 50.1 41.6 54.0 20.0 4.53
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
2KV 48 3960 22 162*110 90 2.4
4KV 48 7020 39 271*110 90 3.6
NF
8KV 48 14400 80 533*110 90 6.5

Notice：
CO

5. Suggest 40V PNP 8KV with two block stack: 210*110*2
IC
6. 40V ESD_PNP High Current Array Size Advice
• For large current STI_PNP ESD, the multi-finger structure can remarkbly improve the capacity of
SM
discharging comparing to the long single-finger structure.

• The Vtri will degrade when the W of single finger is too large.
Cellname FingerW FingerNo Total W ArrY Remark VOP HVBN

20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
40A07 120 90 10800 1 new BSL LDBK40 None

AL
TI
EN
ID
NF
CO
7.2.6. ESD MOS characterization data summary

IC
7.2.6.1. 1.8V N GGMOS (n1d8_esd_ckt)

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Total SABOVG
Wf(um) Length(um) Finger SCP(um) DCP(um) SAB GT_Pin Vt1 Vh leak@Vop It2
Width(W) (um)
240 30 0.18 8 0.75 2.22 Y 0.06 Ground 5.806 4.086 1.16E-09 >2.421
360 30 0.18 12 0.75 2.22 Y 0.06 Ground 5.788 3.865 1.75E-09 >3.36
480 30 0.18 16 0.75 2.22 Y 0.06 Ground 5.768 3.898 2.29E-09 >4.375
AL
600 30 0.18 20 0.75 2.22 Y 0.06 Ground 5.738 3.888 2.95E-09 >5.398
TI
EN
ID
NF
Total ESD It2(A) 2KV HBM

CO
Wf Length SCP DCP SABOVG

Device Width Finger SAB Spec
(um) (um) (um) (um) (um) Forward
(um) Reverse (It2:1.33A)
Diode
1.8V GGMOS 360 30 0.18 12 0.75 2.22 Y 0.06 >3.36 >3.42 Pass
1.8V GDPMOS 360 30 0.18 12 0.75 2.22 Y 0.06 2.203 >3.30 Pass
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
DCP It2 Vh
0.65 2.29 3.87
0.82 2.91 3.72
1.22 3.03 3.74
AL
1.82 3.27 3.84
2.22 3.33 3.84
TI
7.2.6.2. 1.8V P GDMOS (p1d8_esd_ckt)
EN
ID
NF
CO
IC
Total Length SCP DCP SABOVG

Wf(um) Finger SAB GT_Pin Vt1 Vh leak@Vop It2
Width(W) (um) (um) (um) (um)
SM
240 30 0.18 8 0.75 2.22 Y 0.06 Ground 6.223 5.553 1.68E-09 1.398
360 30 0.18 12 0.75 2.22 Y 0.06 Ground 6.395 5.448 2.75E-09 2.203
480 30 0.18 16 0.75 2.22 Y 0.06 Ground 6.326 5.39 3.08E-09 2.819
600 30 0.18 20 0.75 2.22 Y 0.06 Ground 6.276 5.369 4.20E-09 3.517
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
Device Width Finger SAB Spec
(um) (um) (um) (um) (um) Forward
(um) Reverse (It2:1.33A)
NF
Diode
1.8V GGMOS 360 30 0.18 12 0.75 2.22 Y 0.06 >3.36 >3.42 Pass
1.8V GDPMOS 360 30 0.18 12 0.75 2.22 Y 0.06 2.203 >3.30 Pass
CO
7.2.6.3. 1.8V ESD N+/Pwell Diode (ndio1d8_esd)

IC
SM
2KV HBM
ESD performance（Forward)
1.8V diode Perimeter Spec
Von (V) It2(A)
D1 1.8V N+/PW diode 100 0.7 1.905 Pass
D2 1.8V N+/PW diode 200 0.7 2.822 Pass
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.6.4. 1.8V ESD P+/Nwell Diode (pdio1d8_esd)
AL
TI
EN
ID
ESD performance
2KV HBM Spec
1.8V diode Perimeter （Forward)
Von (V) It2(A)
NF
D11 1.8V P+/NW diode 100 0.7 3.008 Pass

D12 1.8V P+/NW diode 200 0.7 3.303 Pass
D13 1.8V P+/NW diode 400 0.7 4.286 Pass
CO
D14 1.8V P+/NW diode 800 0.7 5.64 Pass
7.2.6.5. 5V N GGMOS (n5_esd_ckt)

IC
SM
Total Wf Length Finger SCP DCP SAB SABOVG GT_Pin Vt1 Vh leak@Vop It2
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Width(W) (um) (um) (um) (um) (um)

240 30 0.5 8 0.75 2.22 Y 0.06 Ground 10.713 6.557 5.00E-11 2.24
360 30 0.5 12 0.75 2.22 Y 0.06 Ground 10.679 6.522 5.00E-11 3.002
480 30 0.5 16 0.75 2.22 Y 0.06 Ground 10.684 6.616 5.00E-11 3.774
AL
600 30 0.5 20 0.75 2.22 Y 0.06 Ground 10.684 6.286 5.00E-11 4.822
TI
EN
ID
NF
CO
2KV HBM
Total ESD It2(A) Spec
Device Width Finger SAB (It2:1.33A)
(um) (um) (um) (um) (um)
(um) Forward
Reverse
Diode
IC
GGMOS 360 30 0.5 12 0.75 2.22 Y 0.06 3.002 >3.45 Pass

5V
GDPMOS 360 30 0.45 12 0.75 2.22 Y 0.06 1.211 >3.40 Pass
SM
DCP It2 Vh
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
0.82 6.31 1.93

1.22 6.43 2.58
1.82 6.42 2.78
2.22 8.82 2.97
AL
7.2.6.6. 5V N GRMOS
MOS No. Split Name W total L R Vtri(V) Vhold(V) It2(A)
TI
M29 GR NMOS 5VNMOS_string_R50K 480 0.6 50K 7.75 5.80 3.78
M45 GR NMOS 5VNMOS_string_R100K 480 0.6 100K 7.60 6.00 3.80
M61
M77
GR NMOS
GR NMOS
5VNMOS_string_R200K
5VNMOS_string_R400K
480
480
EN 0.6 200K
0.6 400K
7.00
6.60
5.80
5.80
3.78
3.90
ID
The external resistance combined with GRMOS refer to the table above. When choosing HRP resistance,
satisfy the resistance width exceed the gate length.
NF
7.2.6.7. 5V P GDMOS (p5_esd_ckt)

CO
IC
SM
Total Length SCP DCP SABOVG

Wf(um) Finger SAB GT_Pin Vt1 Vh leak@Vop It2
Width(W) (um) (um) (um) (um)
240 30 0.45 8 0.75 2.22 Y 0.06 Ground 9.96 9.18 5.00E-11 0.9
360 30 0.45 12 0.75 2.22 Y 0.06 Ground 9.9 9.17 5.00E-11 1.211
480 30 0.45 16 0.75 2.22 Y 0.06 Ground 10.24 9.04 5.00E-11 1.723
600 30 0.45 20 0.75 2.22 Y 0.06 Ground 9.91 9.38 5.00E-11 2.229
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
Device Width Finger SAB Forward Spec
(um) (um) (um) (um) (um) Reverse
(um) Diode (It2:1.33A)
GGMOS 360 30 0.5 12 0.75 2.22 Y 0.06 3.002 >3.45 Pass
NF
5V
GDPMOS 360 30 0.45 12 0.75 2.22 Y 0.06 1.211 >3.40 Pass
7.2.6.8. 5V ESD N+/Pwell Diode (ndio5_esd)

CO
IC
SM
ESD performance（Forward) 2KV HBM Spec

5V diode Perimeter
Von (V) It2(A)
D21 5V N+/PW diode 100 0.7 1.829 Pass
D22 5V N+/PW diode 200 0.7 2.786 Pass
D23 5V N+/PW diode 400 0.7 3.206 Pass
D24 5V N+/PW diode 800 0.7 4.468 Pass
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.6.9. 5V ESD P+/Nwell Diode (pdio5_esd)
AL
TI
EN
ESD performance（Forward) 2KV HBM Spec
ID
5V diode Perimeter
Von (V) It2(A)
D31 5V P+/NW diode 100 0.7 2.799 Pass
NF
D32 5V P+/NW diode 200 0.7 3.355 Pass

D33 5V P+/NW diode 400 0.7 4.266 Pass
D34 5V P+/NW diode 800 0.7 5.564 Pass
CO
7.2.6.10. 6V P GDMOS (p6_esd_ckt)

IC
Process: SMIC 0.18BCD V3E platform

6V ESD protection: using GDPMOS for 6V ESD protection.
TLP Characterization:
SM
(+) (-)
G G
PGR B S D S B PGR
WP WP
WN
PSUB
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Cell name HBM Target Vt1(V) Vh(V) Vt2(V) It2(A) DC BV (V)

GDPMOS6_ESD_W480 2KV 9.91 9.38 11.3 (at 1.33A) 1.65 10.2
AL
Cell name(Estimated) HBM Target Vt1(V) Vh(V) Vt2(V) It2(A) DC BV (V)
TI
GDPMOS6_ESD_W1800 8KV 9.91 9.38 11.3 (at 5.33A) 6 10.2
EN
The estimated It2 showed in the table refers to the second breakdown current within ESD design
window (Vt1&Vt2<device BV, Vh>Vop+1.5V).
ID
7.2.7. Capacitor characterization data summary
NF
7.2.7.1. MIM location options

CO
For 1 Top metal(TM1 or TM2 or MTT2)
MIM
MIM Location 1P3M 1P4M 1P5M 1P6M
IC
Option
between M2 and top metal X
SM
1st option
between M2 and M3 X
2nd option between M3 and M4 X
between M4 and M5 X
3rd option between M3 and M4 X
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
For 2 Top metal (TM1+(TM2 or MTT2))
MIM Option MIM Location 1P4M 1P5M 1P6M

between M2 and first top metal X
AL
1st option
between M5 and first top metal
between M2 and M3
TI
2nd option between M3 and M4 X
between M4 and M5
EN
1) 1st MIM
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
1st MIM Via table
Metal Option Under Via Bottom Metal Above Via

IC
1P3M V1 M2 TV1
1P4M V2 M3 TV1
SM
One TM
1P5M V3 M4 TV1
1P6M V4 M5 TV1
1P4M V1 M2 V2
Two TMs 1P5M V2 M3 V3
1P6M V3 M4 V4
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
2) 2nd MIM
AL
TI
EN
ID
NF
2nd MIM Via table

CO

1P4M V1 M2 V2
One TM 1P5M V2 M3 V3
IC
1P6M V3 M4 V4
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
3) 3rd MIM
AL
TI
EN
ID
NF
CO
3rd MIM Via table

IC

SM
7.2.7.2. 1.0fF MIM
Device description 1.0fF MIM
Model name mim_ckt
Terminal count 2
Terminal definition n2 n1
BV 36V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
2) Device symbol
AL
TI
3) Layout
EN
ID
NF
4) Mismatch
CO
IC
SM
MIM(Cspec=1 fF/um2) capacitor mismatch vs 1/Area at T=25 Y=0.0074* (MiM area um2)
7.2.7.3. 2fF MIM
Device description 2fF MIM
Model name mim2_ckt
Terminal count 2
BV 33V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
2) Device symbol
AL
3) Layout
TI
EN
ID
NF
4) Mismatch
CO
IC
SM
MIM(2fF/mm2) Capacitor Mismatch vs 1/sqrt(Wdrawn*Ldrawn*M) at T=25C
7.2.7.4. MOM
Device description MOM
Model name mom_ckt
Terminal count 2
BV >60V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
2) Device symbol
AL
TI
3) Layout
EN
ID
NF
CO
4) Mismatch
IC
SM
MOM Capacitor Mismatch vs 1/sqrt(cap*1e12) at T=25C
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.7.5. Top metal MOM
Device description Top metal MOM
AL
Model name mom_tm_ckt
Terminal count 2
TI
BV >60V
2) Device symbol
EN
ID
NF
3) Layout
CO
IC
SM
7.2.7.6. 1.8V NMOS Varactor
1) Device Description
Device description 1.8V NMOS Varactor

Model name pvar18_ckt
Terminal count 2
BV 5.2V
LDD NLL
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
2) Device symbol
AL
TI
3) Layout EN
ID
NF
CO
4) Cross section
IC
SM
Diode D1
BV 15V
Space PW to NW=0um
5) CV curve
FF/SS corner range is about -/+5%
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
7.2.7.7. 5V NMOS Varactor
EN
ID
NF
Device description 5V NMOS Varactor

Model name pvar50_ckt
Terminal count 2
CO
BV 15V
LDD NLH
IC
SM
2) Device symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
3) Layout
AL
TI
4) Cross section
EN
ID
NF
Diode D1
BV 15V
CO
Space PW to NW=0um
5) CV curve
IC
FF/SS corner range is about -/+5%

SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.7.8. 5V NMOS Varactor in HVBN
Device description 5V N Well with HVBN Varactor
AL
Model name pvar50hvbniso_ckt
Terminal count 2
TI
BV 15V
LDD NLH
2) Device symbol EN
ID
NF
CO
3) Layout
IC
SM
4) Cross section
Diode D1 D2
BV 16V 54V
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.8. Resistor characterization data summary
Type Sheet Resistance(Ω/􀂆) TC1(1/℃) TC2(1/℃2)

1K HRP 985 -8.37e-4 1.72e-6
3K HRP 3245 -1.8e-3 4.06e-6
AL
P+ poly sab 344.2 -2.94E-04 5.92E-07
P+ poly 9.5 2.89E-03 7.21E-07
TI
N+ poly sab 700 -1.40E-03 -4.47E-08
N+ poly 9.5 2.93E-03 1.17E-06
P+ diff sab
P+ diff
142.3
7.2
EN
1.14E-03 -7.89E-07
ID
N+ diff sab 95.02 1.39E-03 -1.52E-06
N+ diff 8
NW_AA 432 2.77E-03 1.12E-05
NF
NW_STI 895.2 2.54E-03 2.22E-05

5V NW_AA 270 3.63E-03 2.17E-05
CO
5V_NW_STI 313.1 3.73E-03 9.99E-06

M1 Resistor 0.1319 3.37E-03 -3.42E-06
M2 Resistor 0.08577 3.43E-03 -2.63E-06
IC
M3 Resistor 0.08101 3.39E-03 -1.05E-06

M4 Resistor 0.08076 3.36E-03 -2.20E-06
SM
M5 Resistor 0.08076 3.36E-03 -2.20E-06

TM 8k Resistor 0.0338 3.6e-03 -5.15e-07
TM 9k Resistor 0.0297 3.6e-03 -5.15e-07
TM 33k Resistor 0.01 3.6e-03 -5.15e-07
TM 38k Resistor 0.0083 3.6e-03 -5.15e-07
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.8.1. 1K ohm/sq P- Poly HRI w/o silicide
Device description 1K ohm/sq P- Poly HRI w/o
AL
silicide
Model name rhrp_ckt, rhrp_3t_ckt,
rhrphv_3t_ckt
TI
2) Key Parameters
1K HRP 985 -8.37e-4 1.72e-6 EN
3) Symbol
ID
NF
CO
4) Layout/Cross section
rhrp_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 0.63um, the STI
IC
surface suffer the leakage risk.

rhrphv_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 2um, no risk.
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
5) Device curve
EN
Length/Resistance versus width for sheet resistance and delta width’s extraction (25C)
Extracted sheet resistance versus width for recommend width’s selection (25C)
Simulated (lines) and measured (symbols) resistance which normalized to Rsh(V=0) versus voltage
ID
Sheet resistance which normalized to Rsh (T=25C) for various widths (Tc1=-8.37E-04, Tc2=1.72E-06)
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
6) Mismatch
AL
TI
EN
ID
7.2.8.2. 3K ohm/sq P- Poly HRI w/o silicide
NF
Device description 3K ohm/sq P- Poly HRI w/o silicide
CO
Model name rhrp_3k_ckt, rhrp_3k_3t_ckt, rhrphv_3k_3t_ckt
2) Key Parameters
IC

3K HRP 3245 -1.8e-3 4.06e-6
SM
3) Symbol
rhrp_3k_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 0.63um, the STI
rhrphv_3k_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 2um, no risk.
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
5) Device curve
CO
Extracted sheet resistance versus width for recommend width’s selection (25C)
Simulated (lines) and measured (symbols) resistance which normalized to Rsh(V=0) versus voltage
Sheet resistance which normalized to Rsh (T=25C) for various widths (Tc1=-1.8E-03, Tc2=4.06E-06)
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
6) Mismatch
EN
ID
NF
CO
7.2.8.3. P+ Poly w/o silicide

IC
SM
Device description P+ Poly w/o silicide

Model name rpposab_ckt, rpposab_3t_ckt, rpposabhv_3t_ckt
2) Key Parameters
rpposab 344.2 -2.94E-04 5.92E-07
3) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
rpposab_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 0.44/0.25um, the
STI surface suffer the leakage risk.
rpposabhv _3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 2um, no risk.
AL
TI
EN
ID
NF
CO
5) Device curve
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
6) Mismatch
NF
CO
IC
SM
7.2.8.4. P+ Poly w/i silicide
Device description P+ Poly w/i silicide
Model name rppo_ckt, rppo_3t_ckt, rppohv_3t_ckt
2) Key Parameters
rppo (W≥2um) 9.5 2.89E-03 7.21E-07
3) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
rppo_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 0.17um, the STI
TI
rppohv_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 2um, no risk.
EN
ID
NF
CO
IC
SM
5) Device curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
6) Mismatch
NF
CO
IC
SM
7.2.8.5. N+ Poly w/o silicide
Device description N+ Poly w/o silicide
Model name rnposab_ckt, rnposab_3t_ckt, rnposabhv_3t_ckt
2) Key Parameters
rnposab 700 -1.40E-03 -4.47E-08
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
3) Symbol
AL
TI
rpposab_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 0.44/0.25um, the
STI surface suffer the leakage risk. EN
rpposabhv_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 2um, no risk.
ID
NF
CO
IC
SM
5) Device curve
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
6) Mismatch
SM
7.2.8.6. N+ Poly w/i silicid
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Device description N+ Poly w/i silicide

Model name rnpo_ckt, rnpo_3t_ckt, rnpohv_3t_ckt
2) Key Parameters
AL
rnpo 9.5 2.93E-03 1.17E-06
TI
3) Symbol
EN
ID
NF
rpposab_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 0.25um, the STI
rpposabhv_3t_ckt: the voltage between poly and psub exceed 60V in case of STI width = 2um, no risk.
CO
IC
SM
5) Mismatch
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
7.2.8.7. P+ DIFF w/o silicide
NF
Device description 3T P+ DIFF w/o silicide

Model name rpdifsab_3t_ckt
CO
Terminal count 3
Terminal definition In out sx
2) Key Parameters
IC

rpdifsab_3t_ckt 142.3 1.14E-03 -7.89E-07
SM
3) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Device curve
AL
TI
EN
ID
NF
CO
IC
SM
6) Mismatch
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.8.8. P+ DIFF w/i silicide
Device description 3T P+ DIFF w/i silicide
AL
Model name rpdif_3t_ckt
Terminal count 3
Terminal definition in out sx
TI
2) Key Parameters
rpdif_3t_ckt 7.2
EN
ID
3) Symbol
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Mismatch
AL
TI
EN
ID
7.2.8.9. N+ DIFF w/o silicide
NF
Device description 3T N+ DIFF w/o silicide
Model name rndifsab_3t_ckt
CO
Terminal count 3
2) Key Parameters
IC

rndifsab_3t_ckt 95.02 1.39E-03 -1.52E-06
SM
3) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
5) Device curve
EN
ID
NF
CO
IC
SM
6) Mismatch
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
7.2.8.10. N+ DIFF w/i silicide
ID
NF
Device description 3T N+ DIFF w/i silicide

Model name rndif_3t_ckt
Terminal count 3
CO
Terminal definition In out sx
2) Key Parameters
IC
rndif_3t_ckt 8
SM
3) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
5) Mismatch
EN
ID
NF
CO
IC
7.2.8.11. NW diff(under AA)

SM
Device description 3T_NW diff under AA
Model name rnwaa_3t_ckt
Terminal count 3
2) Key Parameters
rnwaa_3t_ckt 432 2.77E-03 1.12E-05
3) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
7.2.8.12. NW diff(under STI)
Device description 3T_NW diff under STI
Model name rnwsti_3t_ckt
Terminal count 3
2) Key Parameters
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual

rnwsti_3t_ckt 895.2 2.54E-03 2.22E-05
3) Symbol
AL
TI
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.8.13. 5V NW diff(under AA)
Device description 3T_5V NW diff under AA
AL
Model name rnwaa50_3t_ckt
Terminal count 3
TI
2) Key Parameters
rnwaa50_3t_ckt 270 3.63E-03 2.17E-05
EN
3) Symbol
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
5) Device curve
AL
TI
EN
ID
NF
CO
IC
SM
7.2.8.14. 5V NW diff(under STI)
Device description 3T_5V NW diff under STI
Model name rnwsti50_3t_ckt
Terminal count 3
2) Key Parameters
rnwsti50_3t_ckt 313.1 3.73E-03 9.99E-06
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
3) Symbol
AL
TI
EN
ID
NF
5) Device curve
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
7.2.8.15. M1 Resistor (rm1)
ID
NF
Device description M1 Resistor

Model name rm1
Terminal count 2
CO
Terminal definition in out
2) Key Parameters
IC
M1 Resistor 0.1319 3.37E-03 -3.42E-06

SM
3) Symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
Model name rm2
Terminal count 2
AL
2) Key Parameters
TI
M2 Resistor 0.08577 3.43E-03 -2.63E-06
3) Symbol EN
ID
NF
4) Layout
CO
IC
SM
Model name rm3
Terminal count 2
2) Key Parameters
M3 Resistor 0.08101 3.39E-03 -1.05E-06
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
3) Symbol
AL
TI
4) Layout
EN
ID
NF
CO
IC

Model name rm4
SM
Terminal count 2
2) Key Parameters
M4 Resistor 0.08076 3.36E-03 -2.20E-06
3) Symbol
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
4) Layout
TI
EN
ID
NF
CO
Model name rm5

Terminal count 2
IC
2) Key Parameters
SM

M5 Resistor 0.08076 3.36E-03 -2.20E-06
3) Symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
7.2.8.20. TM_8K (rtm_8k)
NF
Device description TM_8K
Model name rtm_8k
CO
Terminal count 2
IC
2) Key Parameters
SM
rtm_8k 0.0338 3.6e-03 -5.15e-07
3) Symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
7.2.8.21. TM_9K (rtm_9k)

CO
Model name rtm_9k
IC
Terminal count 2
SM
2) Key Parameters
rtm_9k 0.0297 3.6e-03 -5.15e-07
3) Symbol
4) Layout
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
5) Device curve
CO
IC
SM
Sheet resistance which normalized to Rsh (T=25C) for various widths
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
AL
TI
EN
ID
NF
CO
IC
SM
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
7.2.8.22. TM_33K (rtm_33k)
AL
Model name rtm_33k
Terminal count 2
TI
2) Key Parameters
Type
rtm_33k
Sheet Resistance(Ω/􀂆) TC1(1/℃) TC2(1/℃2)
0.01 3.6e-03 -5.15e-07
EN
ID
3) Symbol
NF
CO
IC
4) Layout
SM
7.2.8.23. TM_40K (rtm_33k)
Model name rtm_40k
Terminal count 2
20V/24V/30V/35V /40V 0_REV0
Platform Device
Design Manual
2) Key Parameters
rtm_40k 0.0083 3.6e-03 -5.15e-07
AL
3) Symbol
TI
EN
4) Layout
ID
NF
CO
7.2.9. MVN to MVP BV

IC
SM
8. Attachment: NA

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Semiconductor Manufacturing International Corporation

Document Level: (For Engineering & Quality Document/工程暨品质文件专用)

Document Change History

SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION

0.18um V3E BCD 1.8V/5V/6V/9V/12V/16V/20V/24V/30V/35V /40V Platform Device Introduction

SMIC Confidential – Do Not Copy

7.1.1. Document Overview...............................................................................................................9

7.1.3. Supported Potentials ..............................................................................................................9

7.1.4. 0.18um Tech. Seal Ring and Scribe Lane ............................................................................10

7.2. DEVICE CHARACTERIZATION SUMMARY ....................................................................................... 11

7.2.1. LV/MV devices characterization summary .......................................................................... 11

7.2.1.1. 1.8V NMOS (n18_ckt) ................................................................................................ 11

7.2.1.3. 1.8V native NMOS (nnt18_ckt) ..................................................................................20

7.2.2. LDMOS/DEMOS devices characterization summary .........................................................41

7.2.2.1. 5V NLDMOS (D4) (nld5g5_sa_iso_hvbn_ckt) ..........................................................42

7.2.2.3. 9V NLDMOS (nld9g5_gs_iso_hvbn_ckt) ...................................................................50

7.2.2.14. 40V NLDMOS (nld40g5_rox_gs_ckt) ........................................................................97

7.2.2.16. 6V PDEMOS (pde6g5_sab_hvbn_ckt) ......................................................................106

7.2.2.19. 16V PDEMOS (pde16g5_gs_hvbn_ckt) ...................................................................120

7.2.2.20. 20V PDEMOS (pde20g5_gs_hvbn_ckt) ...................................................................124

7.2.3. Bipolar Transistor characterization data summary...........................................................143

7.2.3.1. 1.8V vertical PNP (pnp18a100_ckt) ..........................................................................143

7.2.3.4. 5V vertical PNP (pnp50a100_poly_ckt) ....................................................................150

7.2.3.15. High Beta NPN (npnhbeta100_sab100_ckt) .............................................................175

7.2.3.17. High Beta NPN (npnhbeta100_sab4_ckt) .................................................................180

7.2.4. Diode characterization data summary ..............................................................................182

7.2.4.1. 1.8V N+/Pwell diode (ndio18) ..................................................................................182

7.2.4.3. 1.8V P+/N-well diode (pdio18) .................................................................................186

7.2.4.12. HVBN/Psub Diode (hvbnpsubdio) ............................................................................202

7.2.5.1. 9V ESD Protection.....................................................................................................208

7.2.5.7. 35V ESD Protection...................................................................................................220

7.2.6. ESD MOS characterization data summary........................................................................224

7.2.6.1. 1.8V N GGMOS (n1d8_esd_ckt) ..............................................................................224

7.2.6.2. 1.8V P GDMOS (p1d8_esd_ckt) ...............................................................................226

7.2.6.4. 1.8V ESD P+/Nwell Diode (pdio1d8_esd) ................................................................228

7.2.7. Capacitor characterization data summary ........................................................................233

7.2.7.1. MIM location options ................................................................................................233

7.2.8.1. 1K ohm/sq P- Poly HRI w/o silicide .........................................................................247

7.2.8.3. P+ Poly w/o silicide ...................................................................................................251

7.2.8.6. N+ Poly w/i silicid .....................................................................................................257

7.2.8.7. P+ DIFF w/o silicide ..................................................................................................259

7.2.8.16. M2 Resistor (rm2)......................................................................................................272

7.2.9. MVN to MVP BV ................................................................................................................281

Reference documents Reference Tech

spice model V/24V/30V/35V/40V SPICE

0.18um V3E BCD TD-BC18-DR-201

7.1.1. Document Overview

7.1.2. Process Overview

for all Power IC applications at or below 40V.

7.1.3. Supported Potentials

7.1.4. 0.18um Tech. Seal Ring and Scribe Lane

7.2. Device Characterization summary

7.2.1. LV/MV devices characterization summary

Model name n18_ckt

2) Operation voltage range

(μA/μm) (um) (mΩmm2) (um) (nC) (nC) (nCmΩ) (nC*mΩ)

Idlin Pitch Ron W Qgg Qgd QggRon QgdRon