RTUIF-18

60 GHz Transmitter Circuits in 65nm CMOS

Alberto Valdes-Garcia, Scott Reynolds and Jean-Oliver Plouchart

IBM T. J. Watson Research Center, Yorktown Heights, NY, 10598

Abstract — This work presents fundamental building Quadrature

IF Filter mmWave Image Reject
Mixer
blocks for a 60GHz transmitter front-end. The circuits are Mixer Driver
I
implemented in a 65nm bulk CMOS technology, operate from
PA
a 1.2V supply, and attain state-of-the-art performance for
Q
multi-Gb/s wireless applications. A single-stage, single-ended,
I&Q
power amplifier achieves peak power gain of 4.5dB, output
1dB compression point of 6dBm, saturated power of 9dBm, ÷2 2X

and peak power added efficiency of 8.5% at 62GHz. A PLL output

double-balanced, Gilbert-based, up-conversion mixer Fig. 1. Superheterodyne 60GHz transmitter architecture
achieves 6.5dB of conversion loss and output 1dB GND GND VDD
compression point of -5.0dBm with LO of 50GHz and IF of
C1 C1
10GHz. Millimeter-wave design considerations and

TL4
measurements over frequency and temperature are discussed.

TL1

TL3
RFOUT
Index Terms — Power amplifier, up-conversion mixer,
millimeter-wave, wireless transmitter, CMOS. RFIN TL5 P2

P1 TL2
M1

R1
I. INTRODUCTION GND
GND
The availability of silicon IC technologies capable of
Fig. 2. Simplified circuit schematic of the 60 GHz PA
operating in the millimeter-wave (mmWave) range, and
the commercial interest in high speed wireless applications a reference point for this RF front-end design. The 60GHz
has motivated the development of integrated 60 GHz band can be covered with an LO in the range of 50GHz
transceivers. In SiGe BiCMOS, complex and fully and an IF in the range of 10 GHz.
integrated transmitter and receiver circuits capable of
multi-Gb/s data transmission in the 60 GHz band have
II. CIRCUIT DESIGN
already been demonstrated [1]. As a natural evolution
towards a 60 GHz system-on-chip (SoC), different
A. Power Amplifier
mmWave building blocks and sub-systems have been
investigated using deep sub-micron CMOS technologies. A simplified circuit schematic for the CMOS PA is
So far, most of the attention in this exploratory work has shown in Fig. 2. It is a single-stage, single-ended common
been devoted to receiver circuits [2-4], where a good level source amplifier. This relatively simple configuration is
of integration and performance has been achieved. chosen to investigate the large-signal compression
Nevertheless, the performance of large signal circuits with characteristics of a 65nm nfet. A significant portion of the
nanometer CMOS devices at mmWave frequencies is less design effort was placed on the layout of the power device
understood. The power delivery capability, linearity, and to optimize its performance while complying with electro-
efficiency of transmitter front-end building blocks are migration reliability requirements. The employed nfet has
critical for the overall performance of a 60 GHz SoC. an equivalent width of 62um, and its DC bias current is
Moreover, the target transmission speeds and modulations 23mA, which results in a current density of 370uA/um.
for 60 GHz applications result in demanding speed and The supply voltage is 1.2V. All of the employed
complexity requirements for the digital baseband transmission lines (TLs) are microstrip.
processors; hence, these SoCs will benefit from the use of The input matching network takes into account the
a CMOS node with the smallest feature size possible. capacitance of the input RF pad (P1), and employs TLs
This work investigates the operation of front-end 60 TL1-3. TL1 and TL3 are connected to AC ground through
GHz transmitter building blocks, namely power amplifier bypass capacitors C1. A 300Ω resistor (R1) is added next
(PA) and up-conversion mixer, in a contemporary 65nm to the transistor gate to procure unconditional stability and
bulk CMOS process. Fig. 1 depicts a potential wide-band match. In simulations, the addition of this
superheterodyne transmitter architecture, which is used as component to the input network reduces the power gain by

978-1-4244-1808-4/978-1-4244-1809-1/08/$25.00 © 2008 IEEE 641 2008 IEEE Radio Frequency Integrated Circuits Symposium
 VDD
Fig. 3 describes the up-conversion mixer. It is a fully
differential, double-balanced Gilbert cell. IF, LO and RF
center frequencies of 10 GHz, 50 GHz and 60 GHz,
TL7

TL7
RFOUT- RFOUT+ respectively, are considered for the design. The supply
P4 TL8 TL5 P4 voltage is 1.2V and the total DC bias current is 24mA. The
IF input transconductor is an inductively degenerated
LO Match LO Match
nmos differential pair. A differential inductor (L1) is
M2 M2 M2 M2
Network Network chosen instead of two separate inductors to provide
VDD
P3 P3
common-mode rejection. The inductance value is chosen
to provide a wideband IF input match. The use of current
TL6

TL6
LO+ LO-
M3 M3
steering is proposed for this mmWave mixer to improve its
IF+ C2 VGP C2
IF- CG and linearity at the expense of additional power. The
P5 M4 M4 P5 nominal current provided to the input transconductor
L1
R2 R2
through pmos transistors M3 is 12mA. The connection
between the input stage and the switching transistors (M2)
VGN GND VGN is modeled as TL6. Stubs TL7 tune the output port of the
mixer for maximum gain at 60 GHz.
Fig. 3. Simplified circuit schematic of the 60 GHz active up-
conversion mixer The LO matching network (not shown for simplicity) is
composed of additional transmission lines and short stubs.
IF At the LO port (RF pads P3), a differential impedance of a
value close to 100Ω is seen in a frequency range of
VDD
approximately 45-65GHz. 50Ω resistors are connected
from AC ground to the gate of each pair of switching
transistors M2 to provide a resistive termination. This
R value of resistance was chosen so that the LO voltage
F LO swing that corresponds to a given conversion gain could
INPUT OUTPUT
be known through measurements. Note that a higher
resistance value can be employed to increase the effective
LO voltage swing (and hence the CG) for a given input
power into the LO port.
Bias

III. MEASUREMENT RESULTS

(a) (b)
The described circuits were fabricated in a 65nm bulk
Fig. 4. Micrographs of the fabricated 65nm CMOS circuits.
(a) Power amplifier, (b) Up-conversion mixer. CMOS process. Fig. 4 shows the chip micrographs. The
size of both designs is limited by the pad frame and the
about 1dB but has no significant impact on the o1dBCP. necessary space between them to accommodate the RF
The output network (TL4-5 and P2) is designed through probes. The PA and mixer use an area of 450umX600um
schematic load-pull simulations. and 0.7mmX1.4mm, respectively. All of the measurements
are performed on-wafer.
The nfet employed for the PA is characterized as a
B. Up-Conversion Mixer
stand-alone device including the parasitics introduced by
The design of an up-conversion mixer for a all of the metal layers required for its connection to the
superheterodyne 60 GHz transmitter faces multiple and top-metal TLs. From s-parameter measurements, the
significant challenges. Both, LO and RF ports operate in calculated cut-off frequency (fT) is 230 GHz.
the mmWave range; as a result, the conversion gain (CG)
A. Power Amplifier
is sensitive to the insertion loss and parasitic components
of the interconnection elements. In addition, since power Fig. 5 shows the measured s-parameters of the PA. In
amplification in the transmitter front-end is expensive in a bandwidth of more than 10 GHz (55-65 GHz) the PA
terms of power consumption, the mixer’s output 1dB attains a power gain higher than 4dB and input match
compression point (o1dBCP) should be as high as better than -10dB. Good output match and reverse
possible. isolation are also obtained.

642
 -4
Conversion Gain o1dBCP
-4.5

Conversion Gain [dB], o1dBCP [dBm]

-5

-5.5

-6

-6.5

-7

-7.5

-8
6 7 8 9 10 11 12 13 14
pFET current [mA]

Fig. 8. Measured 60GHz conversion gain and o1dBCP as a

Fig. 5. Measured s-parameters of the PA function of current through pmos transistors M3
-4
10 Conversion Gain o1dBCP
-4.5
9
Power Gain [dB], PAE [%], o1dBCP [dBm]

Conversion Gain [dB], o1dBCP [dBm]

-5
8
-5.5
7
-6
6
-6.5
5 -7

4 -7.5

3 -8

2 -8.5
Peak Power Gain Peak PAE o1dBCP
-9
1
58 58.5 59 59.5 60 60.5 61 61.5 62
0 RF Output Frequency [GHz]
55 57 59 61 63 65
Fre que ncy [GHz] Fig. 9. Measured conversion gain and o1dBCP as a function
Fig. 6. Measured large-signal frequency response of the PA of RF output frequency for IF=10GHz, LO=48-52GHz
9

changes from 10.5 to 9 dBm, showing that the PA has a

Power Gain [dB], PAE [%], o1dBCP [dBm]

7 large-signal wideband behavior. Fig. 7 shows the result of

6 large signal measurements over temperature. A constant
5 current density was kept for all temperatures.
4

3
B. Up-Conversion Mixer
2
Peak Power Gain Peak PAE o1dBCP
For the mixer characterization, the differential LO signal
1 is applied trough an external waveguide balun and the
0 output is observed with a spectrum analyzer that uses an
20 30 40 50 60 70 80 90
Te mpe rature [°C] external harmonic mixer for measurements. The measured
Fig. 7. Measured temperature response of the PA at 60 GHz LO input return loss is better than -11dB from 45 GHz to
65 GHz and the LO-RF isolation at 50 GHz is 30 dB.
Swept power gain, compression and efficiency Measurements at an RF output of 60GHz are performed
measurements are also performed. The available input with LO and IF frequencies of 10 GHz and 50 GHz
power from the source is calibrated with a through respectively. Fig. 8 shows the performance of the mixer as
measurement on a low-loss GSG substrate, and the a function of the bias current applied through the pmos
frequency dependent loss from the probe tip to the transistors M3, while keeping the total bias current
spectrum analyzer is calibrated using a second-tier short- constant at 24mA. Under nominal bias conditions (pmos
open-load (SOL) adapter technique. The overall current=12mA), the mixer’s performance is relatively
calibration procedure has an estimated accuracy of 0.5dB constant over temperature up to 65°C. At 85°C, the
for both input and output power levels, and is performed at measured 60GHz CG and o1dBCP are -7.5dB and -
each power level and frequency to remove any non-linear 6.5dBm respectively. Figure 9 presents the frequency
and/or frequency dependent effect of the test equipment. response of the mixer. All of the previously mentioned
Fig. 6 shows the large signal behavior of the PA from 56 measurements are performed at an LO power of 5dBm.
to 64 GHz. In this frequency range, the measured o1dBCP With LO power of 3dBm, the measured 60GHz CG and
changes by less than 1dB, and the saturated output power o1dBCP are -7.5dB and -6.5dBm respectively.

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 TABLE I
STATE OF THE ART IN CMOS MILLIMETER-WAVE POWER AMPLIFIERS
Ref. Topology DC Biasing Frequency Power Gain o1dBCP Sat. Power PAE CMOS
[GHz] [dB] [dBm] [dBm] [%] Node
This work 1-stage, CS, SE 23mA, 1.2V 62 4.5 6 9 8.5 65nm
[5] 3-stage, CS, SE 26.5mA, 1.5V 60 4.7 6.4 9.3 7.4 90nm
[6] 2-stage, CS, SE 23mW 57 9.8 6.7 - 20 90nm
[7] 2-stage CC, 1-stage CS, SE 45mW, 1.5V 60 14 1.6 6 5.2 90nm

TABLE II
STATE OF THE ART IN CMOS MILLIMETER-WAVE UP-CONVERSION MIXERS
Power Frequency [GHz] LO Power Conversion o1dBCP LO-RF CMOS
Ref. Topology
[mW] RF IF [dBm] Gain [dB] [dBm] Isolation [dB] Node
This work DF, DB, Gilbert w/ current steering 29 60 10 5 -6.5 -5.0 30 65nm
[8] DF, DB Gilbert w/ LO buffer 70 60 1-5 - -4 to -7 - - 90nm
[9] SB, Resistive, w/ Balun 0 60 2 9 -13.5 -19 34 65nm
[10] DF, DB, Gilbert w/ LO & RF baluns 13.2 51 11 0 -11 -12 26.5 90nm
CS = common source, CC = cascode, DF = differential, SE = single-ended, DB = double-balanced, SB = single balanced

VII. SUMMARY AND CONCLUSIONS REFERENCES

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