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Jameco Part Number 844895

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes 0 Operation
• 33 MHz Clock Rate
• Byte Mode and 128-byte Page Mode for Program Operations
• Sector Architecture:
– Two Sectors with 32K Bytes Each
– 256 Pages per Sector
• Product Identification Mode
• Low-voltage Operation
– 2.7 (VCC = 2.7 to 3.6V)
512Kbit High
•
•
Sector Write Protection
Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software
Speed SPI
Data Protection
• Self-timed Program Cycle (75 µs/byte typical) Serial Flash
• Self-timed Sector Erase Cycle (1 second/sector typical)
• Single Cycle Reprogramming (Erase and Program) for Status Register Memory
• High Reliability
– Endurance: 10,000 Write Cycles Typical 512K (65,536 x 8)
– Data Retention: 20 Years
• 8-lead JEDEC SOIC and 8-lead SAP Packages

Description
AT25F512A
The AT25F512A provides 524,288 bits of serial reprogrammable Flash memory orga-
nized as 65,536 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25F512A is available in a space-saving 8-lead JEDEC SOIC and
8-lead SAP packages. Preliminary
The AT25F512A is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All write cycles are completely self-timed.
Block write protection for the entire memory array is enabled by programming the sta-
tus register. Separate write enable and write disable instructions are provided for
additional data protection. Hardware data protection is provided via the Write Protect
(WP) pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
8-lead SOIC
Table 1. Pin Configuration
CS 1 8 VCC
Pin Name Function
SO 2 7 HOLD
CS Chip Select WP 3 6 SCK
SCK Serial Data Clock GND 4 5 SI
SI Serial Data Input
SO Serial Data Output 8-lead SAP

GND Ground VCC 8 1 CS

VCC Power Supply HOLD 7 2 SO
SCK 6 3 WP
WP Write Protect
SI 5 4 GND
HOLD Suspends Serial Input
Rev. 3345E–FLASH–8/05
Bottom View

1
Absolute Maximum Ratings*
Operating Temperature........................................−40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature .........................................−65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground ........................................ −1.0V to +5.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage ............................................ 4.2V conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA

Figure 1. Block Diagram

65,536 x 8

2 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

Table 2. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 20 MHz, VCC = +3.6V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.

Table 3. DC Characteristics(1)
Applicable over recommended operating range from: TAI = −40 to +85°C, VCC = +2.7 to +3.6V,
TAC = 0 to +70°C, VCC = +2.7 to +3.6V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC Supply Voltage 2.7 3.6 V
ICC1 Supply Current VCC = 3.6V at 33 MHz, SO = Open Read 10.0 15.0 mA
ICC2 Supply Current VCC = 3.6V at 33 MHz, SO = Open Write 25.0 35.0 mA
VCC = 2.7V, CS = VCC; SCK, SI, WP,
ISB Standby Current 2.0 10.0 µA
HOLD = 0V or VCC
IIL Input Leakage VIN = 0V or VCC −3.0 3.0 µA
IOL Output Leakage VIN = 0V or VCC, TAI = −40°C to 85°C −3.0 3.0 µA
VIL(2) Input Low Voltage −0.6 VCC x 0.3 V
VIH(2) Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL Output Low Voltage IOL = 0.15 mA 0.2 V
2.7V ≤ VCC ≤ 3.6V
VOH Output High Voltage IOH = −100 µA VCC − 0.2 V
Notes: 1. Preliminary – subject to change
2. VIL and VIH max are reference only and are not tested.

3
3345E–FLASH–8/05
Table 4. AC Characteristics (Preliminary - Subject to Change)
Applicable over recommended operating range from TAI = −40 to +85°C, VCC = +2.7 to +3.6V
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Min Typ Max Units
fSCK SCK Clock Frequency 0 33 MHz
tRI Input Rise Time 20 ns
tFI Input Fall Time 20 ns
tWH SCK High Time 9 ns
tWL SCK Low Time 9 ns
tCS CS High Time 25 ns
tCSS CS Setup Time 25 ns
tCSH CS Hold Time 10 ns
tSU Data In Setup Time 5 ns
tH Data In Hold Time 5 ns
tHD Hold Setup Time 15 ns
tCD Hold Time 15 ns
tV Output Valid 9 ns
tHO Output Hold Time 0 ns
tLZ Hold to Output Low Z 200 ns
tHZ Hold to Output High Z 200 ns
tDIS Output Disable Time 100 ns
tEC Erase Cycle Time per Sector 1.1 s
tSR Status Register Write Cycle Time 60 ms
tBPC Byte Program Cycle Time(1) 75 100 µs
Endurance(2) 10K Write Cycles(3)
Notes: 1. The programming time for n bytes will be equal to n x tBPC.
2. This parameter is ensured by characterization at 3.0V, 25°C only.
3. One write cycle consists of erasing a sector, followed by programming the same sector.

4 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

Serial Interface MASTER: The device that generates the serial clock.
Description SLAVE: Because the SCK pin is always an input, the AT25F512A always operates as a
slave.
TRANSMITTER/RECEIVER: The AT25F512A has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25F512A, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25F512A is selected when the CS pin is low. When the device is
not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will
remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F512A.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The AT25F512A has a write lockout feature that can be activated by
asserting the WP pin. When the lockout feature is activated, locked-out sectors will be
read only. The write protect pin will allow normal read/write operations when held high.
When the WP is brought low and WPEN bit is “1”, all write operations to the status register
are inhibited. WP going low while CS is still low will interrupt a write to the status register.
If the internal status register write cycle has already been initiated, WP going low will have
no effect on any write operation to the status register. The WP pin function is blocked
when the WPEN bit in the status register is “0”. This will allow the user to install the
AT25F512A in a system with the WP pin tied to ground and still be able to write to the sta-
tus register. All WP pin functions are enabled when the WPEN bit is set to “1”.

5
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 Figure 2. SPI Serial Interface
MASTER: SLAVE:
MICROCONTROLLER AT25F512A
DATA OUT (MOSI) SI

DATA IN (MISO) SO

SERIAL CLOCK (SPI CK) SCK

SS0 CS

SS1
SI
SS2
SO
SS3
SCK

CS

SI

SO

SCK

CS

SI

SO

SCK

CS

6 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

Functional The AT25F512A is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
Description
The AT25F512A utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low transition.
Write is defined as program and/or erase in this specification. The commands Program,
Sector Erase, Chip Erase, and WRSR are write instructions for AT25F512A.

Table 5. Instruction Set for the AT25F512A

Instruction
Instruction Name Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
PROGRAM 0000 X010 Program Data into Memory Array
SECTOR ERASE 0101 X010 Erase One Sector in Memory Array
CHIP ERASE 0110 X010 Erase All Sectors in Memory Array
RDID 0001 X101 Read Manufacturer and Product ID

WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All write instructions must therefore be preceded by the WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI
instruction disables all write commands. The WRDI instruction is independent of the sta-
tus of the WP pin.
READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta-
tus register. The Ready/Busy and write enable status of the device can be determined
by the RDSR instruction. Similarly, the block write protection bits indicate the extent of
protection employed. These bits are set by using the WRSR instruction. During internal
write cycles, all other commands will be ignored except the RDSR instruction.

Table 6. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X X BP0 WEN RDY

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3345E–FLASH–8/05
 Table 7. Read Status Register Bit Definition
Bit Definition
Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the
Bit 0 (RDY)
write cycle is in progress.
Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1” indicates
Bit 1 (WEN)
the device is write enabled.
Bit 2 (BP0) See Table 8.
Bits 3–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 9.
Bits 0–7 are “1”s during an internal write cycle.

READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufac-
turer and product ID of the device. The first byte after the instruction will be the
manufacturer code (1FH = ATMEL), followed by the device code, 65H.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
two levels of protection for the AT25F512A. The AT25F512A is divided into two sectors
where all of the memory sectors can be protected (locked out) from write. Any of the
locked-out sectors will therefore be read only. The locked-out sectors and the corre-
sponding status register control bits are shown in Table 8.
The two bits, BP0 and WPEN, are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, tWC, RDSR).

Table 8. Block Write Protect Bits

Status Register Bits AT25F512A
BP0 Array Addresses Locked Out Locked-out Sector(s)
0 None None
1 000000–00FFFF All sectors (1–2)

The WRSR instruction also allows the user to enable or disable the WP pin through the
use of the WPEN bit. Hardware write protection is enabled when the WP pin is low and
the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is
high or the WPEN bit is “0.” When the device is hardware write protected, writes to the
status register, including the block protect bit and the WPEN bit, and the locked-out sec-
tors in the memory array are disabled. The WRSR instruction is self-timed to
automatically erase and program BP0 and WPEN bits. In order to write the status regis-
ter, the device must first be write enabled via the WREN instruction. Then, the
instruction and data for the two bits are entered. During the internal write cycle, all
instructions will be ignored except RDSR instructions. The AT25F512A will automatically
return to write disable state at the completion of the WRSR cycle.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0” as long
as the WP pin is held low.

8 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

Table 9. WPEN Operation

WPEN WP WEN ProtectedBlocks UnprotectedBlocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writeable Writeable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writeable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writeable Writeable

READ (READ): Reading the AT25F512A via the SO pin requires the following
sequence. After the CS line is pulled low to select a device, the Read instruction is
transmitted via the SI line followed by the three-byte address to be read (see Table 10
on page 10). Upon completion, any data on the SI line will be ignored. The data (D7–D0)
at the specified address is then shifted out onto the SO line. If only one byte is to be
read, the CS line should be driven high after the data comes out. The Read instruction
can be continued since the byte address is automatically incremented and data will con-
tinue to be shifted out. When the highest address is reached, the address counter will
roll over to the lowest address, allowing the entire memory to be read in one continuous
READ instruction.
PROGRAM (PROGRAM): In order to program the AT25F512A, two separate instruc-
tions must be executed. First, the CS line is pulled low to select the device, the device
must be write enabled via the WREN instruction. Then, the Program instruction can be
executed.
The Program instruction requires the following sequence. After the CS line is pulled low
to select the device, the PROGRAM instruction is transmitted via the SI line followed by
the three-byte address and the data (D7–D0) to be programmed (see Table 10 on page
10). Programming will start after the CS pin is brought high. The low-to-high transition of
the CS pin must occur during the SCK low time immediately after clocking in the D0
(LSB) data bit (assuming mode 0 operation). During an internal self-timed programming
cycle, all commands will be ignored except the RDSR instruction.
The Ready/Busy status of the device can be determined by initiating a RDSR instruc-
tion. If Bit 0 = “1”, the program cycle is still in progress. If Bit 0 = “0”, the program cycle
has ended. Only the RDSR instruction is enabled during the program cycle.
A single PROGRAM instruction programs 1 to 128 consecutive bytes within a page if it
is not write protected. The starting byte could be anywhere within the page. When the
end of the page is reached, the address will wrap around to the beginning of the same
page. If the data to be programmed are less than a full page, the data of all other bytes
on the same page will remain unchanged. If more than 128 bytes of data are provided,
the address counter will roll over on the same page and the previous data provided will
be replaced. The same byte cannot be reprogrammed without erasing the whole sector
first. The AT25F512A will automatically return to the write disable state at the completion
of the program cycle.
Note: If the device is not write enabled (WREN), the device will ignore the WRITE instruction
and will return to the standby state when CS is brought high. A new CS falling edge is
required to re-initiate the serial communication.

9
3345E–FLASH–8/05
 Table 10. Address Key
Address AT25F512A
AN A15 – A0
Don’t Care Bits A23 – A16

SECTOR ERASE (SECTOR ERASE): Before a byte can be reprogrammed, the sector
containing the byte must be erased. In order to erase the AT25F512A, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then the SECTOR ERASE instruction can be executed.

Table 11. Sector Addresses

Sector Address AT25F512A Sector
000000 to 007FFF Sector 1
008000 to 00FFFF Sector 2

The Sector Erase instruction erases every byte in the selected sector if the device is not
locked out. Sector address is automatically determined if any address within the sector
is selected. The SECTOR ERASE instruction is internally controlled; it will automatically
be timed to completion. During this time, all commands will be ignored except RDSR
instruction. The AT25F512A will automatically return to the WRDI state at the comple-
tion of the sector erase cycle.
CHIP ERASE (CHIP ERASE): As an alternative to the Sector Erase, the Chip Erase
instruction will erase every byte in both sectors if the device is not locked out. First, the
device must be write enabled via the WREN instruction. Then the Chip Erase instruction
can be executed. The Chip Erase instruction is internally controlled; it will automatically
be timed to completion. The chip erase cycle time typically is 2 seconds. During the
internal erase cycle, all instructions will be ignored except RDSR. The AT25F512A will
automatically return to the WRDI state at the completion of the chip erase cycle.

10 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

Timing Diagrams (for SPI Mode 0 (0, 0))

Figure 3. Synchronous Data Timing
t CS
VIH
CS
VIL
t CSS t CSH

VIH
SCK t WH t WL
VIL

t SU tH

VIH
SI VALID IN
VIL

tV t HO t DIS

VOH
SO HI-Z HI-Z

VOL

Figure 4. WREN Timing

CS

SCK

SI WREN OP-CODE

HI-Z
SO

Figure 5. WRDI Timing

CS

SCK

SI WRDI OP-CODE

HI-Z
SO

11
3345E–FLASH–8/05
Figure 6. RDSR Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

SI INSTRUCTION

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

Figure 7. WRSR Timing

cs

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

DATA IN

SI INSTRUCTION 7 6 5 4 3 2 1 0

SO
HIGH IMPEDANCE

Figure 8. READ Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39
SCK

3-BYTE ADDRESS
SI INSTRUCTION 23 22 21 ... 3 2 1 0

HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0

12 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

Figure 9. PROGRAM Timing

CS

1051
1052
1053
1054
1055
0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34
SCK

1st BYTE DATA-IN 128th BYTE DATA-IN

3-BYTE ADDRESS
SI INSTRUCTION 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0

HIGH IMPEDANCE
SO

Figure 10. HOLD Timing

CS

tCD tCD

SCK

tHD

tHD
HOLD

tHZ

SO
tLZ

Figure 11. SECTOR ERASE Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31

SCK

INSTRUCTION 3-BYTE ADDRESS

SI 0 1 0 1 X 0 1 0 23 22 21 ... 3 2 1 0

HIGH IMPEDANCE
SO

X = Don’t Care bit

13
3345E–FLASH–8/05
Figure 12. CHIP ERASE Timing

cs

0 1 2 3 4 5 6 7
SCK

SI 0 1 1 0 X 0 1 0

HIGH IMPEDANCE
SO

X = Don’t Care bit

Figure 13. RDID Timing

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

SI 0 0 0 1 X 1 0 1

DATA OUT
SO HIGH IMPEDANCE
MANUFACTURER 7 6 5 4 3 2 1 0
CODE (ATMEL)
DEVICE CODE

14 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

Ordering Information
Ordering Code Package Operation Range
AT25F512AN-10SU-2.7 8S1 Lead-free/Halogen-free Industrial
AT25F512AY4-10YU-2.7 8Y4 (−40 to 85°C)

Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
−2.7 Low-voltage (2.7 to 3.6V)

15
3345E–FLASH–8/05
Packaging Information

8S1 – SOIC

E E1

N L

∅
Top View
End View
e B
COMMON DIMENSIONS
A
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 A 1.35 – 1.75
A1 0.10 – 0.25
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
D
E1 3.81 – 3.99
E 5.79 – 6.20
Side View e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚

Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

10/7/03
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Colorado Springs, CO 80906 8S1 B
R
Small Outline (JEDEC SOIC)

16 AT25F512A [Preliminary]
3345E–FLASH–8/05
 AT25F512A [Preliminary]

8Y4 – SAP

PIN 1 INDEX AREA

A

PIN 1 ID

D1
D
E1

E A1
b e
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 0.90
A1 0.00 – 0.05
D 5.80 6.00 6.20
E 4.70 4.90 5.10
D1 2.85 3.00 3.15
E1 2.85 3.00 3.15
b 0.35 0.40 0.45
e 1.27 TYP
e1 3.81 REF
L 0.50 0.60 0.70

5/24/04
TITLE DRAWING NO. REV.
1150 E. Cheyenne Mtn. Blvd. 8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package
Colorado Springs, CO 80906 8Y4 A
R
(SAP) Y4

17
3345E–FLASH–8/05
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3345E–FLASH–8/05