background

This book has two major objectives; to teach procedures for the design of soft-
ware systems and to provide a basts for judgement in the design of software. To
facilitate our task, we have taken specific examples from systems programs. We
discuss the design and implementation of the major system components.
What is systems programming? You may visualize a computer as some sort of
.
beast that obeys all commands It has been said that computers are basically
people made out of metal or, conversely , people are computers made out of
flesh and blood . However, once we get close to computers, we see that they are
basically machines that follow very specific and primitive instructions.
In the early days of computers, people communicated with them by on and
off switches denoting primitive instructions. Soon people wanted to give more
complex instructions. For example, they wanted to be able to say X 30 + Y\
=
=
given that Y 10, what is XI Present day computers cannot understand such
language without the aid of systems programs. Systems programs (e.g,, com -
pilers, loaders, macro processors, operating systems) were developed to make
computers better adapted to the needs of their users. Further, people wanted
more assistance in the mechanics of preparing their programs.
-
Compilers are systems programs that accept people like languages and translate
them into machine language. Loaders are systems programs that prepare machine
language programs for execution. Macro processors allow programmers to use
abbreviations. Operating systems and file systems allow flexible storing and
rctriml of information (Fig , 1,1).
There arc over 100,000 computers in use now in virtually every application.
The productivity of each computer is heavily dependent upon the effectiveness,
effiiicncy , and sophistication of the systems programs.
In this chapter we introduce some terminology and outline machine structure
and ( he basic tasks of an operating system.
i
3 MACHINE STRUCTURE

People

Application programming

Compilers
Macro
Assemblers processors
Searching
Loaders Tent editors Debugging aids
and sorting
Memory Device
I / O programs Fite systems Scheduler Libraries management management

FIGUR E 1.1 Foundations of systems programming

1.1 MACHINE STRUCTURE

We begin by sketching the general hardware organization of a computer system
(Fig. 1.2).

Memory

l;0 I /O CPU CPU

processor processor
z \
Teletype
Card Printer
| read/punch
Disk
or drum
FIGURE 1.2 General hardware organization of a computer system

.
Memory is the device where information is stored Processors are the devices
.
thaHJperate on this information One may view information as being stored in
the form of ones and zeros. Each one or zero is a separate binary digit called a
bit . Bits are typically grouped in units that are called words, characters, or bytes.
Memory locations arc specified by addresses, where each address identifies a
specific byte , word , or character.

ME
BACKGROUND 3

The contents of a word may be interpreted a data (values to be operated on)

or instructions (operations to be performed). A processor is a device that per
forms a sequence of operations specified by instructions in memory , A program
-
(or procedure) is a sequence of instructions.
Memory may be thought of as mailboxes containing groups of ones and zeros.
Below we depict a series of memory locations whose addresses are 10,030
through 10,002.

Add feu Contents

10,000 0000 0000 0000 0001
10.001 OOI 1 0000 0000 0000
10,002 0000 0000 0000 0100

An IBM 1130 processor treating location 10,001 as an instruction would inter -

pret its contents as a "halt" instruction. Treating the same location as numerical
data , the processor would interpret its contents as the binary number 001 i 0000
0000 0000 (decimal 12,288). Thus instructions and data share the same storage
medium.
Information in memory is coded into groups of bits that may be interpreted
as characters, instructions, or numbers. A code is a set of rules for interpreting
groups of bits, e.g., codes for representation of decimal digits (BCD), for char
acters (EBCDIC, or ASGI), or for instructions ( specific processor operation
-
codes). We have depicted two types of processors: Input(Output (\{0 ) processors
and Central Processing Units (CPUs). The I/O processors are concerned with the
transfer of data between memory and peripheral devices such as disks, drums,
printers, and typewriters. The CPUs are concerned with manipulations of data
Stored in memory. The I /O processors execute I/O instructions that are stored in
memory ; they are generally activated by a command from ihe CPU. Typically,
this consists of an "execute I/O" instruction whose argument is the address of
the start of the I/ O program. The CPU interprets this instruction and passes the
argument to the I /O processor (commonly called I/O channels).
The I /O instruction set may be entirely different from that of the CPU and
may be executed asynchronously ( simultaneously) with CPU operation. Asyn
chronous operation of 1/0 channels and CPUs was one of the earliest forms of
-
multiprocessing . Multiprocessing means having more than one processor oper
ating on the same memory simultaneously .
-
Since Instructions, like data , are stored in memory and can be seated as data,
—
by changing the bit configuration of an instruction adding a number to it we
. —
may change it to a different instruction Procedures that modify themselves are
4 EVOLUTION OF THE COMPONENTS OF A PROGRAMMING SYSTEM

called impure procedures. Writing such procedures is poor programming practice.

Other programmers find them difficult to read , and moreover they cannot be
shared by multiple processors. Each processor executing an impure procedure
.
modifies its contents Another processor attempting to execute the same pro-
cedure may encounter different instructions or data. Thus, impure procedures
.
are not readily reusable. A pure procedure does not modify itself To ensure that
the instructions are the same each time a program is used , pure procedure..
-
{re entrant code) are employed .

1.2 EVOLUTION OF THE COMPONENTS OF A PROGRAMMING SYSTEM

1.2.1 Assembler*
Let us review some aspects of the development of t ' e components of a program
ming system.
-
At one time , the computer programmer had at his disposal a basic machine
.
that interpreted , through hardware, certain fundamental instructions He would
program this computer by writing a scries of ones and zeros (machine language ),
place them into the memory of the machine, and press a button, whereupon the
.
computer would start to interpret them as instructions
Programmers found it difficult to write or read programs in machine language.
In their quest for a more convenient language they began to use a mnemonic
( symbol) for each machine instruction , which they would subsequently translate
.
into machine language Such a mnemonic machine language is now called ait
.
assembly language Programs known as assemblers were written to automate the
translation of assembly language imo machine language. The input to an as -
sembler program is called the source program', the output is a machine language
translation { object program ) .
1.2. 2 Loader*
Once the assembler produces an object program, that program must be placed
imo memory and executed . It is the purpose of the loader to assure that object
programs are r.hced in memory in an executable form .
The assemble! could place the object program directly in memory and transfer
consol to it , thereby erasing il e machine language program to be executed .
BACKGROUND 5

However, this would waste core1 by leaving the assembler in memory wliilc Urn
user's program was being executed. Also the programmer would have to retrans
late his program with each execution , thus wasting translation time. To overcome
-
the problems of wasted translation time and wasted memory , systems program
mers developed another component , called the loader . -
A loader is a program that places programs into memory and prepares them for
execution. In a simple loading scheme, the assembler outputs the machine
language translation of a program on a secondary storage device and a loader is
placed in core. The loader places into memory the machine language version of
the usefs program and transfers control to it. Since the loader program is much
smaller than the assembler , this makes more core available to the user's program.
The realization that many users were writing virtually the same programs led
to the development of “ready -made” programs (packages). These packages were
written by the computer manufacturers or the users. As the programmer became
-
more sophisticated , he wanted to mix and combine ready made programs with
his own. In response to this demand , a facility was provided whereby the user
could write a main program that used several other programs or subroutines. A
subroutine is a body of computer instructions designed to be used by other
routines to accomplish a task . There are two types of subroutines: closed and
open subroutines. An open subroutine or macro definition is one whose code is
inserted into the main program ( flow continues). Thus if the same open sub-
routine were called four times, it would appear in four different places in the
calling program. A dosed subroutine can be stored outside the main routine,
and control transfers to the subroutine. Associated with the closed subroutine
are two tasks the main program must perform: transfer of control and transfer
of data.
Initially , closed subroutines had to be loaded into memory at a specific ad
dress. For example, if a user wished to employ a square root subroutine, he
-
would have to write his main program so that it would transfer to the location
assigned to the square root routine ( SQRT) . His program and the subroutine
would be assembled together . If a second user wished to use the same subroutine,
he also would assemble it along with his own program, and the complete machine
language translation would be loaded into memory. An example of core alloca
tion under this inflexible loading scheme is depicted in Figure 1.3, where core is
-
depicted as a linear array of locations with the program areas shaded.

1 Main memory is typically implemented as magnetic cores ; hence me and core are used
synonymously .

rm
6 EVOLUTION OF THE COMPONENTS OF A PROGRAMMING SYSTEM

Locations

J v:
->
SORT -v ’
'V
* SQRTc . ..
^:•: : i- . .-: ^ : ^
' WAV VIS'
*
• y -
1
, v . *.
^
:<1
•V
^ ' 2< *
“•n
Program
i

fcf
Program 1 ; -. Vv - '

FIGURE \ 2 Example core allocation for absolute loading

Nolo that program 1 has “holes” in core. Program 2 overlays and thereby
destroys part of the SQRT subroutine.
Programmers wished to use subroutines that referred to each other symbolical-
ly and did not want to be concerned with the address of parts of their programs.
They expected the computer system to assign locations to their subroutines and
to substitute addresses for their symbolic references.
Systems programmers noted that it would be more efficient if subroutines
could be translated into an object form that the Loader could “relocate” directly
behind the user 's program. The task of adjusting programs so they may be placed
in arbitrary core locations is called relocation , Relocating loaders perform four
functions:
1 . Allocate space in memory for the programs ( allocation )
2 . Resolve symbolic references between object decks { linking)
3 . Adjust ail address-dependent locations, such as address constants, to cor *
respond to the allocated space { relocation )
4 . Physically place the machine instructions and data into memory ( loading ) .
The various types of loaders that we will discuss ("compile -and-go ” absolute,
rdoca ing, direct-linking, dynamic-loading, and dynamic-linking) differ primarily
in the manner in which these four basic functions arc accomplished.
The period of execution of a user 's program is called execution time. The
period or translating a user’s source program is called assembly or compile time.
Load time refers to the period of loading and preparing an object program for
execution.

1.2,3 Macros
To relieve programmers of the need to repeat identical parts of their program,

ana
BACKGROUND 7

operating systems provide a macro processing facility , which permits the pro-
grammer to define an abbreviation for a part of his program and to use the ab
breviation in his program . The macro processor treats the identical parts of the
-
program defined by the abbreviation as a macro definition and saves the defini
tion . The macro processor substitutes the definition for ali occurrences of the
-
abbreviation (macro call) in the program.
In addition to helping programmers abbreviate their programs, macro facilities
have been used as general text handlers and for specializing operating systems to
.
individual computer installations In specializing operating systems ( systems
generation) , the entire operating system is written as a series of macro defini*
tions To specialize the operating system , a scries of macro calls are written.
*

These are processed by the macro processor by substituting the appropriate

definitions, thereby producing all the programs for an operating system *

1.2 4 Compilers
*

As the user’s problems became more categorized into areas such as scientific,
business, and statistical problems, specialized languages ( high level languages )
were developed that allowed the user to express certain problems concisely and

— —
easily . These high level languages examples are FORTRAN , COBOL, ALGOL,
and PL/J are processed by compilers and interpreters. A compiler is a ptogram
that accepts a program written in a high level language and produces an object
program . An interpreter is a program that appears to execute a source program
.is if it were machine language. The same name ( FORTRAN , COBOL, etc.) is
often used to designate bulh a compiler and its associated language.
Modern compilers must be able to provide the complex facilities that pro
grammers are now demanding. The compiler must furnish complex accessing
-
methods for pointer variables and data structures used in languages like PL / I ,
COBOL, and ALGOL 68 Modem compilers must interact closely with the oper
* -
ating system to handle statements concerning the hardware interrupts of a com-
puter (e.g. conditional statements in PL /1).

1.2,5 Formal Systems

A formal system is an tmintcrpreied calculus. It consists of an alphabet , a set of
words called axioms, and a finite set of relations called rules of inference Ex
* -
amples of formal systems are: set theory , boolean algebra, Fost systems, and
Backus Normal Form , Formal systems are becoming important in the design ,
implementation , and study of programming languages. Specifically , they can be

na
8 EVOLUTION OP OPERATING SYSTEM
*
used to specify the syntax ( form) and the semantics (meaning) of programming
languages . They have been used in syntax-directed compilation, compiler verifica -
tion , and complexity studies of languages.

1.3 EVOLUTION OF OPERATING SYSTEMS

Just a few years ago a FORTRAN programmer would approach the computer
with liis source deck in his left hand and a green deck of cards that would be a
FORTRAN compiler in his right hand . He would:
1 . Place the FORTRAN compiler (green deck ) in the card hopper and press
the load button. The computer would load the FORTRAN compiler,
2. Place his source language deck into the card hopper. The FORTRAN com-
piler would proceed to translate it into a machine language deck , which
was punched onto red cards.
3 . Reach into the card library for a pink deck of cards marked "loader ,” and
place them in the card hopper . The computer would load the loader into
its memory.
4 . Place his newly translated object deck in the card hopper. The loader
would load it Into the machine.
5 . Place in the card hopper the decks of any subroutines which his program
called. The loader would load these subroutines.
6. Finally , the loader would transfer execution to the user’s program, which
might require the reading of data cards.
This system of multicolored decks was somewhat unsatisfactory, and there was
strong motivation for moving to a more flexible system. One reason was that
valuable computer Lime was being wasted as the machine stood idle during card-
handling activities and between jobs. ( A job is a unit of specified work , e g., an
,

assembly of a program.) To eliminate this waste, the facility to batch jobs was
provided , permit ling a number of jobs to be placed together into the card hopper
to be read. A batch operating system performed the task of batching jobs . For
example the batch system would perform steps I through 6 above retrieving the
FORTRAN compiler and loader from secondary storage.
As the demands for computer time , memory, devices, and files increased, the
efficient management of these resources became more critical. In Chapter 9 we
discuss various methods of managing them. These resources are valuable, and in-
efficient management of them can be costly. The management of each resource
has evolved as tlie cost and sophistication of its use increased.
In simple batched systems, the memory resource was allocated totally to a
BACKGROUND ft

single program. Thus, if a program did not need the entire memory, a portion of
that resource was wasted. Multiprogramming operating sterns with partitioned
^
core memory were developed to circumvent this problem. Multiprogramming al -
lows multiple programs to reside in separate areas of core at the same time. Pro-
gran: s were given a fixed portion of core ( Multiprogramming with Fixed Tasks
-
(MFf )) or a varying size portion of core ( Multiprogramming with Variable Tasks
(MVT)).
Often in such partitioned memory systems some portion could not be used
.
since it was too small to contain a program The problem of “ho lessor unused
portions of core is called fragmentation. Fragmentation has been minimized by
the technique of relocatable partitions (Burroughs 6S00) and by paging (XDS
940, HIS 645). Relocatable partitioned core allows the unused portions to be
condensed into one continuous part of core .
Paging is a method of memory allocation by which the program is subdivided
into equal portions or pages, and core is subdivided into equal portions or blocks.
The pages are loaded into blocks.
There are two paging techniques: simple and demand. In simple paging all the
pages of a program must be in core for execution. In demand paging a program
can be executed without all fiages being in core , i.e., pages are fetched into core
as they are needed (demanded).
The reader will recall from section LI that a system with several processors is
.
termed a multiprocessing system The traffic controller coordinates the proces -
sors and the processes. The resource of processor time is allocated by a program
known as the scheduler. The processor concerned with I/O is referred to as the
IjO processort and programming this processor is called //0 programming.
The resource of files of information is allocated by the file system , A segment
.
is a group of information that a user wishes to treat as an entity Files are seg -
ments. There are two types of files: ( l) directories and (2) data or programs.
Directories contain the locations of other files. In a hierarchical file system,
directories may point to other directories, which in turn may point to directories
or files.
Timesharing is one method of allocating processor time. It is typically char -
-
acterized by interactive processing and time slicing of the CPU’s time to allow
quick response to each user.
A virtual memory ( name space, address space) consists of those addresses that
may be generated by a processor during execution of a computation The mem.
ory space consists of the set of addresses that correspond to physical memory
-
-
locations. The technique of segmentation provides a large nam pace and a good
10 OPERATING SYSTEM USER VIEWPOINT

protection mechanism. Protection and sharing are methods of allowing controlled

access to segments .

14 OPERATING SYSTEM USER VIEWPOINT: FUNCTIONS

From the user's point of view , the purpose of an operating system (monitor) is
to assist him in the mechanics of solving problems. Specifically , the following
functions are performed by the system:
1. Job sequencing, scheduling, and traffic controller operation
2. Input /output programming
3. Protecting itself from the user ; protecting the user from other users
4. Secondary storage management
5. Error handling
Consider the situation in which one user has a job that takes four hours, and
another user has a job that takes four seconds. If both jobs were submitted
simultaneously, it would seem to be more appropriate for the four-second user
to have his run go fust . Based on considerations such as this, job scheduling is
automatically performed by the operating system. If it is possible to do input
and output while simultaneously executing a program , as is the case with many
computer systems, all these functions are scheduled by the traffic controller.
As we have said , the I/O channel may be thought of as a separate computer
with its own specialized set of instructions. Most users do not want to learn how
to program it ( in many cases quite a complicated task). The user would like to
simply say in his program, “Read,*' causing the monitor system to supply a pro
gram to the I /O channel for execution . Such a facility is provided by operating
-
systems. In many cases the program supplied to the I/O channel consists of a
sequence of closely interwoven interrupt routines that handle the situation in
tills way: “Hey , Mr. I /O Channel, did you receive that character?” “Yes, I re
ceived it ,” “Are you sure you received it?” “Yes, Tm sure.” “Okay , I’ll send
-
another one.” “ Fine, send it .” “You’re sure you want me to send another one?"
“Smfit!”
An extremely important function of an operating system is to protect the user
-
from being hurt , either maliciously or accidentally , by other users; that is , pro
tect him when other users are executing or changing their programs , files, or data
bases. The operating system must insure inviolability. As well as protecting
users from each other, the operating system must also protect itself from users
who, whether maliciously or accidentally , might “crash” the system.
Students are great challengers of protection mechanisms. When the systems
 2
machine structure, machine
language , and assembly language

The purpose of this chapter is to discuss machine structure , machine language ,

and assembly language.
We have taken examples from the IBM Systems/360 and 370, 1 Our purpose is
not to teach specific assembly languages, and we present only enough material to
illustrate the design of assemblers (and later the design of compilers). The in -
troduction to 370 assembly language afforded by our discussion should be sup -
-
plemented by further reading (see Chapter 10 (References) machine structure).
We have written this section primarily for two classes of people: those who
know assembly language programming well and want to become somewhat
familiar with the 370; and those who have not programmed in any assembly
language and who may use this chapter as an introduction to the manuals. The
approach and examples can be easily translated to other machines.

21 GENERAL MACHINE STRUCTURE

Almost all conventional modem computers are based upon the "stored program
computer” concept , generally credited to the mat hematic Ian John von Neumann
-
(1903 1957), Figure 2.1 illustrates the structure of the CPU for a typical von
Neumann machine, such as the IBM System /360 .
The CPU consists of an instruction interpreter, a location counter , an instruc
.
tion register and various working registers and general registers The instruction
-
interpreter is a group of electrical circuits ( hardware )t that performs the intent
of instructions fetched from memory. The location Counter (LC), also called

i
•Pit IBM Syitoti /360 (or Just 360) is th* name of a series of IBM computers In production
.
since 1964, all of which have compatible Instruction sets and manuals The IBM 370, a re -
.
vised version of the 360, was introduced in 1970 The 370 ft compatible with the 360.
21
72 GENERAL MACHINE STRUCTURE

Other t
I / O channels 1W x.
i if any I
' s, 0
1
Memory 2
controller 3
I/O channel
^ Memory Address
Register ( MARI
Memory Buffer
Register ( MBR )

I
-
1

t Working
1
Location Counter ( IC> Registers
!
i
i
^ IWR )
I
Instruction
i
Instruction Register OR )
^ Data
£
Instruction
interpreter

i General
1
Registers
( GR )
L .CPU J

r*
7.1
!i Other CPUs
t if any i

FIGURE 2.1 General machine structure

Program Counter (PC) or Instruction Counter (1C), is a hardware memory device

which denotes the location of the current instruction being executed. A copy of
the current instruction is stored in the Instruction Register ( IR ) . The working
registers are memory devices that serve as "scratch pads” foT the instruction
interpreter , while the general registers are used by the programmer as storage
locations and for special functions.
The primary interface between the memory and the CPU is via the memory
address register and the memory buffer register. The Memory Address Register
(MAR ) contains the address of the memory location that is to be read from or
stored into. The Memory Buffer Register ( MBR ) contains a copy of the designat
ed memory location specified by the MAR after a "read / ’ or the new contents
-
of the memory location prior to a "write ” The memory controller is harawaie
*

TIE
MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 23

that transfers data between the MBR and the core memory location the address
of which is in the MAR.
The 1(0 channels may be thought of as separate computers which interpret
special instructions for inputting and outputting information from the memory.
To illustrate how these components of the machine structure interact , let us
- -
consider a simple computer (SC 6253). The SC 6251 has four general registers,
designated 00, 01, 10, and 11 in binary rotation. The basic instruction format is
as follows;

Operation Register Memory

code number location
{op} treg) (eddrl

For example, the instruction

ADD 2,176

would cause the data stored in memory location 176 to be added to the curren;
.
contents of general register 2 The resulting sum would be left as the new
contents of register 2, The micro -flowchart in Figure 2.2 illustrates the sequence
of hardware operations performed within the instruction interpreter to execute
an Instruction.
Although the specific details vary from computer to computer, this example cf
machine structure is representative of all conventional machines.

2.1.1 General Approach to a New Machine

Outlined in this section is an approach that may be taken to become familiar
with a new machine. Jt consists of finding answers to a series of questions that
we ask if we wish to program the machine ,
Wc first list these questions and then answer them for the IBM 360 and 370.
In sec ' ion 9.1 we will ask these same questions regarding I /O channels (which
may be considered as separate computers).
L MEMORY
What is the memory 's basic unit , size, and addressing scheme?
2. REGISTERS
How many registers are there? What are I heir size, function , and interrelationship?

na
24 GENERAL MACHINE STRUCTURE

V
MAR <= 1C

MBR <- M( MAR ) ( Read instruction from memory )

|R <=
I MBR
( Put instruction in instruction
register)

c Test instruction
type )
J
""
ADD SUBTRACT I MULTIPLY | BRANCH Other

V
V
^ ^
OP codes

MAR <= IR ( addr )

MBR <= M ( MAR ) ( Read data from memory )

I ( Copy designated general register

WR <= B ( l R ( rtg> ) into working register )

\/

WR <= WR +MBR ( Perform addition )

V
( Leave resulting sum in general register)
RtlR (reg) ) <= WR

V
( Increase Instruction counter to location
1C <= IC+1 of next instruction )

FIGURE 22. Example micro flowchart for ADD instruction

npy righted material

MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 25

.
3 DATA
What types of data can be handled by the computer ? Can it handle characters,
numbers, logical data? How is this data stored?
4 . INSTRUCTIONS
What are the classes of instructions on the machine? Are there arithmetic instruc
tions, logical instructions, symbol-manipulation instructions? What are their
-
formats? How are they stored in memory?
.
5 SPECIAL FEATURES
What is the interrupt structure of (he machine? What sort of protection mecha
nism is available to the user?
-
.
2.1 2 Machine Structure
— 360 and 370
In this section we will answer these questions in the context of the IBM 360.
The material is equally applicable to the 370 .
1. MEMORY
—
The basic unit of memory in the 360 is a byte eight bits of information. That
is, each addressable position in memory can contain eight bits of information.
There are facilities to operate on contiguous bytes in basic units. The basic units
are as follows:

Unit of memory Bym Length in bftt

Bytft 1 8
Halfword 2 1S
Word 4 32
Doubleword 8 64

A unit of memory consisting of four bits is sometimes referred to as a nibbk

*
The size of the 360 memory is up to 22 bytes (about sixteen million) .
The addressing on the 360 memory may consist of three components. Specifi -
cally, the value of an address equals the value of an offset , plus the contents of a
base register , plus the contents of an index register. We will give examples of this
addressing later.
In general, operations on units of memory are specified by the low-order byte
address. For example, when addressing a word (four bytes) the address of ' he
word is that of the low order byte.
2. REGISTERS
-
The 360 has 16 general purpose registers consisting of 32 bits each. In addition
there are 4 floating-point registers consisting of 64 bits each. It has a 64- bit

na
26 GENERAL MACHINE STRUCTURE

Program Status Word (PSW) that contains the value of the location counter,
protection information , and interrupt status.
-
The general purpose registers may be used for various arithmetic and logical
.
operations and as base registers When the programmer uses them in arithmetic
or logical operations , he thinks of these registers as scratch pads to which num
bers are added , subtracted , compared , and so forth. When used as base registers,
-
they aid in the formation of the address. Take for example the instruction

Index register
A
f
*$
1,901 ( 2, 15}
Offset Bass
register

It is interpreted as an add instruction. A number is lobe added to the contents

of register 1.
The location of the number is 901 { offset ) plus the contents of register 2
{index ) plus the contents of register 15 ( base ). That is, if those three numbers
were added together , the result would be the address of the memory location
whose contents we wish to add to the contents of register 1.
One may ask why such complexity in the formation of addressing is necessary.
The motivation is twofold . First , a base register aids in the process of relocation
of a program . As we will see , an entire program may be moved from one series
of locations to another by changing the contents of a base register.2 A major
motivation for employing base registers, however , is to promote efficient ad -
dressing of core. For example , in order to address all possible core locations (!6
million) in the 360 without the use of a base register , we w ould need 24 bits for
every address. By way of illustration , if the preceding add instruction were
formed in core as depicted in the following diagram , we would need a total of
40 bits to store it : 8 bits for the op code, 4 bits to specify one of 16 possible
registers to which the number is added , an additional 4 bits to specify one of
16 possible index registers , and lastly , 24 bits to specify the address of the num-
ber we wish to add

2 Uasc registers do not completelysolve the problem of relocation. The difficult problem of
address constants must also be resolved . An address constant is a feature by which a pro-
grammer may specify that a ccriain location In memory contains an address of a specified
memory locjtion.
MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 21

Arg Index
Op cod* reg Address
rcg
8 bits 4 bits 4 bits 24 bits Total; 40

If we use a base register , we can store the instruction in the following format,
We could specify any one of 16 possible registers as the base register, using 4 bits,
and employ an additional 12 for an offset. The total number of bits for an add
instruction would be 32, a savings of 8 bits per address reference.

Arg Index Base

Op code Offset
rog reg

8 bits 4 bits 4 bits 4 bits 12 bits Total ; 32

The disadvantages of this shorter form are the overhead associated with the
formation of the address during execution and the fact that the offset , which is
12 bits long, can only specify a number from 0 to 4,095. Thus, it may be dif
ficult to “reach ' the data. That is, without using an index register and without
1
-
changing the contents of the base register , the core location we wish to address
cannot be any further than 4,095 locations away from the core location to
which the base register is pointing.
3, DATA
The 360 may store several different types of data as is depicted in Figure 2.3.
That is , groups of bits stored in memory are interpreted by a 360 processor in
several ways. If a 360 interprets the contents of two bytes as an integer ( Fig.
2.3a), it interprets the First bit as a sign and the remaining 15 as a binary number
(e.g., OQOQ 0010 0001 1101 is interpreted as the binary number equivalent to
^
the decimal number + 541). If a 360 interprets the contents of two bytes as a
packed decimal ( Fig, 2.3c), it would interpret the fust byte as two BCD coded
digits, the First four bits of the second byte as a BCD digit , and the last four as
..
a sign (e g , 0000 0010 00 Oj 1J 0J is interpreted as the decimal number 031).
0 2 1 Sign
-
All data and instructions am physically stored as sequences of binary ones and
zeros. Thus, a 16 bit fixed point halfword with decimal value + 300 would be
- -
3 S _‘t
' AfpcnJi A for binary to decanal conversions.
*

riE
38
*.
GENERA MACHINE STRUCTURE

a ) Short form
fixed point
s
01 15
Sign bit
t Full word
b) Long form
fixed point
S Integer ]
01 31
1 to 16 byte
tt * <4 bits)
cf Decimal packed D D D S

0 34 78
it
True form binary- coded
Zone code ( 4 bits ) decimal digit (4 bits) 1
it
d) Unpacked Z 0 z D s D
U
0 34 78 M 12 1516
*C Sign
(4 bits)
e] Short form
floating point S C F

0 1 7a 31
Fraction
"$
Sia - haracteristic
\1/
fj Long form
\ f
floating point S C F

01 78
it 63
Character codes 46 bits)
i n
9} Logical
( characters )
ch ch ch

0 1 3
n
15 1 to 256 bytes

FIGURE 7 3 Data formats for iht jyjtcm / 360 and 370

stored tn binary us ‘0000 0001 0010 1100’* For convenience, binary number,
arc usually written in the Itexadecimal { base ] 6) number system rather than the
binary (base 2) number system. The hexadecimal digits are shown in Figure 2.4.
Note that every hexadecimal digit can be replaced by exactly four binary digits
and vice veisa. Thus when we have the number +300 in decimal, which equals

B' OOOO 0001 qoip 11001 in binary

X - 6 1 2 C in hexadecimal

TIE
MACH I ME IT RUCTUE E, MACHINE LANGUAGE AND ASSEMBLY LANQU AGE 29

Hwm/tcimat Binary Dtckmt

0 »XM 0
i 0001 t
2 0010 2
3 0011 3
4 0100 4
5 0101 6
6 0110 6
7 0111 7
8 1000 a
9 1001 9
A 1010 10
B 1011 11
c 1100 12
D 1101 13
E 1110 14
F 1111 IB
HGURE 24 Hexadecimal-binary -decimal conversion

The prefixes X and B indicate mode of representation (hexadecimal , binary).

-
Fixed point numbers may be stored in either a halfword or a fullword (Figs .
23a and 23b) .
The 360 allows the storage of numbers In decimal form (Figs, 23c and 2.3d) .
That is, numbers may be stored not as binary numbers but in a format closely
approximating the decimal representation. For example, the number 12 cou;d
appear in one byte where the first four bits would contain a decimal 1 (0001)
and the second four bits would contain a decimal 2 (0010). Decimal forms are
.
useful in business data processing

.
-
The 360 allows floating point numbers, logical data, and character strings
(Fig 23g) to be represented in memory as depicted in Figure 23 .
.
There are instructions to operate on all these types of data
4. INSTRUCTIONS
The 360 has arithmetic, logical, control or Iransier, and special interrupt
instructions.
The formats of the 360 instructions are depicted in Figure 2.5 .
These five types of instructions differ basically in the types of operands they
use.
Register operands refer to data stored in one of the 16 general registers (32 bits

-
-
long), which are addressed by a four bit field in the instruction. Since registers
are usually constructed of high speed circuitry, they provide faster access to data
than does core storage.
For example, the instruction Add register 3, 4
3Q GENERAL MACHINE STRUCTURE

Format
r: 6 bytes
**
d bytes

r: 2 bytes
Register operands
Rft 1 2

OP R1 R2

0 73 11 12 15
Register
operand 1 Sto rage operand 2
IrX

OP R1 X2 E32 D2

0 7a 11 12 15 IS 19 20 31

Register operands Storage operand

RS 1 3 2

OP Rt R3 m D2

0 78 11 12 1518 1920 31
Immediate
Operand Storage operand
SI 2 1

OP 12 61 D1

0 7 3 15 16 1920 31

Length 1 Storage operands 2

SS *

OP L B1 D1 B2 D2

0 78 1 G 16 1920 31 32 35 36 4/

Mnemonics used '

OP *v operation code
HI contents of general register used as operand
Xi -tontents of general register used as inefe
8i contents of general register used as base *
Di displacement
li immediate data
L Operand length

EICUR £ 24» Basic 360 instruction formats

MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 31

2 bytes >
OP R1 R2
0001 1010 0011 0100 ( RR - format)
Add register 3 4

causes the contents of general register 4 (32 bits) to be added to the contents of
general register 3 (32 bits) and the resulting sum to be left in general register 3,
Storage operands refer to data stored in core memory. The length of the
operand depends upon the specific data type (as illustrated in Figure 2 3) Oper
and data fields that are longer than one byte arc specified by ( he address of the
-. -
- .
lowest address byte (logically leftmost) For example , the 32-bit binary fixed
point full word with value + 267 (in hexadecimal X‘00 00 01 OB*) , stored in
-
locations 1016» 1017, 1018, and 1019 as depicted below is said to be “located
at address 1016 /’

k 4 bytes x 32 bits

0000 0000 0000 0000 0000 0001 0000 1011

Byte address ;016 1017 1016 1019

The address of (he itTl storage operand is computed from the instruction in the
following way;

Address
or
- cfBi
ctBi
}
)
+ c ( X 1| +
+ 01
Dl IRX format)
IRS, $1 , 3$ format )

where c(Bi) and c(Xi) denote the contents of general registers Bi and Xi
respectively . Exception; if Xi=0, then e(Xi) are treated as 0; likewise for Bi*0 .
For example, if we assume that general register 5 contains the number 1000,
the following instruction:

4 bytes-
OP R1 X2 B2 D2

0101 1010 0011 0000 0101 0000 0001 0000 ( RX - format)

Add from 3 0 5 16
borage to
regisi&r
32 GENERAL MACHINE STRUCTURE

causes the contents of the word (32 bits) located at address

* ctB2 ) + c ( X2 ) + D ?

--
« C( 5) + C[OJ 4 16
1000 4 o + 16
1016

to be added to the contents of general register 3 (32 bits)* with the resulting sum
left in general register 3*
Another example , assuming again that general register 5 contains 1000, is the
following instruction: (Note: in SS instructions the length is always one less than
the data moved* e.g., length 0 means move one byte.)
=
6 bytes 5H
OP L 61 D1 B2 02

1101 0010 0100 1111 0101 0000 00100000 0101 Q001 00101100
1.
Move bytes 79 & 32 6 300
from operand 2
to operand 1 (SS - format )

This instruction involves two storage operands:

Storage operand 1 address

*
c ( B1 ) + D 1
1000 + 32 - c( 5) 4 32
1032

-
Storage operand 2 address * c( B2) + D2 -
1000 4 300 - c(5) 4 300
1300

This instruction copies ( moves) th'e 80 byiesfrom locations 1032 * 1111 to

locations 1300 • 1379. Since a character is stored as a byte (see Fig 2.3g), this .
instruction could be viewed as copying an 80-character “card image" from one
area to another.
Immediate operands are a single byte of data and are stored as part of the
instruction .
Again assuming register 5 to contain 1000, the following SS instruction ,
causes the byte 0100 0000 (bits 8 through 15 of instruction) to be stored at
location 1001.

naJ
MACHINE STRUCTURE;MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 33

N- 4 bytes
OP 12 B1 D1

1001 0010 0100 0000 0101 0000 0000 0100 (SI - format)

Move immedi- 64 5 4
ate byte to (Code for
operand 1 character
blank)

Representative 360/370 instructions

Various 360 instructions will be used throughout this book in examples and as
needed In problem sets and machine problem assignments. The following subset
is particularly relevant to our purpose and should be studied in the appropriate
reference manual (See Appendix A for complete set of instructions.)

Hexadecimal
op code Mnemonic Meaning ( format )
Load group
53 L Load ( RX )
43 LH Load halfword ( RX )
S 93 LM Load multiple ( RS)
V,
E 1 13 LR Load ( RR )
La
12 LTR Load and test ( RR )
£
o
v Store group
I 50 ST Store IRX )
40 STH Store halfword ( RX )
90 STM Store multiple ( RS)

Add-group
5A A Add ( RX )
4A AH Add halfword ( RX )
u 1A AR Add ( RR )
ci
c Compare-group
m 59 C Compere ( RX )
e 49 CH Compere halfword ( RX )
a
T3
19 Cfl Compare IRR )
«L
* Divide-group
LL
5D D Divide ( RX )
1.0 DR Divide ( RR )

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34 GENERAL MACHINE STRUCTURE

Hexadecimal
op code Mnemonic Meaning l format )

Multiply group
U
5C M Multiply { RX }
it
E 4C MH Multiply halfword ( RX)
,r
1C MR Multiply ( RR )

c= Subtractgroup
o
CL 50 S Subtract ( RX )
u
4B SH Subtract halfword tRX )
LL IB SR Subtract ( RR )

Compare- group

I 55 CL Compare logical ( RX )
D5 CLC Compare logical ( SS )
95 CLI Compare logical ( SI )
15 CLR Compare logical ( RRI

Move -group
D2 MVC Move ( SS )
92 MVI Move ( SI )

And-group
54 N Boolean AND ( RX )
D4 NC Boolean AND (SS )
94 Nl Boolean AND (SI )
14 NR Boolean £ ND ( RR )
U
-
'i -
Or -grotip
-j
56 O Boolean OR ( RX )
DG OC Boolean OR ( SS )
90 01 Boolean OR 'SI )
1G OR Boolean OR ( RR )

Exdusi ve-or group

57 X Exclustve- or (F X )
07 XC Exclu$ ive-or ( SSI
97
17
XI -
Exclusive or (SI)
XR Exdusive or ( RR )

Stuff
8D SLDL Shift left (double logical ) * RS)
89 SLL Shift left ( single logical ) (RSI
BC SRDL Shift right (double logicalt IRS
63 SRL Shiit right ( single logical ) , R $ )

Ik
MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 35

Hexadecimal
op cods Mnemonic Meaning ( format )

Linkage group
45 GAL Branch and link { RX )
05 BALR Branch and Jink ( RR )
&-
Tn
Branch group
£
(3
47 BC Branch on condition ( R X )
i— 07 BCR Branch on condition ( R R )
46 BCT Branch on count { R X )
OG BCTR Branch on count { R R )

Miscellaneous
9E HIO Halt t /O ( R X )
in 41 LA Load address { R X )

I
n
9C
OA
S10
SVC
Start I /O ( R X )
Supervisor call ($1)
T 90 TIO Test I /O ( R X I
S 43 1C Insert character ( R X )
91 TM Tett under mask (SI )
42 STC Store character |RX >

5 , SPECIAL FEATURES
The 360 has hardware protection in blocks of 2,048 byles and has an elaborate
interrupt structure discussed in Chapter 9 .

2.2 MACHINE LANGUAGE

In tilts section we will discuss machine language (the actual code executed by a
computer). Again, our examples are taken from a 360 type computer. However,
-
they are easily applied toother machines.
In this section we will start the reader on his way to learning machine language.
After reading this section, the reader is referred to one of the many books or
manuals that discuss the machine language of the particular machine that he will
be using.
We will not write machine language in ones and zeros, nor will we use hexa-
decimal numbers, Rather, we will use a< mnemonic form of machine language.
3G MACHINE LANGUAGE

Binary Mnemonic

0101 10QP 0010 0000 0001 0011 1001 11QQ I L 2, 924(0,1)

OP HI X2 B2 2 OP R1, D2{X2,B2)
L
sa 2 0 1 39C
Hexadecimal

FIGURE 2J6 Mnemonic form of machine language

Figure 2.6 depicts a series of ones and zeros that may be interpreted by the
CPU as a load instruction, and the mnemonic form that we shall employ to
represent this instruction.
The following simple example will be used several times in this chapter to
demonstrate features of machine language:
Write a program that will add the number 49 to the contents of 10 adjacent
fullwords in memory , under the following set of assumptions:
Assumption 1 . The 10 numbers that are to be added to are in contiguous
fullwords beginning at absolute core location 952.
Assumption 2 . The program is in core starting at absolute location 48.
Assumption 3 . The number 49 is a fullword at absolute location 948 .
Assumption 4. Register 1 contains a 48.
Core may be thought of as shown In Figure 2.7.

2.2.1 Long Way, No Looping

Figure 2.8 illustrates a program to accomplish this addition.
The first instruction L 2,904(0,1) loads the fust number into register 2. Reg*
istcr 2 will be used as the accumulator. As was explained in section 2.13, the 360
addresses are made up of an offset plus the contents or an index register , plus the
contents of a base register. In this instruction wc have denoted the index register
as being 0. There is a zero register. However, when it is used as an index , base, or
.
branch register, it is assumed to have zero contents Therefore, the address
specified in the first load instruction above is equal to 904 plus the contents of
.
register 1 (which contains a 48), i.e., 952 This is the absolute address of the first
data element , DATA1,
The next instruction in the program adds the contents of absolute location
.
948 to register 2 Absolute location 948 contains a 49. Next comes a store
instruction that stores the contents of register 2 back into absolute location 952,

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MAC ) I INF STRUCTURE , MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 37

Absohj le Relative
locat jcn location Core

48 0
Program

948 900 49
952 904 DATA t
958 90r! DATA 2

983 940 DATA 10

FIGURE 27 Diagram of core setup for addition problem

destroying the original first data item and replacing it by a new one that is equal
to DATA 1 plus 49, SimilarlyT the next three instructions add 49 to DATA 2. An
identical set of three instructions is used for each data item.
The preceding program will worfc ; however , there are some potential problems.
For example, if we wanted to process 300 data items rather than just 10, the
storage needed for the instructions would be (3 instructions) X (length of each
-
instruction) x ( number of data items) 3,600 bytes. Thus the instructions would
overlap our data in core. Furthermore, the distance from the first instruction to
the last piece of data would be 4,800 bytes, since the data itself occupies 4 x
300 = 1,200 bytes. Using register 1 as a base register, it would be impossible to

flE
38 MACHINE LANGUAGE

Absolute Relative
ttftiress address Hexadecimal instructions Comments
48 0 68201363 L 2,90440.1) Load reg 2 from !oc

52 4 5 A 201384 A 2,900(0,1)
-
904+C(«jg 1) 052
Add 49 ( loc - 900i
c(reg 1 ) ) = 948
SS 3 50201338 ST 2,904 (0,1) Store back
60 12 B820138C L 2,908(0,1) Load next data
64 16 5 A 201384 A 2,900(0,1) Add 49
63 20 6020138C ST 2.908 (0,1) .Store back
94S 900 00000031 49
952 904

FIGURE 28 Program for addition problem - straightforward approach

access both the first data item and the last. The programmer must be aware of
this type of problem if he is writing in machine language, and should bear in
mind th J fact that the largest possible vahic of an offset is 212 A or 4,095, which
ma > not reach all his data. (It is, of course , possible to use more than one base
reg isier .)
Note that if the preceding program were loaded into location 336 instead of
location 48 , it would still execute correctly if the content of register 1 was 336.
Moving the program to a different location is a process called relocation . The
use of base registers facilitates this process.

2-2,2 Address Modification Using Instructions As Data

Our example may be analogous to the “program” depicted in Figure 2.9. If an
M.J .T. student had a date with a girl, he might write a program to do the fol
lowing.
-
1 2 3 4
If
Rent Get slide Call refused
tuxedo rule Nancy change 3
to Mary

FIGURE 2.9 Situation

The preceding boxes represent locations, and the words in those boxes repre
sent instructions to the processor, in this case , the MJ .T, student. The program
-
would have the student rent a tuxedo, get a slide rule ( this is M.I.T.), and nail
.. .
Nancy. But jf Nancy refuses, the M I T student does not want to write a new

TIE
MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 2&

program , so he writes an instruction that simply changes the contents of loca -

tion 3 from Nancy to Mary and then repeats 1 through 4. The execution of the
instruction in location 4 changes the instruction in location 3. Of course , in the
preceding program he could end up renting many tuxedos, and if Mary refuses,
she will receive an awful lot of telephone calls.
7 his M.l.T. student , however, has grasped two basic programming techniques.
The first is that the instruction in location 3 may be treated as data. The second
is looping, which he accomplished with the transfer rule in step 5. In this section
and the next we will see how these two techniques can simplify our previous
program .
Observe that in the program in Figure 2,8 we were merely using three instruc
tions over and over again . The only element that changed was the offset of the
-
load and store commands. In the first set of three instructions, the offset was
-
904. In the next set it was 90S, then 912 An alternate technique is to write a
machine language program consisting only of those three instructions, followed
by a sequence of commands that would change the offset of the load and store
instructions by adding 4 to them. The computer would execute the litres
instructions, change two of them so that the offset was increased by 4, and Joop
back to rc-cxecute the set of three instructions. Of course, they would now have
a different offset and therefore would refer to a different address.
The program in Figure 2 ,10 depicts a sequence of instructions that will per -
form the operation of adding the number 49 to 10 locations in core by modify
ing the instructions themselves.
-
Aosolute Relative
address address Instructions Comments
48 0 L 2 ,904 ( 0,11
52 4 A 2,900( 0,1 J Add 49 to a number
56 8 ST 2 ,904 (0,1 J
GO 12 L 2,0 (0,1 )
Increase displacement of
64 16 A 2,896( 0,1 )
load instruction by A
68 20 ST 2,0( 0,1)
72 24 L 2,8 (0,1)
Increase displacement of
76 28 A 2,896 (0,1 )
store instruction by 4
80 32 ST 2,8(0,1)
Branch to relative location 0 nine times

944 896 4
948 900 49
962 904 Numbers

FIGURE 2 ,10 Program for addition problem using instruction modification

nalcrial
40 MACHINE L A N G U A G E

ADDITIONAL ASSUMPTIONS:
Assumption 5. Relative location 896 contains a 4 .

To see how the program operates we must keep in mind that the contents of
location 48 ( Fig. 2.11) are not L 2,904 (0,1), but rather

0101 tOOD 0010 0000 0001 0011 T 000 1000

_
1 2 0 1
T
I
l 904
1
Sit
number 0 78 11 12 15 16 1920 31
Bytp 48 49 50 51
number

-
FIGURE 2 11 Contents of localion 48

The offset of the Instruction is Ihe last and rightmost part of the number
stored in that location. This instruction may be interpreted as a piece of data ,
and adding the number 4 to it updates the offset .
Treating instructions os data is not a good programming technique because in
maintaining the program over a period of time , it may become difficult to under -
stand what the original programmer was doing. In the case of multiprocessing
-
systems it would violate all the rules of pure procedures ( re entrant code), which
are procedures that do not modify themselves. We are including this example
merely to exemplify instruction formats and explicitly demonstrate that instruc
tions are stored as a type of data.
-
2.2 .3 Address Modification Using Index Registers
Perhaps the most elegant way to solve this example is to use the index registers
for address modification. Recall that an address equals the offset plus the con -
tents of the base register plus the contents of an index register. We use the same
three main instructions: the load instruction, add 49, and the store instruction.
We simply loop through those three instructions, updating the contents of an
index register by 4 during each pass and so updating the value of the address
specified in the load and store instructions. The following program section uses
this technique:

flE
MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 41

Absolute Relative
address address Instructions Comments
43 0 SR 4,4 Clear register 4
50 2 L 2,904 (4,1) Load data element of a rav
54 6 A (
2,900 0 ,1) Add 49
50 10 ST 2,904 (4,1) Replace data element
62 14 A 4,890 (0,1) Add 4 to index resists'
Branch bach to relative location 2, nine nme&

-
The first Instruction in this program is a subtract instruction , ft is a registcr to
register instruction* subtracting register 4 from register 4 , thereby initializing its
contents to 0, Note that this instruction is only two bytes long. As we discussed
in the previous section , the 3(10/370 has different length instructions. The 8R
instruction starts at absolute location 48. The next instruction starts at location
SO. Notice also that the load and store instructions now specify register 4 as an
index register . The first time through the loop, register 4 will contain 0, the next
.
time * 4, etc This will point the load and store instructions at a different data
item each time.
Now that we have seen how to modify instruction addresses, wc will prcceed
to add the instructions that will cany out the actual looping.

2,2.4 Looping
In this section We will discuss two 1ooping melhods using machine language. Wo
will make the additional assumptions:
Assumption 6. Relative location 892 contains a f 0
Assumption 7. Relative location 888 contains a 1 ( first method only)
Figure 2.12 depicts one looping scheme.

After the first four basic instructions are executed , there is a sequence ; ip
instructions that subtracts one from the temporary location and delects whether
or not the result is positive. If positive, control loops back to the main program
at relative location 2.
There is one instruction , Branch on Count (BCT, shown in Fig. 2.13) that ac -
complishes the work of the last four instructions in Figure 2,! 2 .
The reader is referred to the manuals for the explanation of the BCT instruc
tion. Essentially , register 3 is decremented by 1 until a 0 is reached. While the
-
content of register 3 is positive , we transfer to the address specified in the ad
dress field , in this case, 6 plus the contents of register 1. When zero is reached ,
-
no branch occurs , Most computers have a similar branching instruction .
42 MACHINE LANGUAGE

Absolute Relative
address address Instructions

43 0 SR 4A
50 2 L 2,904(4 ,1 )
64 6 A 2,900( 0,1 ) Add 49 to a number
6G 10 ST 2,904(4,1 )
62 14 A 4,896(0,1 } Add 4 to Index register
66 18 L 3,892(0,1 } Load temp (nto register 3
70 22 S 3,883( 0,1 ) Subtract 1
74 26 ST 3,892 (0,1 } Store temp
73 30 BC 2,2 (0,1) Branch If result is positive
( 2 denotes a condition
code)

936 838 1
940 892 ( Initially 10 - decremented by 1 after each loop)
944 BOG 4
943 900 49
952 904 Numbers

FIGURE 2,12 Program for addition problem showing looping

Absolute Relative
address address Instructions

43 O L 3,892 (0,1 ) Load register 3 with 10

52 4 SR 4,4 Clear register 4
54 6 L 2,904 (4,1)
53 10 A 2,900 (0.1 ) Add 49 to a number
62 14 ST 2,904 (4,1)
66 13 A 4,896 ( 0,1 ) Add 4 to index register
70 22 BCT 3,6(0,1 ) Subtract one from register
3 and branch to relative lo-
cation 6 when positive

940 892 10
944 89 G 4
948 900 49
952 904 Numbers

992 unused

FIGURE 2.13 Final version of example

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MACHINE STRUCTURE, MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 43

We now have reduced the program to 26 bytes of instruct ions and 52 bytes of
data, in contrast to the 120 bytes of instructions and 44 of data utilized in our
first attempt. This is a savings of 86 bytes. Note: all of the preceding programs
could be placed elsewhere in core, at location 400 rather than 48, for example,
and only register I need be changed.

2.3 ASSEMBLY LANGUAGE

When the user wishes to communicate with the computer, he has available to
him a spectrum of languages:

English Best for programmer

PL / l , FORTRAN A

Assembly language
Mnemonic machine language v
Machine language Best for machine

So far we have discussed the two lowest members of this spectrum, We will
now go into assembly language, which is the most machine -dopendent language
used by programmers today .
There are four main advantages to using assembly language rather than machine
language.
1 . It is mnemonic ; e.g., we write ST instead of the bit configuration 01010000
for the store instruction
2. Addresses are symbolic, not absolute
3. Reading is easier
4 . J ntroduction of data to program is easier
A disadvantage of assembly language is that it requires the use of an assembler
to translate a source program into object code. Many of the features of 360 or
370 assembly language exist in assembly languages for other machines ( if the
reader is using another machine). These examples may be easily translated into
the machine he is using.

2.3 , 1 An Assembly Language Program

Let us rewrite the program discussed in the previous section in assembly language
(shown in Fig. 2.14 ). In doing so, the assumptions iliat were made when written
in machine Language are eliminated. One of the assumptions is that the program's

ME
44 A&SEM8LY LANGUAGE

starting address was absolute core location 48. We, as programmers, cannot pre -
sume to know into what location our program will be loaded in core Thus there.
must be a way for us to load the base register with the address of the program in
core just prior to execution time. That is, execution time is the only time in
which the program , the programmer , or anyone else can be certain as to where
in core the loader will Load the user's program. The BALR instruction is one
mechanism for loading the base register .
If the assembler is to automatically compute the displacement field of instruc
tions, it must know what register can be used as a base register and what that
-
register will contain. The USING instruction tells both of these things to the as-
sembler and thus makes it possible for it to produce correct code. The ySING
-
instruction is a pseudo op. A pseudo op is an assembly language instruction that
specifies an operation of the assembler; it is distinguished from a machine op -
which represents to the assembler a machine instruction. The Define Constant
-
(DC) and Define Storage ( DS) instructions are pseudo ops that instruct the
assembler to place a 10, a 4, and a 49 in 3 consecutive fullwords (“F”) In mem*
.
ory and leave 10 more for data A number before the F would cause multiple
allocations, e.g. DS 1GGF causes the assembler to set aside a 100 full word area .

Program Comments
TEST START identifies name of program
BEGIN BALR 15.0 Set register 15 to theaddress of the next instruc-
tion
USING BEG1N+2.1& Pseudo-op indicating to assembler register 16 Is
base register and its content is address of next
instruction
SR 4.4 dear register 4 tret indexed
L 3, TEN Load tha number 10 Into register 3
LOOP L 2,DATAf 4) Load data (Index ) Into register 2
A .
2 FORTY 9 Add 49
ST .
2 DATA {4) Store updated value of data (Index)
A .
4 FOLR Add 4 to register 4 ( set index - index+4)
BCT .
3 LOOP Decrement register 3 by 1> if result non- zero ,
branch back to loop
BR 14 Branch back to caller
TEN DC F1Q' Constant TO
FOUR DC F ‘4 f
Constant 4
FORTY 9 DC F'49‘ Constant 49
DATA DC F'1,3.3 ,3.3,
Words to be processed
END

FIGURE 2.14 An usembly language program

ME
 .
MACHINE STRUCTURE MACHINE LANGUAGE AND ASSEMBLY LANGUAGE 45

CLARIFICATION

-
1. USING is a pseudo op that indicates to the assembler which general register
.
to use as a base and what its contents will be This is necessary because no
special registers are set aside for addressing, thus the programmer must in -
form the assembler which registers) to use and how to use them . Since ad
dresses are relative, he can indicate to the assembler the address contained
-
in the base register. The assembler is thus able to produce the machine
code with the correct base register and offset .
2. BALR is an instruction to the computer to load a register with the next
.
address and branch to the address in the second field When the second
-
operand is register 0, as it is here , execution proceeds with the next instruc
tion. It is important to see the distinction between the BALR, which toads
the base register, and the USING , which informs the assembler what is in
the base register. The distinction will be clearer after we study the as
sembler, but for now , note that a USING only provides information to the
-
assembler but does not load the register. Therefore, if the register does not
contain the address that the USING says it should contain , a program error
may result.
3. START is a pseudo -op that tells the assembler where the beginning or the
program is and allows the user to give a name to the program. In this case
the name is TEST,
-
A , END is a pseudo op that tells the assembler that the last card of the pro
gram has been readied.
-
5. Note that instead of addresses in the operand fields of the instructions as
in the example of Figure 2.8, there are symbolic names. The main reason
for assemblers coming into existence was to shift the burdens of calculating
specific addresses from the programmer to the computer.
6. BR 14, the last machine- op instruction , is a branch to the location whose
address is in general register 14. By convention , calling programs leave
their return address in register 14.

.
2.3 2 Example Using Literals
Here we will repeat the same example using tiierals , which are mechanisms where
by the assembler creates data areas for the programmer, containing constants he
-
requests.
=
In the program of Figure 2. IS the arguments FT 0', “F'49', =F'4' are literals
which will result in the creation of a data area containing 10,49,4 and replace-
ment of the literal operand with the address of the data it describes.
The assembler translates the instruction L 3, = FT IT so that its address portion
points to a full word that contains a 10. Normally, the assembler will construct
43 ASSEMBLY LANGUAGE

TEST START 0
BEGIN BALFt BASE .Q
USING BEG IN + 2 ,BASE
SR 4,4
L -
3, F' tD'
LOOP L 3,DATA (4 )
A 3, = F *49’
ST 2,DATA (4 )
A 4 = F'4 f
BCT 3 , *- 10
6R 14
LTORG
DATA DC F 11 ,3, 3,3,3,4.5£,9 ,CT
BASE EOU 15
END

FIGURE 2.15 Assembly language program using literals

a “literal table” at the end or the program. This table will contain all the con -
stants that have been requested through the use of literals. However , the pseudo
op LTORG can tell the assembler to place the encountered literals at an earlier
-
location. This pseudo-op is used in the case where we have a very long program.
For example , if otir DC instruction contained 10,000 pieces of data, it would
have been impossible for the offset of the load instruction to reach the literals at
the end of our program. In this case , wc would want to force the literals into the
program before the DC instruction .
In the BCT instruction in the same program we have used as an address M6.
The star is a mnemonic that means “here.” The expression *-16 refers to the
address of the present instruction minus 16 locations, which is LOOP. (This type
of addressing is not usually good practice; should it become necessary for the
-
programmer to insert other statements in between LOOP and BCTt he would
have to remember to change the 16.)
The statement BASE EQU IS assigns this value IS to the symbol BASE; BASE
will be everywhere evaluated as 15 . The EQU pseudo-op allows the programmer
to define variables. Here, for example, if he wished to use a different base
register , he would need only to change the EQU statement. Any sort of valid
arithmetic expression may appear as the operand of the EQU statement.
Depicted in Figure 2.16 is the assembled version (that is, the output of the as
sembler ) of the preceding program.
-
Observe that some pseudo-ops (e.g., START and USING) do not generate
machine code. Note also that the BR 14 instruction has been translated to
BCR 15,14. This is because BR is a member of the assembler mnemonic group
of instructions that allow the programmer to use a more mnemonic op code in
place of BC followed by a particular mask value (see Appendix A).

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