SPWM-Based D-Ȉ Digital Control for

Paralleled 3-φ Grid-Connected Inverters

T.-F. Wu, Y.-Y. Chang, C.-H. Chang and T.-C. Zou Y.-R. Chang
Elegant Power Electronics Applied Research Lab (EPEARL) Engineering Division
Department of Electrical Engineering Institute of Nuclear Energy Research (INER)
National Tsing Hua University Atomic Energy Council, Executive Yuan
Hsin-Chu 30013, Taiwan, ROC Longtan, Taoyuan 32546, Taiwan, ROC
Email: [email protected] E-mail: [email protected]

Abstract—This paper presents an SPWM-based division- blocking the circulating current. While, it will increase system
summation (D-Ȉ) digital control for paralleled three-phase grid- size and cost significantly. Secondly, inter-phase reactors are
connected inverters. The proposed D-Ȉ control approach derives introduced to provide high impedance path among paralleled
the plant, and then obtains the control gains or duty-ratio control inverters, which can block high-frequency circulating current
laws to cancel the variation effects of dc voltage, switching period
effectively. However, this approach cannot eliminate low-
and inductance. With the D-Ȉ digital control, each inverter can
track sinusoidal reference current of each phase independently, frequency component and it needs bulky reactors. The third
eliminating circulating currents. The inverter system can achieve one, synchronized control, treats the paralleled-inverter system
the functions of grid connection, rectification with power factor as an inverter. It usually requires some high-frequency
collection, and STATCOM by taking into account wide filter- communication signals to synchronize the switching action of
inductance variation and grid-voltage distortion, reducing core all the modules. However, when more inverters are in parallel,
size significantly. The control laws for achieving the desired the system becomes very complicated to design and control
functions are derived in detail and they are expressed in general due to noise interference. To overcome the above limitations,
forms for readily software programming. In the design and some approaches without additional passive components were
implementation, the inductances corresponding to various
presented [13]-[15]. In [13], it develops a zero-sequence
inductor currents were measured at start up and stored in the
controller for scheduling loop gain cycle by cycle. Experimental model to predict the dynamics of the zero-sequence current
results from a three-inverter system have confirmed the analysis and it introduces a control variable associated with space-
and discussion of the proposed control approach. vector modulation (SVM) to suppress the circulating current.
In [14], a continuous and discrete variable structure control
Keywords—D-Ȉ digital control; SPWM; paralled inverter; was proposed to improve transient performance of the control
inductance variation method in [13]. Another approach, namely one-cycle control
(OCC) [15], uses an interaction between vector operation and
I. INTRODUCTION bipolar operation to limit the circulating current, keeping
With the development of dc distribution system and switching loss low. Its controller is mainly realized by an
renewable power generation technologies, the use of integrator with reset, linear and logic components, but no DSP,
paralleled inverters has become more popular, especially microprocessor and software. However, inductance variation
paralleled three-phase grid-connected inverters. Parallel with current levels has not been considered in the controller
operation of three-phase inverters can extend the power range design yet.
to a much higher level. Furthermore, it allows modular design In literature, two-phase modulation (TPM) and SVPWM
to attain the redundancy purpose, improving system reliability. based D-Ȉ digital control for a 3‫ ׋‬bi-directional inverter with
wide inductance variation overcoming some of the
In the design of paralleled inverters, there are two concerns:
aforementioned limitations have been designed and
current sharing [1]-[6] and circulating current among the
implemented [16], [17]. By selecting the zero-crossing points
inverter modules [7]-[12]. For the first concern, the “automatic of phase voltages as region transitions, the control laws and
master” or called the “democratic current sharing” method is the related parameter tables for the four operation modes, grid-
employed widely due to its simplicity and easy expandability. connected, rectification with PFC, PF leading and PF lagging,
In this case, control of the circulating current becomes an can be unified to a general form, reducing program size and
important subject for the paralleled-inverter design. firmware-programming complexity significantly. The
In the literature, there are typically three approaches to switching sequences of the four modes are also unified to the
avoiding circulating current: isolation, high impedance and one of the grid-connection mode. In this paper, the D-Ȉ digital
synchronized control. The isolation approach adopts a three- control is extended to parallel operation of multi-inverters.
phase isolated transformer to separate ac from dc side, Based on sinusoidal PWM (SPWM) and with the D-Ȉ digital

978-1-4673-7151-3/15/$31.00 ©2015 IEEE 6818

Authorized licensed use limited to: Tsinghua University. Downloaded on March 21,2023 at 01:00:32 UTC from IEEE Xplore. Restrictions apply.
control, each phase of an inverter module can track its the meshes are connected to voltage vN0 at node O referred to
sinusoidal reference current independently, eliminating neutral point N in parallel. In other words, each three-phase
circulating currents significantly. While, it will decrease dc- inverter can be equivalent to three individual single-phase
bus voltage utilization. Experimental results from a three- inverter, in which the average switching-state circuit of each
inverter system have confirmed the analysis and discussion of inverter and its equivalent circuit for each leg are shown in Fig.
the proposed control approaches. 2(a) and 2(b), respectively. According to KVL, the mesh
In section II, the plant of a three-phase full-bridge inverter equation derived from Fig. 2(b) is given below
is first modeled to a current source and then the controller is diLX
designed to achieve unity loop gain. The final duty-ratio u X = LX + v XN + vNO , (1)
dt
control laws are obtained through a simple proof of parameter
where
k and a stability analysis is used to verify the feasibility of the
proposed control approach. u X = d X ⋅ vDC
and
II. D-Ȉ DIGITAL CONTROL FOR PARALLELED INVERTERS vNO = k ⋅ vDC .
For a PWM converter, one switching cycle is divided into In (1), inductance LX is the inductance of the filter inductor in
several time intervals and each time interval is corresponding the inverter, voltage vXN is the phase voltage and iLX is the
to a switching-state voltage. The average switching-state inductor current. Voltage u X denotes the average switching-
voltage over one switching cycle is equal to the sum of all state voltage of each leg which is equivalent to the product of
products of duty ratio and switching-state voltage, which can duty ratio dX and dc-bus voltage vDC. Voltage vNO varies with
help derive state equations and obtain t plant Gp. The D-Ȉ
switching states and it can be classified into four levels: 0,
digital control is then developed to cancel all variation effects
of the system parameters in the plant. In the following, the D- vDC/3, 2vDC/3 and vDC. Thus, its average (vNO ) can be denoted
Ȉ digital control for the inverters in parallel operation is by the product of variable k and voltage vDC. Equation (1) can
presented. be also transformed to the form of state equation,
diLX 1
DTH
= (d X vDC − vXN − kvDC ), (2)
SRH VLR iR dt LX
DRH SSH DSH STH
uR LR vRN and its discrete form can be written as follows:
VLS iS
TS
(d X vDC − vXN − kvDC ),
vDC uS
LS vSN
N ΔiLX = (3)
VLT iT LX
DRL DSL uT
LT vTN where the diLX/dt in (2) is expressed in discrete form: ǻiR/TS,
SRL SSL STL and TS is the switching period. It can be seen that the output
O DTL
controlled variable ΔiLX (=iref(n+1),x –iLX(n)) consists of one
Fig. 1. Circuit diagram of a three-phase inverter. control variable dX and two voltage variables vXN and vDC. In
iLR (3), duty ratio dX can be expressed as
uR LR 
uS LS iLS vRN d X = DX + d X , (4)
O N 
LT iLT vSN
uT where d X is the small-signal variation of the duty ratio and DX
vTN is the operating point of the duty ratio. According to (3),
v NO operating point DX can be obtained by assuming inductor-
current variation ΔiLX equal to zero, and
(a)
v XN
uX LX iLX DX = k + . (5)
vDC
VLX vXN 
To find small-signal variation d X , plant GP must be derived
O N
vNO first. By taking partial derivative of ΔiLX with respect to the
(b)
three variables (dX, vXN and vDC), the plant can be expressed as
Fig. 2. (a) The average switching-state circuit of a three-phase full-bridge follows:
inverter and (b) its equivalent circuit for each leg.
TS vDC
A. Inverter modeling G ∂ΔiLX =− , (6)
P,
∂d X
LX
Power circuit diagram of a three-phase six-switch inverter
is shown in Fig. 1. In a multiple parallel-inverter system, each
inverter can be considered as an individual system, since all of

6819

Authorized licensed use limited to: Tsinghua University. Downloaded on March 21,2023 at 01:00:32 UTC from IEEE Xplore. Restrictions apply.
 TS LX ie vXN
G ∂ΔiLX =− (7) dX = + + k. (12)
P, LX TSVDC VDC
∂v XN

and Note that from the above derivation procedure, it can be

recognized that given a three-phase inverter, we derive the
kTS state equation, as the form shown in (2), and convert it into the
G ∂ΔiLX =− . (8) digital form shown in (3) first, and then take partial derivative
P,
∂vDC
LX of (3) to obtain the plant, as shown in equations (6), (7) and
(8). Secondly, we solve for control gain of ΔiLX with respect
From (6) to (8), the average plant model of the average
switching-state circuit shown in Fig. 2(b) can be obtained and to dX, as shown in (10). Finally, we will obtain a control law,
illustrated in Fig. 3. as shown in (12). The proposed control approach derive the
duty-ratio control law by cancelling the variation effects of the
system parameters, such as LX and TS, which saves the
G conventional abc-dq transformation and also overcomes its
F,
∂ Δ iLX
∂v X
e − sTS limitations [16]. Additionally, the duty-ratio control law of
each phase is independent of the others, so as the discussed
∧
inverter can track sinusoidal reference current of each phase
dX G ΔiLX ΔiLX individually, reducing circulating currents.
P,
∂Δi LX
∂d X
¦ ¦
&RQWURO 3ODQW

Y;1 G
G ∂ Δ iL X '; F,
∂ Δ iLX
∂v X
e − sTS
F,
∂vDC   
∧
ΔiLX 
∧
,UHI  LH G dX  G ΔiLX  L/;
¦ C,
∂d X ¦ ∂Δi
P , LX
∂d X
¦ ¦
∂ΔiLX

Fig. 3. Plant block diagram of an equivalent single-phase inverter. LIE
Y'& G
∂ Δ iLX
F,
B. Controller Design ∂vDC

With the D-Ȉ digital control, loop gain is designed to +

canceling the variation effects of the system parameters, such
as LX and TS, from which the inverter can track current Fig. 4. Control block diagram of an equivalent single-phase inverter.
command at next switching cycle precisely. Additionally, the
D-Ȉ digital control regards an inverter system as a current C. Determination of Parameter k
source so that control gain GC is defined as duty ratio versus This section proves that the average value of voltage vNO
current error ie (=Iref-ifb). Then, GC can be derived by satisfying over one switching period is equal to half of dc-bus voltage
the following equations: vDC under sinusoidal pulse width modulation (SPWM); thus
parameter k can be determined to be 0.5. First, the reference-
G ∂Δd X ⋅G ∂ΔiLX = 1. (9) voltage commands based on SPWM are defined as three
C, P,
∂iLX ∂d X sinusoidal voltages with 120Ʊ shift from each other, which can
be expressed as follows:
By substituting (6) into (9), the control gain can be obtained as
belows: va* = VM cos(θ ), (13)
LX 2
G ∂Δi = . (10) vb* = VM cos(θ − π ) (14)
C , LX
∂d X
TSVDC 3
and
Combing (10) with Fig. 3, an overall control block diagram of 4
each phase is shown in Fig. 4. It can be observed that the vc* = VM cos(θ − π ), (15)
control block includes one feedback variable ifb and two 3
where voltage VM is the magnitude of ac side voltage. When
feedforwards vX and vDC. With the proposed D-Ȉ control, the an SPWM-based inverter system is operated in the steady
designed controllers can eliminate the impacts of system state, one line period can be divided into six rsectors due to
parameters (i.e. LX and TS) on the plant GP, insuring current non-zero vectors, as shown in Fig. 5. In sector I, the required
tracking accuracy. According to Fig. 4, the small-signal durations of two adjacent vectors, V1 and V2, in one switching
variation of the duty ratio can be expressed as period T are t1 and t2, which can be expressed as
 Li
dX = X e . (11)
TSVDC
The duty-ratio control law can be then rewritten as

6820

Authorized licensed use limited to: Tsinghua University. Downloaded on March 21,2023 at 01:00:32 UTC from IEEE Xplore. Restrictions apply.
 π LS ΔiLS vSN 1
sin( − θ ) dS = + + , (23)
3V 3 (16) TSVDC VDC 2
t1 = T
2VDC π
sin( ) and
3
LT ΔiLT vTN 1 (24)
and dT = + + .
TSVDC VDC 2
3V sin(θ ) (17)
t2 = T .
2VDC sin(π ) V3 010 V2 110
3 II
Then, the durations of zero vectors, t0 and t7, in one switching
period can be also determined by the relationship of similar III I
triangles: V4 011 V0 V1 100
V7
1 IV VI
t0 = T (Vdc − 2V cos θ ) (18)
V
2Vdc
and
V5 001 V6 101
π
sin( − θ ) Fig. 5. Space vectors of three-phase inverters.
3V 3 3V sin(θ ) 1 (19)
t7 = T − T −T −T (Vdc − 2V cos θ ).
2Vdc π 2V π 2V
sin( ) dc sin( ) dc
3 3 d̂ ΔiL
¦ GC GP G
Over one switching period, voltage vNO has four states, vDC,
2vDC/3, vDC/3 and 0, corresponding to V7 (111), even vectors,
odd vectors and V0 (000) and the average value (vNO ) can be
determined as

§1 ·t §2 ·t t
vNO = ¨ Vdc ¸ 1 + ¨ Vdc ¸ 2 + Vdc 7 . (20)
Fig. 6. Control block diagram for stability analysis.
© 3 ¹ T © 3 ¹ T T
By substituting equations (16) ~ (19) into (20), we can obtain D. Stability Anaysis
π π According to the aforementioned derivation, the control
V sin( − θ ) 3V sin( − θ )
3 2V sin(θ ) 3 3V sin(θ ) Vdc block diagram for stability analysis is illustrated in Fig. 6,
vNO = + + Vdc − − − + V cos(θ )
π π π π 2 where GP and GC are shown in (6) and (10), respectively, and
2sin( ) 2sin( ) 2sin( ) 2sin( )
3 3 3 3 G is the transfer function of inductor-current variation ΔiLX to
π
−2V sin( − θ ) − V sin(θ ) output inductor current iLX, which can be expressed by
3 V
= + dc + V cos(θ )
π 2 iLX 1
2sin( )
3 G= = . (25)
π π π
ΔiLX 1 − e − sT
−2V sin( − θ ) cos(θ ) + 2V cos( ) sin(θ ) − V sin(θ ) + 2V sin( − θ ) cos(θ )
= 3 3 3 HX is the feedback gain. Since the feedback delay time (5 ȝs)
π
2sin( ) is much smaller than sampling time (50 ȝs), the feedback gain
3
π
can be considered as an ideal case. That is, HX is unity gain.
2V cos( ) sin(θ ) − V sin(θ ) Loop gain / can be then determined as the follows:
3 V
= + dc
π 2
2sin( )
/ = GC ⋅ GP ⋅ G ⋅ H X = 1
3 . (26)
V 1 − e− sT
= dc .
2
In (26), e-sT can be approximated with (1-sT) by using Taylor
(21) series and thus the loop gain can be rewritten as
The above derivation shows that the average value of voltage
vNO over one switching period is equal to half of dc-bus /= 1 . (27)
voltage vDC under sinusoidal pulse width modulation (SPWM), sT
so as parameter k is equal to 0.5. Finally, by replacing X with It can be seen that loop gain / is a low-pass filter so as the
R, S and T in (12) and taking into account (21), the duty-ratio system is stable. To observe the frequency response of the
control laws for the three upper-arm switches can be expressed system, the gain of the transfer function of iL/Iref must be
as follows: derived and it can be expressed as:
LR ΔiLR vRN 1
dR = + + , (22) Γ=
1
.
TSVDC VDC 2 1 + sT (28)

6821

Authorized licensed use limited to: Tsinghua University. Downloaded on March 21,2023 at 01:00:32 UTC from IEEE Xplore. Restrictions apply.
With MATLAB Simulink, the Bode plots of the transfer III. EXPERIMENTAL RESULTS
function in (28) are illustrated in Fig. 7, from which we can The proposed D-Ȉ digital control has been confirmed by a
observe that the frequency bandwidth is 20 k (rad/s) and the 8 kVA three-phase inverter. Based on the aforementioned
closed-loop gain is 0 db (unity gain) when frequency Ȧ is specification and analysis, parameter determination of the
below 20 k (rad/s), which means that when input current power stage is summarized in Table I. The range of dc-bus
command is changed, output inductor current can track the voltage is specified from 360 V to 400 V and the switching
command precisely in one switching cycle. frequency is 20 kHz. The nominal phaseġ voltage is 220 Vrms
Bode Diagram
and the line frequency is 60 Hz. The inverter inductance varies
0

-5
from 2 mH to 300ġ ȝH per phase, of which the plot of
-10 inductance percentage versus its inductor current is illustrated
Magnitude (dB)

-15

-20
in Fig. 8. With the variation, the core size can be reduced by 5
-25 times. The power diodes are realized with silicon carbide,
-30
which have no reverse-recovery time. The harmonic
components of the output currents were measured up to 20th
-35
0

harmonic with a power analyzer WT1600.

Phase (deg)

-45

TABLE I. SYSTEM PARAMETERS OF THE DESIGNED INVERTER.

-90
3 4 5 6
10 10 10 10
Frequency (rad/s)
Parameters Symbols Values
Fig. 7. Bode plots of the transfer function in (28). DC-bus voltage vDC 360 ~ 400 V
AC grid voltage vRS, vST & vTR 220 Vrms (nominal)
Maximum rated Pmax 8 kVA
VRN ILR ILS ILT
power
Line frequency fl 60 Hz
Inductors LR, LS & LT 300 ȝH ~ 2 mH
Output filter capacitor Co 5 ȝF
IGBT VCE(on) typ. = 1.6 V, VCES =
Power switch HGTG40N60A4 600V, and
IC(TC =25ɗ ) = 75 A
Power diode CREE VF(TJ=25ɗ) typ. = 1.5 V
(silicon carbide) C3D20060D Zero-Recovery Time
Switching frequency fs 20 kHz
(iLR, iLS and iLT: 20A/div; time: 2ms/div) Power factor PF 0 ~ 1 leading or lagging
(a)

VRN ILR ILS

ILT

(iLR, iLS and iLT: 20A/div; time: 2ms/div)

(b)
Fig. 8. Plots of inductance percentage versus its inductor current for MPP core
CM778060.
ILS ILT
VRN ILR A. Test with Wide Inductance Variation
Fig. 9 shows the current waveforms with (case (a)) and
without (case (b)) considering wide inductance variation at 8
kW and it also shows the transition from case (a) to case (b).
The tests were based on the proposed control laws and the
inverter was operated in grid-connection mode. With the
consideration of wide inductance variation, the inverter can
track sinusoidal reference currents precisely, from which the
(iLR, iLS and iLT: 20A/div; time: 2ms/div) good tracking is achieveded by canceling the effects of system
(c) parameters. While, those without the consideration have sub-
Fig. 9. Measured waveforms of the three-phase inductor currents using the harmonic oscillation. That is, the inverter requires other well-
proposed control approach (a) with, (b) without considering wide inductance
variation and (c) under a transition from case (a) to case (b) in grid-connection designed controllers to compensate the lack of inductance-
mode at 8 kW. variation consideration.

6822

Authorized licensed use limited to: Tsinghua University. Downloaded on March 21,2023 at 01:00:32 UTC from IEEE Xplore. Restrictions apply.
 current. For the test in grid-connection mode, a dc source is
connected to dc bus through a resistor RL and its voltage is
ILR1
higher than the dc-bus voltage, insuring that the power from
the dc source will inject into the dc-bus side.
ILR2 RL iLR1
iLS1
VDC INV 1
iLT1
iDC Slave
I in1 R
I0
iLR2 Relay vR
DC Source iLS2 vS
INV 2
iLT2 N
Slave vT

(iLR1 and iLR2: 10A/div; i0: 5A/div; time: 5ms/div) I in 2

(a) iLR3
R
INV 3 iLS3
Master iLT3
I in 3
ILR1
(a)
ILR2 VDC

ILR1

I0
ILR2

(iLR1 and iLR2: 10A/div; i0: 5A/div; time: 5ms/div)

ILR3
(b)
Fig. 10. Measured waveforms of the three-phase inductor currents and total
output current based on (a) TPM and (b) SPWM.

B. Comparison between TPM-Based and SPWM-Based D-Ȉ (b)

Digital Control (VDC : 100 V/div, Iin1 ,Iin2 ,Iin3: 5 A/div, time: 10 ms/div)
The proposed D-Ȉ digital control can be also applied to VDC
any modulation, such as two-phase modulation (TPM or Iin1
DPWM) and space-vector PWM (SVPWM). Generally, when
SVPWM is adopted for a paralleled inverter system, it Iin2
requires extra compensation of the zero-sequence current,
complicating inverter control. With TPM, the inverter has Iin3
lower switching loss than that with other modulations, since it
only keeps two legs switching. However, TPM-based
paralleled inverters have obvious current distortion due to six-
region transition, as shown in Fig. 10(a). When TPM is
adopted, one of three-leg switches will be turned on or off (c)
over one-sixth line period, resulting in six switching patterns. (VDC : 100 V/div, Iin1 ,Iin2 ,Iin3: 5 A/div, time: 10 ms/div)
Thus, the total output current will vary significantly at pattern Fig. 11. (a) Configuration of the designed three paralleled inverter system and
transitions. When SPWM is adopted, all of switches are measured waveforms of (b) three phase-R inductor currents and (c) three
output total currents.
switched all the time without transitions. Fig. 10(b) shows the
measured waveform of the inductor currents and the total Fig. 11(b) shows measured waveforms of three phase-R
output current based on SPWM. It can be seen that the inductor currents and the dc-bus voltage. It can be seen that
circulating currents due to the six-sector transitions are almost the three inverters track sinusoidal reference currents precisely
eliminated. and the dc-bus voltage can be also regulated to the certain
range. Additionally, with the master-slave mechanism, the
C. Verification for three paralleled inverters RMS values of the three inverters are identical. Fig. 11(c)
Fig. 11(a) shows a system configuration of three shows three output total currents. It can be observed that the
paralleled inverters, which is set for grid-connection mode. average values of the three currents are close to zero, but they
First, ac grid will charge dc-bus capacitor through resistor R have high frequency ripples, which resulted from
and three inverter modules. When the control unit of the asynchronous PWM carriers of each inverter module.
master inverter is ready, relays will be turned on. The master Fig. 12(a) shows the system configuration for
inverter then regulates dc-bus voltage to the required voltage rectification-mode test. A resistive load RL is connected to the
range, 360 ~ 400 V. Delaying about 1 s, the control units of dc bus through a breaker, insuring that power will be injected
the two slave inverters sense total input dc current iDC and from ac grid and supply for the load. Fig. 12(b) and Fig. 12(c)
their current commands is determined by one-third of the total show measured waveforms of three phase-R inductor currents
and three output total currents, respectively. Similar to grid-

6823

Authorized licensed use limited to: Tsinghua University. Downloaded on March 21,2023 at 01:00:32 UTC from IEEE Xplore. Restrictions apply.
connection mode, the three inverters can track sinusoidal significantly. Experimental results have verified the feasibility
inductor currents as well as regulate the dc-bus voltage. With of the proposed control approaches.
the proposed D-Ȉ digital control and the master-slave
mechanism, the paralleled inverter system can achieve both ĐŬŶŽǁůĞĚŐŵĞŶƚ
current sharing and circulating-current elimination.
The authors would like to thank the Institute of Nuclear
iLR1
Energy Research and Ministry of Science and Technology,
INV 1
iLS1 Taiwan, ROC, for funding this research.
iDC VDC iLT1
Slave
I in1 R

iLR2 Relay vR ZĞĨĞƌĞŶĐĞƐ

INV 2 iLS2 vS
RL
iLT2 vT
N [1] K. Matsui, “A pulse width modulated inverter with parallel-connected
Slave
I in 2 transistors by using sharing reactors,” in Proc. IEEE Ind. Applicat. Soc.
Annu. Meeting, Toronto, ON, Canada, 1985, pp. 1015–1019.
iLR3
R [2] T. Kawabata and S. Higashino, “Parallel operation of voltage source
INV 3 iLS3
Master iLT3
inverters,” IEEE Trans. Ind. Applicat., vol. 24, pp. 281–287, Mar./Apr.
I in 3 1988.
[3] J. W. Dixon and B. T. Ooi, “Series and parallel operation of hysteresis
current-controlled PWM rectifiers,” IEEE Trans. Ind. Applicat., vol. 25,
(a)
pp. 644–651, July/Aug. 1989.
VDC [4] J. W. Kolar, and T. Friend, “The Essence of Three-Phase PFC Rectifier
Systems Part I,” IEEE Trans. on Industrial Electronics, 2012. S.
ILR1
Ogasawara, J. Takagaki, and H. Akagi, “A novel control scheme of a
parallel current-controlled PWM inverter,” IEEE Trans. Ind. Applicat.,
ILR2
vol. 28, pp. 1023–1030, Sept./Oct. 1992.
[5] Y. Komatsuzaki, “Cross current control for parallel operating three-
phase inverter,” in Proc. 25th Annu. IEEE Power Electron. Spec. Conf.,
ILR3 1994, pp. 943–950.
[6] Y. Sato and T. Kataoka, “Simplified control strategy to improve ac-
input current waveform of parallel-connected current-type PWM
rectifiers,” Proc. Inst. Elect. Eng., vol. 142, pp. 246–254, July 1995.
[7] L. Matakas Jr. and E. Masada, “Analysis of the parallel connection of
(b)
3-phase VSC converters,” in Proc. Int. Power Electron. Congr. (IPEC),
(VDC : 100 V/div, Iin1 ,Iin2 ,Iin3: 5 A/div, time: 10 ms/div)
1995, pp. 854–859.
[8] L. Matakas Jr. andW. Kaiser, “Lowharmonics, decoupled histeresis
Iin1 type current control of a multi-converter consisting of a parallel
transformerless connection of VSC converters,” in Proc. IEEE Ind.
Applicat. Soc. Annu. Meeting, New Orleans, LA, 1997, pp. 1633–1640.
Iin2
[9] S. Fukuda and K. Matsushita, “A control method for parallel-connected
multiple inverter systems,” in Proc. Power Electron. Variable Speed
Iin3 Drive Conf., London, U.K., 1998, pp. 175–180.
[10] R. Abe, Y. Nagai, and K. Tsuyuki, “Development of multiple space
vector control for direct connected parallel current source power
converters,” in Proc. Power Conv. Conf., vol. 1, 1997, pp. 283–288.
[11] C. S. Lee et al., “Parallel UPS with an instantaneous current sharing
control,” in Proc. 24th Annu. Conf. IEEE Ind. Electron. Soc., vol. 1,
(c)
1998, pp. 568–573.
(VDC : 100 V/div, Iin1 ,Iin2 ,Iin3: 5 A/div, time: 10 ms/div)
Fig. 12. (a) configuration of the designed three paralleled inverter system and [12] K. Xing, “Modeling, Analysis and Design of Distributed Power
measured waveforms of (b) three phase-R inductor currents and (c) three Electronics System Based on Building Block Concept,” Ph.D.
inverter output total currents. dissertation, Virginia Polytech. Inst. and State Univ., Blacksburg, May
1999.
IV. CONCLUSION [13] Z. Ye, D. Boroyevich, J. Y. Choi, and F. C. Lee, “Control of circulating
current in two parallel three-phase boost rectifiers,” IEEE Trans. Power
The SPWM-based D-Ȉ digital control for three-phase Electron., vol. 17, no. 5, pp. 609–615, Sep. 2002.
paralleled inverters considering wide inductance variation and [14] S. K. Mazumder, “Continuous and discrete variable-structure controls
for parallel three-phase boost rectifier,” IEEE Trans. Ind. Electron., vol.
taking into account line voltage distortion has been presented 52, no. 2, pp. 340–354, Apr. 2005.
in this paper. In the derivation procedure of the control laws, [15] Y. Chen and K. Smedley, “Parallel operation of one-cycle controlled
the discussed inverter is modeled to an average switching-state three-phase PFC rectifiers,” in Proc. IEEE APEC, Austin, TX, Mar. 6–
circuit first and its state equation is then derived. With the D-Ȉ 10, 2005, vol. 3, pp. 1689–1695.
[16] T.-F. Wu, C.-H. Chang, L.-C. Lin, G.-R. Yu and Y.-R. Chang, “A D-Ȉ
digital control, the product of plant GP and control gain GC is Digital Control for Three-Phase Bidirectional Inverter to Achieve
unity, which can cancel the variation effects of the system Active and Reactive Power Injection,” IEEE Trans. on Industrial
parameters, such as LX and TS. Stability analysis has also been Electronics, vol. 61, no 8, pp. 3879-3890, August. 2014.
presented to verify that the inverter can operate stably to track [17] T.-F. Wu, C.-H. Chang and L.-C. Lin, “SVPWM-Based D-Ȉ Digital
Control for Three-Phase Grid-Connected Inverter with Wide
the reference currents. In addition, the proposed D-Ȉ digital Inductance Variation,” 2014 ECCE Conf., 2014.
control allows each inverter module to track its own reference
current independently, eliminating circulating current

6824

Authorized licensed use limited to: Tsinghua University. Downloaded on March 21,2023 at 01:00:32 UTC from IEEE Xplore. Restrictions apply.