ENSC 450 FINAL EXAM, APRIL 19 2016

Student Number:

This exam is organized in 116 points, grades will be awarded in percentage

SECTION 1: Problem (30pts)

Consider a logic network formed by a NORx3 gate, driving a wire that has total equivalent capacitance 2C, and
equivalent resistance 3R. The wire is driving a NANDx2 gate and two BUFx1 gates. Assume a ratio of 2 between
the resistivity of PMOS and NMOS.

Determine the rise and fall propagation time in the best and in the worst case in terms of Equivalent RC units
using Elmore Delay. We suppose that a NMOS device of minimum width offers resistance R and Gate/Diffusion
Capacitance C and that all gates in the network have symmetrical behavior in the worst case.

In the layout, diffusion areas are to be considered shared whenever possible. To ease your work, it is
recommended to draw the circuit annotating the R and C values that are relevant for the calculation.

The Elmore Delay formula is :

t pd ≈ ∑
nodes i
Ri −to − sourceCi

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

Hint: Please remember that the Elmore delay is always calculated STARTING FROM THE Voltage SOURCE into
the network. VDD or VSS are both seen as sources, respectively for pull-up and pull-down.
SECTION 2: Problem (20pts)
Use Elmore delay to calculate the maximum skew in the clock tree described below.
SECTION 3: Problem [12pts]:

Starting from the attached formula for switching probability propagation P, estimate the switching activity
Ai=Pi * !Pi for every wire in the network below, and suggest what wire is more critical for dynamic power
consumption.

Consider a probability of 50pts (0.5) at the inputs.

P1 : P2: P3:

A1: A2: A3:

Critical Node:

SECTION 4: Problem [12pts] Given the spice circuit described below:

x1 vdd vdd n2 n1 pmos w=Wmin

x2 vdd vdd n1 n2 pmos w=Wmin
x3 gnd b1 w n1 nmos w=X
x4 gnd b2 w n2 nmos w=X
x5 gnd gnd n2 n1 nmos w=Y
x6 gnd gnd n1 n2 nmos w=Y

a) Draw the related schematic

b) Explain the functionality of the circuit
c) Propose valid values for X, Y
SECTION 5: Questions [8pts]

a) Which of the two configuration is more common in standard automated P&R Designs? Why ?

b) Which of the two configurations is more common in standard automated P&R Designs? Why ?
SECTION 6: Multiple Choice Questions [24 pts]:

Note: In the following, there is more than one correct answer. 4pts is awarded for each questions only if all
answers are marked correctly

1) In which of the following Signoff checks it is necessary to take into account Cross-Talk Effects ?

( ) Power Analysis
( ) Hold Analysis
( ) Setup Analysis
( ) Power Integrity
( ) DRC
( ) LVS

2) What is the most common market for NOR Flash memories?

( ) USB Sticks
( ) SSD Drives
( ) Embedded memory macros
( ) Wireless communications
( ) Automotive Microcontrollers

3) When are ATPG test pattern calculated?

( ) They are calculated by a CAD tool that takes as input the Verilog netlist of the IC
( ) They are calculated during testing by the ATPG test equipment
( ) They are stored in the IC memory
( ) They are calculated by the place&route tool and saved in the SPEF files
( ) They are calculated by the probe station that injects them in the wafer

4) Can a design have more than one scan chain?

( ) Yes, but there will be more routing congestion
( ) Yes, and the test will be faster
( ) No
( ) Yes, but the test will be slower
( ) Yes but there will be more IO Pads

5) Which of the following Memories can be defined “Non Volatile” ?

( ) ROM
( ) SRAM
( ) NOR Flash
( ) DRAM
( ) Nand Flash
6) Can the standard 6T memory cell be used in Asynchronous (Non-Clocked) Memories?
( ) Yes, but it won’t be pipelined so it will be slower
( ) Yes, in all cases
( ) No, because the address needs to be saved in a register
( ) No, the 6T cell itself will not function without a clk

SECTION 7: Problem [10pts]

The text below contains a report from Cadence Encounter:

Total area of Standard cells: 229713.078 um^2

Total area of Standard cells (Subtracting Physical Cells): 130709.208 um^2
Total area of Macros: 160000.000 um^2
Total area of Blockages: 0.000 um^2
Total area of Pad cells: 0.000 um^2
Total area of Core: 465991.705 um^2
Total area of Chip: 480000.000 um^2
Effective Utilization: 9.1563e-01

Answer the following questions:

a) Does the Design contain any Filler / Fillercap cells (y/n) ? …………………………
b) What is the area taken by the power ring ? …………………………………………………
c) Does the design contain any hard Macro? …………………………………………………………..
d) Is this design a full chip or a block? ………………………………………………………………
e) Supposing the area of the NAND2 cell 0.8 um^2, what is the Kilogate Count of this design?
……………………………………….
 Solution of Problem One
NANDx2
NORx3

W=12

W=12
BUFx1

W=3 W=3

BUFx1
 NANDx2
NORx3
C=8
R=1/6
C=12
R=1/6 R=3
C=12+6
BUFx1
C=1 C=1 C=3
R=1/3 R=1/3

C=3 BUFx1

Note that PMOS resistance = 2/W, NMOS Resistance = 1/W,

Gate Capacitance=W, Diffusion capacitance=w (Unless shared as in pull-up)

Note: As the text specified Shared diffusion, the capacitance between the PMOS should be 12. The capacitance of the two
NMOS depends on the specific layout choices that are not visible in the schematic, so both options 3C and 6C are
considered acceptable in the correction, although this solution adopts 6C
 NANDx2
NORx3

R1=1/6
C1=12
R2=1/6 R3=3
C2=19 C3=15
BUFx1

BUFx1

Pull-Up (Same Best/Worst): R1C1 + R2*R2*C2 + (R1+R2+R3)*C3 =

= 1/6 *12 + 2/6 *19 + (18+2+1)/6 *15 = (12+38+315)/6= 60.88 RC

 NANDx2
NORx3

R2=3
C1=19 C2=15
BUFx1

R1=1/3

BUFx1

Pull-Down (Best): R1C1 + R2*R2*C2 =

Pull-Down (Worst): R1C1 + R2*R2*C2 =
= 1/6 *19 + (1+18)/6*15 = 50.66 RC
= 1/3 *19 + (9+1)/3 *15 = 19/3 + 150/3 = 56.33 RC
 Solution of Problem Two
Wire
R=1, C=2
1x

1x

1x
1x Wire:
R=1, C=2

1x

1x

Wire 2x
R=2, C=4
 Solution of Problem Two
Wire Until the output of the second set of buffers, all branches
R=1, C=2 Are equal so there is no point in calculating the delay before that.
1x Also, please note that in a buffer there is no electrical connection
between In and Out, so the Path in purple and the one in yellow are
1x COMPLETELY SEPARATED
Vdd
1x
1x R1=1
Wire: R2=1
R=1, C=2
1x C1=3+1 C2=1+6 (Wire+2 Buffers)

1x
Delay 1 (yellow)= Rise=Fall=best=Worst=
Wire 2x R1*C1 + (R1+R2)*C2 = 4+14 = 18RC
R=2, C=4
 Solution of Problem Two
Wire
Delay 3:
R=1, C=2
Rise=Fall=best=Worst=R1*C1 + (R1+R2)*C2 = 5+(3*8) = 29RC
1x

1x Note that to be precise the first stage of the buffer would have
same gate capacitance as IVx1=3RC (only second stage has 2x)
1x but students that used 6C won’t be penalized; in that case the
result would be 38RC)
1x
Wire: Vdd
R=1, C=2
1x
R1=1
1x R2=2

C1=3+2 C2=2+6 (wire + 2 buffers)

Wire 2x
R=2, C=4
MAX SKEW VALUE = 11 RC
 Solution of Problem 3
αi = Pi * !Pi
0.5 P1

0.5
P2

0.5 P3

0.5

P1=1-(.5 * .5) = 1-0.25 = 0.75 => A1=0.75*0.25 = 0.1875

P2=0.75*.5 = 0.375 => A2=0.375*0.625=0.234375
P3=(1-(.5*.625)) = 0.6875 => A3= 0.6875*0.3125 = 0.2148
 Solution of Question 1

VIA VIA
M2 M3 M2
2/3 2/3

(A) (B) M3

• Configuration (a) is illegal because adjacent metal are orthogonal in

standard P&R Practices
 Solution of Question 1
VIA
M2 M2 2/3

M3 M3

(A) (B)

• Configuration (b) is not convenient as due to the Via size the current will crowd at the periphery
causing a bad use of the Via surface. Configuration (a) offers a much better use of the Via area
and hence a lower equivalent resistance
 Solution of Question 2
x1 vdd vdd n2 n1 pmos w=Wmin
x2 vdd vdd n1 n2 pmos w=Wmin
x3 gnd b1 w n1 nmos w=X
x4 gnd b2 w n2 nmos w=X
x5 gnd gnd n2 n1 nmos w=Y n1 n2

x6 gnd gnd n1 n2 nmos w=Y

The circuit is a 6T cell, and a suggested dimensioning could be Y=4*Wmin , X=2*Wmin

QUESTION 2: Multiple Choice Questions [24 %]:
Note: In the following, there is more than one correct answer. 4% is awarded for each questions only if all answers are marked correctly
1) In which of the following Signoff checks it is necessary to take into account Cross-Talk Effects ?
( ) Power Analysis
( ) Hold Analysis
( ) Setup Analysis
( ) Power Integrity
( ) DRC
( ) LVS
2) What is the most common market for NOR Flash memories?
( ) USB Sticks
( ) SSD Drives
( ) Embedded memory macros
( ) Wireless communications
( ) Automotive Microcontrollers
3) When are ATPG test pattern calculated?
( ) They are calculated by a CAD tool that takes as input the Verilog netlist of the IC
( ) They are calculated during testing by the ATPG test equipment
( ) They are stored in the IC memory
( ) They are calculated by the place&route tool and saved in the SPEF files
( ) They are calculated by the probe station that injects them in the wafer
4) Can a design have more than one scan chain?
( ) Yes, but there will be more routing congestion
( ) Yes, and the test will be faster
( ) No
( ) Yes, but the test will be slower
( ) Yes but there will be more IO Pads
5) Which of the following Memories can be defined “Non Volatile” ?
( ) ROM
( ) SRAM
( ) NOR Flash
( ) DRAM
( ) Nand Flash
6) Can the standard 6T memory cell be used in Asynchronous (Non-Clocked) Memories?
( ) Yes, but it won’t be pipelined so it will be slower
( ) Yes, in all cases
( ) No, because the address needs to be saved in a register
( ) No, the 6T cell itself will not function without a clk
The text below contains a report from Cadence Encounter:
Total area of Standard cells: 229713.078 um^2
Total area of Standard cells (Subtracting Physical Cells): 130709.208 um^2
Total area of Macros: 160000.000 um^2
Total area of Blockages: 0.000 um^2
Total area of Pad cells: 0.000 um^2
Total area of Core: 465991.705 um^2
Total area of Chip: 480000.000 um^2
Effective Utilization: 9.1563e-01

Answer the following questions:

Does the Design contain any Filler / Fillercap cells (y/n) ? Yes, 229713.078 – 130709 um^2 are occupied by Fillers or
FillerCaps
What is the area taken by the power ring ? 480000 – 465991 = 14008 um^2
Does the design contain any Macro? Yes, 160 000 um^2 are occupied by hard macros (There is no way of knowing how
many).
Is this design a full chip or a block? The design is a block as it does not contain any IO Pads
Supposing the area of the NAND2 cell 0.8 um^2, what is the Kilogate Count of this design? 130709/0.8 =~ 163 Kgates (only
stdcells are used for Kgate count)