Part - A

1. For the given circuit slack = 0 then, Find clk to Q delay of FF1

2. Find the Maximum Clock frequency of the below Circuit? Both Registers are rise edge and
each buffer taking 1ns and each register taking 2ns and library setup time of R2 = 0.5 ns ?

3. Find the setup time and Hold slack for the below?

Clock period =5ns, each b1 & b2 has max =1.37 & min =0.78ns
Each b3, b4&b5 has max = 1.25 & min = 0.85ns
Each register delay max: 3.25 ns & min 2.85 ns
Library setup time of R2 = 1.5ns & Library hold time of R2 = 1ns
Combo delay, max = 5.5ns, min = 4.5 ns
4. For the circuit Show below, what is the maximum Frequency of operations?

1. are there any hold violations for FF2?

2. If yes how do you modify the circuit to avoid them?

5. Calculate the maximum time period and maximum clock frequency at which given circuit can
operate.

Can you operate the given circuit at same frequency you have calculated. If yes, then what
modifications are required in the design?
6. Calculate the metal area & antenna ratio for the below metals. Which of the following is fix for
the antenna violation

Consider three cases here:

In case-1 suppose metal-2 has length = 300um as shown in the above figure and width of metal
=1um. This metal wire is connected to the gate of a transistor. The transistor is having gate width =
3um and length = 0.6um.

In case-2 suppose the situation is same but the metal-2 is connected to 4 such transistors instead
of 1. calculate the antenna ratio?

7. There is the Floorplan with an area of 16 sqmm. Due to changes in RTL logic, added 2
standard cells logic blocks measuring of 2 sqmm each got added. And 7 sqmm memory
macros are added.
What should be the new floorplan area keeping utilization and other aspects are same
(core to dia area, spacing are same)
8. Calculate channel space between two macros that have 50 pins equally distributed in
M1,M2,M3,M4 layers and Pitch of these all four metal layers is 0.5 um?

9. In the figure below, three buffers, flipflops combinational circuits have two delays one
is min delay, and another is the delay after adding derating i.e., Max delay.
Consider time period = 8ns, Tsetup and Thold = 0.2ns
A). Find the setup slack (only setup)

Cell name Max Delay Min delay

Buffer1 0.70 0.60
Buffer2 0.65 0.55
Buffer3 0.75 0.45
Tcombo 3.6 2.5
Tclk to Q 0.6 0.48

10. Consider the below register 1 = positive edge triggered and register 2 is negative edge
triggered. Clock period = 10ns, each buffers delay = 1ns, each register delay = 2 ns, library
setup time & hold time of R2 = 0.5ns, derates values Max = 5%, Min = 2%
1. Calculate setup
11. Find the setup slack

R1 is Negative edge triggered and R2 is positive,

each b1 & b2 has max = 1.37ns

Combo delay max= 5.5ns

Each b3, b4, & b5 has max = 3.35

Library setup time of R1 = 1.5 ns and library hold time of R2 = 1ns

12) Find the hold slack (with without derates values)

R1 is Negative edge triggered and R2 is positive,

each b1 & b2 has min =0.75 ns

Combo delay min 4.5 ns

Each b3, b4, & b5 has min 2.85

Library setup time of R1 = 1.5 ns and library hold time of R2 = 1ns

12) . A std cell library contains a clock buffer with capacitance of 5ff & Output capacitance of 20ff.
There is a design with 64 flops that have input capacitance of 5ff.

Build a clock tree that symmetrically drives above flops?

Assume buffer delay as 0.25 ns & net delay as 0.125ns, what is the maximum latency on
your clock network?
Note: Assume net delay of 0.125 ns for every net segment from root to sink and in
between.

Part : B

1. How delay varies with different PVT conditions? Match the following below. ( )

V - Increases Delay
V – Decreases
T - Increases
T - Decreases

2. Select correct statements below for Low power implementation techniques for ASIC
physical design ( )
various techniques for saving the power with the help of supply voltage.

A) Multi VDD.
B) DVFS (dynamic voltage and frequency scaling)
 C) Multi Vt (implementing the design with a multi-threshold voltage standard cells library to
save power in the design).
D) Power gating (power shut off) (internal leakage power of the CMOS circuit can be reduced
by shutting down the block/module for a particular interval of time by applying a specific
signal.)

All the above

3. In multi VDD design, level shifters are used for ( )

A) High to low voltage level shifter (impact on timing is minimum)
B) Low to high voltage level shifter (It may cause higher switching current and reduce the noise
margin)
C) During the placement stage, special care needs to be taken for the low to high voltage level
shifter.
D) All the above

5. What is the total delay on the below circuit?

A) 12 times units
B) 4 times units
C) 16 times units
D) None of the above

6. The output delays are measured relatively to what type of signals. ( )

A) Input port signal that drives the path

B) Output port signal.
C) Clock signal.
 D) Any asynchronous signal.

7. What is total clock latency given maximum clock tree delay is 100ps and maximum clock delay
the clock source to the clock port is 150 ps ? ( )

A) 100 ps
B) 200 ps
C) 250 ps
D) 300 ps

8. Matching Design objects to constraints ( )

Match the objects on the left to best related constraints on the right

1. Pin A. Duty cycle

2. Net B. Vt type
3. cell c. Transistion
4. clock D.Timing Constraints

9.Consider the inverter circuit of Figure given below. VO1 is the output voltage of inverter I1, and
VI2 is the input voltage of inverter I2. Both inverters have the following characteristics: VDD = 5 V,
VIL = 1.35 V, VIH = 3.15 V, VOL = 0.33 V, and VOH = 3.84 V. What is the inverter low and high noise
margins? ( )

Solution

The inverter noise margins are:

NML = VIL − VOL = (1.35 V − 0.33 V) = 1.02 V,

NMH = VOH − VIH = (3.84 V − 3.15 V) = 0.69 V.

A) NML = 2.02v & NMH 0.89 V.

B) NML = 10.02v & NMH 10.69 V.
 C) NML = 8.02v & NMH 0.69 V.
D) NML = 1.02v & NMH 0.69 V.

19) For the given timing path. Three (3) clock cycles are required to propagate the data
from the start point to the end point of the path. Then how do you approach for the
timing calculations.

Ts =
Adder =
Tsetup
Total clk cycles

(A) set_multicycle_path 3 –setup –from FF1/cp -to FF2/D

set_multicycle_path 4 –hold –from FF1/cp -to FF2/D
(B) set_multicycle_path 2 –setup –from FF1/cp -to FF2/D
set_multicycle_path 3 –hold –from FF1/cp -to FF2/D
(C) set_False_path –from FF1 –to FF2
(D) set_multicycle_path 3 –setup –from FF1/cp -to FF2/D
 set_multicycle_path 2 –hold –from FF1/cp -to FF2/D

19. Imagine that you got responsibility that to write a specification of the next processer
design, What and all things you consider and how you write them based on the which
factors. ______________________
20. Which of the following is the latest technology processer. ( )

A) B)

C) D)

20. Which of the following metal layer has Maximum resistance?

a. Metal1

b. Metal2

c. Metal3

d. Metal4

21). To achieve better timing ____ cells are placed in the critical path.

a. HVT

b. LVT

c. RVT

d. SVT

22). Leakage power is inversely proportional to ___.

a. Frequency

b. Load Capacitance

c. Supply voltage

d. Threshold Voltage
23). Maximum current density of a metal is available in ___.

a. .lib

b. .v

c. .tf

d. .sdc

26.What is the effect of high drive strength buffer when added in long net?

a. Delay on the net increases

b. Capacitance on the net increases

c. Delay on the net decreases

d. Resistance on the net increases.

27.Pitch of the wire is ___.

a. Min width

b. Min spacing

c. Min width - min spacing

d. Min width + min spacing

Which of the following is adds up to the metal pitch ?

a. Min width

b. Min spacing

c. Min width - min spacing

d. Min width + min spacing

28.Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/inverters

b. Clock buff/inverters are slower than normal buff/inverters
c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare
to normal buff/inverters
d. Normal buff/inverters are having equal rise and fall times with high drive strengths
compare to Clock buff/inverters.

30.If the data is faster than the clock in Reg to Reg path ___ violation may come.
a. Setup
b. Hold
c. Both
d. None
31. The minimum height and width a cell can occupy in the design is called as ___.
a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell
32. Select all applicable Solutions to fix Antenna violation is ___.
a. Diode insertion
b. Shielding
c. Dummy buffer insertion
d. Double spacing
F , metal jumping

33. To avoid cross talk, the shielded net is usually connected to ___.
a. VDD
b. VSS
c. Both VDD and VSS
d. Clock