Compal La-5581p R2.0 Schematics PDF

A B C D E
ZZZ
PCB_LS5581P
Part Number = DA80000FB20
Compal confidential 1
Schematics Document
Mobile Penryn ULV singal/dual
2 core with Intel 2
Cantiga_GS45/GS40 +ICH9-M SFF

core logic
ULV core logic board 3
2009-07-23
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/02/20 Deciphered Date 2009/02/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LS-5581P 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, July 23, 2009 Sheet 1 of 30
A B C D E
A B C D E
1 1
2 2
3 3
4 4

Block Diagram
Custom LS-5581P 2.0
Date: Tuesday, July 21, 2009 Sheet 2 of 30
A B C D E
A
( O MEANS ON X MEANS OFF )

Voltage Rails
Symbol Note :
+B +5VALW +1.5V +5VS
+3VL +3VALW +3VS
+1.5VS : means Digital Ground
power
plane +0.75V
+VCCP
+CPU_CORE : means Analog Ground
@ : means just reserve , no build

CONN@ : means ME part.
State 45@ : means install after SMT.
SMBUS Control Table
SERIAL THERMAL
SOURCE INVERTER BATT EEPROM SENSOR SODIMM CLK CHIP MINI CARD LCD
S0 (CPU)
O O O O
S1
O O O O
SMB_EC_CK1
SMB_EC_DA1
KB926 X V V X X X X X
S3
O O O X
SMB_EC_CK2
SMB_EC_DA2
KB926 X X X V X X X X
SMB_CK_CLK1
S5 S4/AC
O O X X SMB_CK_DAT1 ICH9 X X X X V V V X
S5 S4/ Battery only LCD_CLK
O X X X LCD_DAT Cantiga
X X X X X X X V
S5 S4/AC & Battery
1
don't exist X X X X 1
Descrebtion Descrebtion Descrebtion
USB port 0 USB connector PCI-e port 0 SATA port 0 SATA HDD
USB port 1 BT Module PCI-e port 1 WLAN Conn. SATA port 1
USB port 2 cardreader PCI-e port 2 SATA port 2 WWAN/SSD
USB port 3 USB connector PCI-e port 3
USB port 4 WLAN Conn. PCI-e port 4
USB port 5 WWAN/SSD PCI-e port 5 LAN
USB port 6 USB connector
USB port 7 CMOS
USB port 8 Fingerprint
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS

DDR SO-DIMM 0 A0 10100000
CLOCK GENERATOR (EXT.) D2 11010010 Notes List
Custom LS-5581P 2.0
A
5 4 3 2 1
U1 U1 U1 U1 U1 U1 U1
CPU SU2700 CPU SU9600 CPU SU3500 CPU 743 CPU SU7300 CPU SU4100 CPU SU2300
2700@ 9600@ 3500@ 743@ 7300@ 4100@ 2300@
07/06 Add U1 SA00003BZ10 for 3500@

D D
07/23 Add U1 SA00003IA50 for 7300@
Add U1 SA00003I950 for 4100@ XDP_TDI +VCCP
Add U1 SA00003H060 for 2300@ XDP_DBRESET#
Add U1 SA00003JO60 for 743@ XDP_TDO
XDP_TDI R1 1 2 54.9_0402_1%
XDP_TMS R2 1 2 54.9_0402_1%
XDP_TMS
XDP_TDO R3 1 2 54.9_0402_1%
XDP_TRST#
XDP_TCK
XDP_TRST# R6 1 2 51_0402_1%
Place close to U1. +VCCP @ @ @
2
XDP_TCK R7 1 2 54.9_0402_1%
D9 D10 D11
<8> H_A#[3..16] This shall place near CPU
U1A PJDLC05_SOT23-3 PJDLC05_SOT23-3 PJDLC05_SOT23-3
H_A#3 P2 M4
H_A#4 A[3]# ADS# H_ADS# <8>
V4 A[4]# BNR# J5 H_BNR# <8>
H_A#5 W1 L5
A[5]# BPRI# H_BPRI# <8>
2
56_0402_5%
H_A#6 T4 A[6]#
ADDR GROUP 0
H_A#7 AA1 N5 R10
H_A#8 A[7]# DEFER# H_DEFER# <8>
AB4 F38 51_0402_1%
H_DRDY# <8>
1
H_A#9 A[8]# DRDY#
T2 A[9]# DBSY# J1 H_DBSY# <8> For ESD
R9
H_A#10 AC5
1
A[10]#
CONTROL
H_A#11 AD2 M2
H_A#12 A[11]# BR0# H_BR0# <8>
AD4 A[12]#
H_A#13 AA5 B40
C H_A#14 A[13]# IERR# C
AE5 A[14]# INIT# D8 H_INIT# <18>
H_A#15 AB2
H_A#16 A[15]#
AC1 A[16]# LOCK# N1 H_LOCK# <8>
<8> H_ADSTB#0 Y4 ADSTB[0]#
G5 H_RESET#
RESET# H_RESET# <8>
<8> H_REQ#0 R1 REQ[0]# RS[0]# K2 H_RS#0 <8>
0.1U_0402_16V4Z
<8> H_REQ#1 R5 REQ[1]# RS[1]# H4 H_RS#1 <8> 1
<8> H_REQ#2 U1 K4 H_RS#2 <8>
REQ[2]# RS[2]# C1046 @
<8> H_REQ#3 P4 L1 H_TRDY# <8>
REQ[3]# TRDY#
<8> H_REQ#4 W5
REQ[4]#
H2 2 For ESD
<8> H_A#[17..35] HIT# H_HIT# <8>
H_A#17 AN1 F2
A[17]# HITM# H_HITM# <8>
H_A#18 AK4
H_A#19 AG1
A[18]#
AY8 Add 0 ohm per EMI request.
A[19]# BPM[0]# +3VS
ADDR GROUP 1
H_A#20 AT4
A[20]# BPM[1]#
BA7 10/17
H_A#21 AK2 BA5
H_A#22 A[21]# BPM[2]#
AT2 AY2
H_A#23 A[22]# BPM[3]#
AH2 AV10
A[23]# PRDY#
XDP/ITP SIGNALS
0.1U_0402_16V4Z
H_A#24 AF4 AV2 1
H_A#25 A[24]# PREQ# XDP_TCK
AJ5 AV4
H_A#26 A[25]# TCK XDP_TDI C1034
AH4 AW7
H_A#27 A[26]# TDI XDP_TDO U7
AM4 AU1
H_A#28 A[27]# TDO XDP_TMS 2
AP4 AW5
H_A#29 A[28]# TMS XDP_TRST#
AR5 AV8
H_A#30 A[29]# TRST# XDP_DBRESET#
AJ1 J7 XDP_DBRESET# <19> 1 8 EC_SMB_CK2 <21>
H_A#31 A[30]# DBR# VDD SMCLK
AL1 H_PROCHOT# <28>
H_A#32 A[31]# H_THERMDA
AM2 2 7 EC_SMB_DA2 <21>
H_A#33 A[32]# Place Close to U1. +VCCP C1035 DP SMDATA
AU5
A[33]# THERMAL
H_A#34 AP2 1 2 H_THERMDC 3 6 R3051 2 10K_0402_5%
A[34]# DN ALERT# +3VS
H_A#35 AR1 D38 R22 1 2 68_0402_5% 2200P_0402_50V7K
A[35]# PROCHOT# H_THERMDA_R R23 H_THERMDA THERM#
<8> H_ADSTB#1 AN5 BB34 1 2 0_0402_5% 4 5
ADSTB[1]# THERMDA H_THERMDC_R R24 H_THERMDC THERM# GND
BD34 1 2 0_0402_5%
B THERMDC R306 B
<18> H_A20M# C7
A20M# H_THERMTRIP#
<18> H_FERR# D4 B10 H_THERMTRIP# <8,18> +3VS 1 2
FERR# THERMTRIP#
ICH
F10 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8

<18> H_IGNNE# IGNNE#
H_THERMDA, H_THERMDC routing together,
<18> H_STPCLK# F8 Address:100_1100
<18> H_INTR C9
STPCLK#
H CLK Trace width / Spacing = 10 / 10 mil
LINT0
<18> H_NMI C5 A35 CLK_CPU_BCLK <16>
LINT1 BCLK[0]
<18> H_SMI# E5 C35 CLK_CPU_BCLK# <16>
SMI# BCLK[1]
V2
RSVD01
Y2
RSVD02
AG5
RSVD03
RESERVED
AL5
RSVD04
J9
RSVD05 H_PROCHOT#
F4
RSVD06
0.1U_0402_16V4Z
H8 1
RSVD07
C1057 @
2
For EMI
PENRYN SFF_UFCBGA956
723@
07/06 Change U1 from SA000038J40 to SA000038J60
A A

Penryn(1/3)-AGTL+/ITP-XDP
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE
<8> H_D#[0..15] H_D#[32..47] <8>
U1B U1C
H_D#0 F40 AP44 H_D#32 F32 AB28
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
G43 AR43 G33 AD30
H_D#2 D[1]# D[33]# H_D#34 VCC[002] VCC[069]
E43 AH40 H32 AD28
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
J43 AF40 J33 Y26
D[3]# D[35]# VCC[004] VCC[071]
DATA GROUP 0
D H_D#4 H_D#36 D
H40 AJ43 K32 AB26
H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
H44 AG41 L33 AD26
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
G39 AF44 M32 AF30
DATA GROUP 2
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E41 AH44 N33 AF28
H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
L41 AM44 P32 AH30
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
K44 AN43 R33 AH28
H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
N41 AM40 T32 AF26
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
T40 AK40 U33 AH26
H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
M40 AG43 V32 AK30
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
G41 AP40 W33 AK28
H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
M44 AN41 Y32 AM30
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
L43 D[15]# D[47]# AL41 AA33 VCC[016] VCC[083] AM28
H_DSTBN#0 K40 AK44 H_DSTBN#2 AB32 AP30
<8> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <8> VCC[017] VCC[084]
H_DSTBP#0 J41 AL43 H_DSTBP#2 AC33 AP28
<8> H_DSTBP#0 H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2 H_DSTBP#2 <8> VCC[018] VCC[085]
<8> H_DINV#0 P40 DINV[0]# DINV[2]# AJ41 H_DINV#2 <8> AD32 VCC[019] VCC[086] AK26
<8> H_D#[16..31] H_D#[48..63] <8> AE33 VCC[020] VCC[087] AM26
AF32 VCC[021] VCC[088] AP26
H_D#16 P44 AV38 H_D#48 AG33 AT30
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
V40 D[17]# D[49]# AT44 AH32 VCC[023] VCC[090] AT28
H_D#18 V44 AV40 H_D#50 AJ33 AV30
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
AB44 D[19]# D[51]# AU41 AK32 VCC[025] VCC[092] AV28
H_D#20 R41 AW41 H_D#52 AL33 AY30
D[20]# D[52]# VCC[026] VCC[093]
DATA GROUP 1
H_D#21 W41 AR41 H_D#53 AM32 AY28
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
N43 BA37 AN33 AT26
DATA GROUP 3
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
U41 D[23]# D[55]# BB38 AP32 VCC[029] VCC[096] AV26
H_D#24 AA41 AY36 H_D#56 AR33 AY26
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
AB40 D[25]# D[57]# AT40 AT34 VCC[031] VCC[098] BB30
H_D#26 AD40 BC35 H_D#58 AT32 BB28 +VCCP
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099]
AC41 D[27]# D[59]# BC39 AU33 VCC[033] VCC[100] BD30
H_D#28 AA43 BA41 H_D#60 AV32
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
Y40 D[29]# D[61]# BB40 AY32 VCC[035] VCCP_001 J11 R27 1 2 0_0402_5%
H_D#30 Y44 BA35 H_D#62 BB32 E11 R28 1 2 0_0402_5%
C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP_002 C
T44 D[31]# D[63]# AU43 BD32 VCC[037] VCCP_003 G11 R29 1 2 0_0402_5%
H_DSTBN#1 U43 AY40 H_DSTBN#3 B28 J37 1
<8> H_DSTBN#1 H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 H_DSTBN#3 <8> VCC[038] VCCP_004
<8> H_DSTBP#1 W43 DSTBP[1]# DSTBP[3]# AY38 H_DSTBP#3 <8> B30 VCC[039] VCCP_005 K38
+
Change to 330u_R9,
H_DINV#1 R43 BC37 H_DINV#3 B26 L37 C5
<8> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <8>
D28
VCC[040] VCCP_006
N37 330U_D2E_2.5VM_R9
casue high
V_CPU_GTLREF COMP0 VCC[041] VCCP_007 limitation. 12/14
AW43 GTLREF COMP[0] AE43 D30 VCC[042] VCCP_008 P38
COMP1 2
E37 TEST1 MISC COMP[1] AD44 F30 VCC[043] VCCP_009 R37
TEST2 D40 AE1 COMP2 F28 U37
T8 TEST2 COMP[2] VCC[044] VCCP_010
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
C43 AF2 COMP3 H30 V38
TEST3 COMP[3] VCC[045] VCCP_011
1 R32
1 R33
AE41 H28 W37
TEST4 VCC[046] VCCP_012
1 R30
1 R31
TEST5 AY10 G7 D26 AA37
T9 TEST5 DPRSTP# H_DPRSTP# <8,18,28> VCC[047] VCCP_013
TEST6 AC43 B8 F26 AB38
T10 TEST6 DPSLP# H_DPSLP# <18> VCC[048] VCCP_014
C41 H_DPWR# <8> H26 AC37
DPWR# VCC[049] VCCP_015
<16> CPU_BSEL0 A37 E7 H_PWRGOOD <18> K30 AE37
BSEL[0] PWRGOOD VCC[050] VCCP_016
<16> CPU_BSEL1 C37 D10 H_CPUSLP# <8> K28
BSEL[1] SLP# H_PSI# VCC[051]
<16> CPU_BSEL2 B38 BD10 T11 M30 B34
BSEL[2] PSI# VCC[052] VCCA[01] +1.5VS
M28 D34
2
VCC[053] VCCA[02]
10U_0805_6.3V6M
0.01U_0402_16V7K
Near pin B34
PENRYN SFF_UFCBGA956 K26
Near pin D34

VCC[054]
Cause CPU core power change to M26
VCC[055] VID[0]
BD8 CPU_VID0 <28>
1 phase, and not need support P30 BC7 CPU_VID1 <28> 1 1
VCC[056] VID[1]
P28 BB10 CPU_VID2 <28>
the pin, leave it as TP. 10/02 VCC[057] VID[2] C6 C7
T30 BB8 CPU_VID3 <28>
VCC[058] VID[3]
layout note: Route TEST3 & TEST5 traces on Resistor placed within T28
VCC[059] VID[4]
BC5 CPU_VID4 <28> 2 2
V30 BB4
ground referenced layer to the TPs 0.5" of CPU pin.Trace V28
VCC[060] VID[5]
AY4
CPU_VID5 <28>
VCC[061] VID[6] CPU_VID6 <28>
should be at least 25 P26
VCC[062]
T26
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 mils away from any other V26
VCC[063]
BD12 VCCSENSE
VCC[064] VCCSENSE VCCSENSE <28>
toggling signal. Y30
VCC[065]
COMP[0,2] trace width is Y28
VCC[066] VSSSENSE
AB30 BC13 VSSSENSE <28>
18 mils. COMP[1,3] trace VCC[067] VSSSENSE
B
166 0 1 1 B
width is 4 mils. PENRYN SFF_UFCBGA956
200 0 0
Length match within 25 mils.
1
The trace width/space/other is
20/7/25.
266 0 0 0
+VCC_CORE
R34
1 2 VCCSENSE
+VCCP 100_0402_1%
R35
1
1 2 VSSSENSE
100_0402_1%
R36
1K_0402_1%
2
V_CPU_GTLREF
Close to CPU pin

1
R37
within 500mils.
A 2K_0402_1% A
2
Close to CPU pin AW43

within 500mils. Security Classification Compal Secret Data Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
Custom LS-5581P 2.0
5 4 3 2 1
A
B
C
D
5
5
BD28 AL37
VCC_101 VCCP_021
BB26 AN37
VCC_102 VCCP_022
BD26 AP38
VCC_103 VCCP_023
B22 B32
VCC_104 VCCP_024
B24 VCC_105 VCCP_025 C33
D22 VCC_106 VCCP_026 D32
D24 VCC_107 VCCP_027 E35
F24 VCC_108 VCCP_028 E33
F22 VCC_109 VCCP_029 F34
H24 VCC_110 VCCP_030 G35
H22 VCC_111 VCCP_031 F36
K24 VCC_112 VCCP_032 H36
K22 VCC_113 VCCP_033 J35
M24 VCC_114 VCCP_034 L35
M22 VCC_115 VCCP_035 N35
P24 VCC_116 VCCP_036 K36
P22 VCC_117 VCCP_037 R35
T24 VCC_118 VCCP_038 U35
T22 VCC_119 VCCP_039 P36
V24 VCC_120 VCCP_040 V36
V22 VCC_121 VCCP_041 W35
Y24 VCC_122 VCCP_042 AA35
Y22 VCC_123 VCCP_043 AC35
AB24 VCC_124 VCCP_044 AB36
AB22 VCC_125 VCCP_045 AE35
AD24 VCC_126 VCCP_046 AG35
AD22 VCC_127 VCCP_047 AJ35
AF24 VCC_128 VCCP_048 AF36
AF22 VCC_129 VCCP_049 AL35
AH24 VCC_130 VCCP_050 AN35
AH22 VCC_131 VCCP_051 AK36
AK24 VCC_132 VCCP_052 AP36
AK22 B12
VCC_133 VCCP_053
AM24 B14
4
4
VCC_134 VCCP_054
AM22 C13
VCC_135 VCCP_055
AP24 D12
VCC_136 VCCP_056
AP22 D14
VCC_137 VCCP_057
AT24 E13
VCC_138 VCCP_058
AT22 F14
VCC_139 VCCP_059
AV24 F12
VCC_140 VCCP_060
AV22 G13
VCC_141 VCCP_061
AY24 H14
VCC_142 VCCP_062
AY22 H12
VCC_143 VCCP_063
BB24 J13
VCC_144 VCCP_064
BB22 K14
VCC_145 VCCP_065
BD24 K12
VCC_146 VCCP_066
BD22 L13
VCC_147 VCCP_067
B16 L11
VCC_148 VCCP_068
B18 M14
VCC_149 VCCP_069
B20 N13
VCC_150 VCCP_070
D16 N11
VCC_151 VCCP_071
D18 K10
VCC_152 VCCP_072
F18 P14
VCC_153 VCCP_073
F16 P12
VCC_154 VCCP_074
H18 R13
VCC_155 VCCP_075
H16 R11
VCC_156 VCCP_076
D20 T14
VCC_157 VCCP_077
F20 U13
VCC_158 VCCP_078
H20 U11
VCC_159 VCCP_079
K18 V14
VCC_160 VCCP_080
K16 V12
VCC_161 VCCP_081
M18 W13
VCC_162 VCCP_082
M16 W11
VCC_163 VCCP_083
K20 P10
VCC_164 VCCP_084
M20 V10
VCC_165 VCCP_085
P18 Y14
VCC_166 VCCP_086
P16 AA13
Issued Date
VCC_167 VCCP_087
T18 AA11
VCC_168 VCCP_088
3
3
T16 AB14
VCC_169 VCCP_089
Security Classification
V18 AB12
VCC_170 VCCP_090
V16 AC13
VCC_171 VCCP_091
P20 AC11
VCC_172 VCCP_092
T20 AD14
VCC_173 VCCP_093
V20 AB10
VCC_174 VCCP_094
Y18 AE13
VCC_175 VCCP_095
Y16 AE11
VCC_176 VCCP_096
AB18 AF14
VCC_177 VCCP_097
AB16 AF12
VCC_178 VCCP_098
AD18 AG13
VCC_179 VCCP_099
AD16 AG11
VCC_180 VCCP_100
Y20 AH14
2006/02/20
VCC_181 VCCP_101
AB20 AJ13
VCC_182 VCCP_102
AD20 AJ11
VCC_183 VCCP_103
AF18 AF10
VCC_184 VCCP_104
AF16 AK14
VCC_185 VCCP_105
AH18 AK12
VCC_186 VCCP_106
AH16 AL13
VCC_187 VCCP_107
AF20 AL11
VCC_188 VCCP_108
AH20 AN13
VCC_189 VCCP_109
AK18 VCC_190 VCCP_110 AN11
AK16 VCC_191 VCCP_111 AP12
AM18 VCC_192 VCCP_112 AR13
AM16 VCC_193 VCCP_113 AR11
AP18 VCC_194 VCCP_114 AK10
AP16 VCC_195 VCCP_115 AP10
AK20 VCC_196 VCCP_116 AU13
AM20 VCC_197 VCCP_117 AU11
Compal Secret Data
Deciphered Date
AP20 VCC_198 VCCP_118 L9
AT18 VCC_199 VCCP_119 L7
AT16 VCC_200 VCCP_120 N9
AV18 VCC_201 VCCP_121 N7
AV16 VCC_202 VCCP_122 R9
AY18 R7
2
2
VCC_203 VCCP_123
AY16 VCC_204 VCCP_124 U9
AT20 VCC_205 VCCP_125 U7
AV20 VCC_206 VCCP_126 W9
AY20 VCC_207 VCCP_127 W7
BB18 VCC_208 VCCP_128 AA9
BB16 AA7
2009/02/20
VCC_209 VCCP_129
BD18 VCC_210 VCCP_130 AC9
BD16 AC7
VCC_211 VCCP_131
BB20 VCC_212 VCCP_132 AE9
BD20 VCC_213 VCCP_133 AE7

AM14 VCC_214 VCCP_134 AG9
AP14 VCC_215 VCCP_135 AG7
AT14 VCC_216 VCCP_136 AJ9
AV14 VCC_217 VCCP_137 AJ7
AY14 VCC_218 VCCP_138 AL9
BB14 VCC_219 VCCP_139 AL7
BD14 VCC_220 VCCP_140 AN9
AN7
Title
Date:
VCCP_141
+VCC_CORE
AF38 VCCP_017 VCCP_142 AR9

AG37 VCCP_018 VCCP_143 AR7
AJ37 VCCP_019 VCCP_144 A33
AK38 VCCP_020 VCCP_145 A13
+VCCP
+VCCP
Custom LS-5581P
U1F
Size Document Number
Tuesday, July 21, 2009

1
1
Sheet
Penryn(3/3)-Power
6
of
Compal Electronics, Inc.
30
Rev
2.0
A
B
C
D
5 4 3 2 1
U1D U1E +VCC_CORE Mid Frequence Decoupling

B42 VSS[001] VSS[082] AM36 G25 VSS_164 VSS_280 AA15
F44 VSS[002] VSS[083] AR35 G23 VSS_165 VSS_281 AC15
D44 VSS[003] VSS[084] AU35 G21 VSS_166 VSS_282 Y10
D42 VSS[004] VSS[085] AV34 J25 VSS_167 VSS_283 AD10
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
F42 VSS[005] VSS[086] AW35 J23 VSS_168 VSS_284 AH12
H42 VSS[006] VSS[087] AW33 J21 VSS_169 VSS_285 AE15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K42 VSS[007] VSS[088] AY34 L25 VSS_170 VSS_286 AG15
M42 VSS[008] VSS[089] AT36 L23 VSS_171 VSS_287 AJ15
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
P42 VSS[009] VSS[090] AV36 L21 VSS_172 VSS_288 AH10
T42 BA33 N25 AM12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VSS[010] VSS[091] VSS_173 VSS_289
V42 BC33 N23 AL15
VSS[011] VSS[092] VSS_174 VSS_290
Y42 BB36 N21 AN15
D VSS[012] VSS[093] VSS_175 VSS_291 D
AB42 BD36 R25 AR15
VSS[013] VSS[094] VSS_176 VSS_292
AD42 C27 R23 AM10
VSS[014] VSS[095] VSS_177 VSS_293
AF42 C29 R21 AT12
VSS[015] VSS[096] VSS_178 VSS_294
AH42 C31 U25 AV12
VSS[016] VSS[097] VSS_179 VSS_295
AK42 E29 U23 AW13
VSS[017] VSS[098] VSS_180 VSS_296
AM42 E27 U21 AW11
VSS[018] VSS[099] VSS_181 VSS_297
AP42 G29 W25 AY12
VSS[019] VSS[100] VSS_182 VSS_298
AY44 G27 W23 AU15
VSS[020] VSS[101] VSS_183 VSS_299
AV44 E31 W21 AW15
VSS[021] VSS[102] VSS_184 VSS_300
AT42 G31 AA25 AT10
VSS[022] VSS[103] VSS_185 VSS_301 +VCC_CORE
AV42 J29 AA23 BA13
VSS[023] VSS[104] VSS_186 VSS_302
AY42
BA43
VSS[024] VSS[105] J27
L29
AA21
AC25
VSS_187 VSS_303 BA11
BB12
High Frequence Decoupling
VSS[025] VSS[106] VSS_188 VSS_304
BB42 VSS[026] VSS[107] L27 AC23 VSS_189 VSS_305 BC11
C39 VSS[027] VSS[108] N29 AC21 VSS_190 VSS_306 BA15
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
E39 VSS[028] VSS[109] N27 AE25 VSS_191 VSS_307 BC15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
G37 VSS[029] VSS[110] J31 AE23 VSS_192 VSS_308 B6
H38 VSS[030] VSS[111] L31 AE21 VSS_193 VSS_309 D6
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
J39 VSS[031] VSS[112] N31 AG25 VSS_194 VSS_310 E9
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
L39 VSS[032] VSS[113] R29 AG23 VSS_195 VSS_311 F6
M38 VSS[033] VSS[114] R27 AG21 VSS_196 VSS_312 G9
N39 VSS[034] VSS[115] U29 AJ25 VSS_197 VSS_313 H6
R39 VSS[035] VSS[116] U27 AJ23 VSS_198 VSS_314 K8
T38 VSS[036] VSS[117] R31 AJ21 VSS_199 VSS_315 K6
U39 VSS[037] VSS[118] U31 AL25 VSS_200 VSS_316 M8
W39 VSS[038] VSS[119] W29 AL23 VSS_201 VSS_317 M6
Y38 VSS[039] VSS[120] W27 AL21 VSS_202 VSS_318 P8 6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.
AA39 VSS[040] VSS[121] W31 AN25 VSS_203 VSS_319 P6
AC39 VSS[041] VSS[122] AA29 AN23 VSS_204 VSS_320 T8
AD38 VSS[042] VSS[123] AA27 AN21 VSS_205 VSS_321 T6
AE39 VSS[043] VSS[124] AC29 AR25 VSS_206 VSS_322 V8
AG39 VSS[044] VSS[125] AC27 AR23 VSS_207 VSS_323 V6
C C
AH38 VSS[045] VSS[126] AA31 AR21 VSS_208 VSS_324 U5
AJ39 VSS[046] VSS[127] AC31 AU25 VSS_209 VSS_325 Y8
AL39 VSS[047] VSS[128] AE29 AU23 VSS_210 VSS_326 Y6
AM38 AE27 AU21 AB8
AN39
AR39
VSS[048]
VSS[049]
VSS[129]
VSS[130] AG29
AG27
AW25
AW23
VSS_211
VSS_212
VSS_327
VSS_328 AB6
AD8
ESR <= 1.5m ohm
VSS[050] VSS[131] VSS_213 VSS_329
AR37 VSS[051] VSS[132] AJ29 AW21 VSS_214 VSS_330 AD6
AT38 AJ27 BA25 AF8
AU39
VSS[052]
VSS[053]
VSS[133]
VSS[134]
AE31 BA23
VSS_215
VSS_216
VSS_331
VSS_332
AF6 Near CPU CORE regulator
AU37 AG31 BA21 AH8
VSS[054] VSS[135] VSS_217 VSS_333
AW39 AJ31 BC25 AH6
VSS[055] VSS[136] VSS_218 VSS_334
AW37 AL29 BC23 AK8
VSS[056] VSS[137] VSS_219 VSS_335 +VCC_CORE
BA39 AL27 BC21 AK6
VSS[057] VSS[138] VSS_220 VSS_336
BC41 AN29 C17 AM8
VSS[058] VSS[139] VSS_221 VSS_337
BD40 AN27 C19 AM6
VSS[059] VSS[140] VSS_222 VSS_338
BD38 AL31 E19 AP8
VSS[060] VSS[141] VSS_223 VSS_339
B36 AN31 E17 AP6
VSS[061] VSS[142] VSS_224 VSS_340
220U_D2_2VK_R9
220U_D2_2VK_R9
220U_D2_2VK_R9
H34 AR29 G19 AT8 1 1 1
VSS[062] VSS[143] VSS_225 VSS_341
C56
C57
C58
D36 AR27 G17 AT6
VSS[063] VSS[144] VSS_226 VSS_342 + + +
K34 AR31 J19 AU9
VSS[064] VSS[145] VSS_227 VSS_343
M34 AU29 J17 AV6
VSS[065] VSS[146] VSS_228 VSS_344
M36 AU27 L19 AU7
VSS[066] VSS[147] VSS_229 VSS_345 2 2 2
P34 AW29 L17 AW9
VSS[067] VSS[148] VSS_230 VSS_346
T34 AW27 N19 AY6
VSS[068] VSS[149] VSS_231 VSS_347
V34 AU31 N17 BA9
VSS[069] VSS[150] VSS_232 VSS_348
T36 AW31 R19 BB6
VSS[070] VSS[151] VSS_233 VSS_349
Y34 BA29 R17 BC9
VSS[071] VSS[152] VSS_234 VSS_350
AB34 BA27 U19 BD6
VSS[072] VSS[153] VSS_235 VSS_351
AD34 BC29 U17 B4
VSS[073] VSS[154] VSS_236 VSS_352
Y36 BC27 W19 C3
VSS[074] VSS[155] VSS_237 VSS_353
AD36
VSS[075] VSS[156]
BA31 W17
VSS_238 VSS_354
E3 Del C37 to improve power plan. 6/14
AF34 BC31 AA19 G3
B VSS[076] VSS[157] VSS_239 VSS_355 B
AH34 C21 AA17 J3
VSS[077] VSS[158] VSS_240 VSS_356
AH36 C23 AC19 L3
VSS[078] VSS[159] VSS_241 VSS_357
AK34 C25 AC17 N3
VSS[079] VSS[160] VSS_242 VSS_358
AM34 E25 AE19 R3
VSS[080] VSS[161] VSS_243 VSS_359
AP34 E23 AE17 U3
VSS[081] VSS[162] VSS_244 VSS_360
E21 AG19 W3
VSS[163] VSS_245 VSS_361
AG17 AA3
VSS_246 VSS_362
AJ19 AC3
PENRYN SFF_UFCBGA956 VSS_247 VSS_363
AJ17 AE3
VSS_248 VSS_364
AL19 AG3
VSS_249 VSS_365
AL17 AJ3
VSS_250 VSS_366 +VCCP
AN19 AL3
VSS_251 VSS_367
AN17 AN3
VSS_252 VSS_368
AR19 AR3
VSS_253 VSS_369
AR17 AU3
VSS_254 VSS_370
AU19 AW3
VSS_255 VSS_371
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AU17 BA3 1 1 1 1 1 1 1 1 1 1 1 1
VSS_256 VSS_372
AW19 BC3
VSS_257 VSS_373
AW17 D2
VSS_258 VSS_374
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
BA19 E1
VSS_259 VSS_375 2 2 2 2 2 2 2 2 2 2 2 2
BA17 G1
VSS_260 VSS_376
BC19 AW1
VSS_261 VSS_377
BC17 BA1
VSS_262 VSS_378
C11 BB2
VSS_263 VSS_379
C15 A41
VSS_264 VSS_380
E15 A39
VSS_265 VSS_381
G15 A29
VSS_266 VSS_382
H10 A27
VSS_267 VSS_383
M12 A31
VSS_268 VSS_384
J15 A25
VSS_269 VSS_385
L15 A23
VSS_270 VSS_386
N15 VSS_271 VSS_387 A21
A A
M10 VSS_272 VSS_388 A19
T12 VSS_273 VSS_389 A17
R15 VSS_274 VSS_390 A11
U15 VSS_275 VSS_391 A15
W15 VSS_276 VSS_392 A7
T10 VSS_277 VSS_393 A5
Y12 VSS_278 VSS_394 A9
AD12 BD4
VSS_279 VSS_395 Security Classification Compal Secret Data Compal Electronics, Inc.
Penryn(3/3)-GND/Bypass
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
H_A#[3..35] <4> U3B

<5> H_D#[0..63] U3A
L15 H_A#3 J43
H_A#_3 T12 RSVD1
H_D#0 J7 B14 H_A#4 L43 BB32 M_CLK_DDR0 <14>
H_D#_0 H_A#_4 T13 RSVD2 SA_CK_0
H_D#1 H6 C15 H_A#5 J41 BA25
DDR CLK/ CONTROL/COMPENSATION

H_D#_1 H_A#_5 T14 RSVD3 SA_CK_1 M_CLK_DDR1 <14>
H_D#2 L11 D12 H_A#6 L41 BA33 M_CLK_DDR2 <15>
H_D#_2 H_A#_6 T15 RSVD4 SB_CK_0
H_D#3 J3 F14 H_A#7 AN11 BA23 M_CLK_DDR3 <15>
H_D#_3 H_A#_7 T16 RSVD5 SB_CK_1
H_D#4 H4 G17 H_A#8 AM10
H_D#_4 H_A#_8 T17 RSVD6
H_D#5 G3 B12 H_A#9 Add them for Boundary Scan. 10/23 AK10 BA31
H_D#_5 H_A#_9 T18 RSVD7 SA_CK#_0 M_CLK_DDR#0 <14>
H_D#6 K10 J15 H_A#10 AL11 BC25
H_D#_6 H_A#_10 T19 RSVD8 SA_CK#_1 M_CLK_DDR#1 <14>
H_D#7 K12 D16 H_A#11 F12 BC33
H_D#_7 H_A#_11 T20 RSVD9 SB_CK#_0 M_CLK_DDR#2 <15>
RSVD
H_D#8 L1 C17 H_A#12 R38 1 2 @ 1K_0402_5% TCK AN45 BB24
H_D#_8 H_A#_12 RSVD10 SB_CK#_1 M_CLK_DDR#3 <15>
H_D#9 M10 D14 H_A#13 R39 1 2 @ 4.7K_0402_5% TDI AP44
H_D#10 H_D#_9 H_A#_13 H_A#14 R40 @ 4.7K_0402_5% TDO RSVD11
M6 K16 1 2 AT44 BC35 DDR_CKE0_DIMMA <14>
H_D#11 H_D#_10 H_A#_14 H_A#15 R41 @1K_0402_5% TMS RSVD12 SA_CKE_0
N11 F16 +3VS 1 2 AN47 BE33 DDR_CKE1_DIMMA <14>
H_D#12 H_D#_11 H_A#_15 H_A#16 RSVD13 SA_CKE_1
L7 B16 T21 C27 BE37 DDR_CKE2_DIMMB <15>
H_D#13 H_D#_12 H_A#_16 H_A#17 RSVD14 SB_CKE_0
D K6 C21 T22 D30 BC37 DDR_CKE3_DIMMB <15> D
H_D#14 H_D#_13 H_A#_17 H_A#18 RSVD15 SB_CKE_1
M4 D18
H_D#15 H_D#_14 H_A#_18 H_A#19
K4 J19 T23 J9 BK18 DDR_CS0_DIMMA# <14>
H_D#16 H_D#_15 H_A#_19 H_A#20 RSVD17 SA_CS#_0
P6 J21 BK16 DDR_CS1_DIMMA# <14>
H_D#17 H_D#_16 H_A#_20 H_A#21 SA_CS#_1
W9 B18 BE23 DDR_CS2_DIMMB# <15>
H_D#18 H_D#_17 H_A#_21 H_A#22 SB_CS#_0
V6 D22 T24 AW42 BC19 DDR_CS3_DIMMB# <15>
H_D#_18 H_A#_22 RSVD20 SB_CS#_1
0.01U_0402_25V7K
2.2U_0603_6.3V4Z
H_D#19 V2 G19 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
P10 J17 BJ17 M_ODT0 <14>
H_D#21 H_D#_20 H_A#_24 H_A#25 +1.5V SA_ODT_0
W7 L21 BJ19 M_ODT1 <14>
H_D#22 H_D#_21 H_A#_25 H_A#26 SA_ODT_1 +1.5V
N9 L19 BB20 BC17 M_ODT2 <15>
H_D#23 H_D#_22 H_A#_26 H_A#27 RSVD22 SB_ODT_0
P4 G21 1 1 T26 BE19 BE17 M_ODT3 <15>
H_D#_23 H_A#_27 RSVD23 SB_ODT_1
1
C71
C72
H_D#24 U9 D20 H_A#28 BF20
H_D#_24 H_A#_28 T27 RSVD24
H_D#25 V4 K22 H_A#29 BF18 BL25 SMRCOMP R43 1 2 80.6_0402_1%
H_D#_25 H_A#_29 T28 RSVD25 SM_RCOMP
H_D#26 U1 F18 H_A#30 R42 BK26 SMRCOMP# R44 1 2 80.6_0402_1%
H_D#27 H_D#_26 H_A#_30 H_A#31 2 2 1K_0402_1% SM_RCOMP#
W3 H_D#_27 H_A#_31 K20
H_D#28 V10 F20 H_A#32 BK32 SMRCOMP_VOH
2
H_D#29 H_D#_28 H_A#_32 H_A#33 SMRCOMP_VOH SM_RCOMP_VOH SMRCOMP_VOL
U7 H_D#_29 H_A#_33 F22 SM_RCOMP_VOL BL31 1 2 1.5V_PGOOD <25>
H_D#30 W11 B20 H_A#34 R429 0_0402_5%
H_D#_30 H_A#_34
1
H_D#31 U11 A19 H_A#35 BC51 DDR3_NB_REF
H_D#_31 H_A#_35 R45 SM_VREF @1
H_D#32 AC11 H_D#_32 SM_PWROK AY37 SM_PWROK 2 R46 10K_0402_1%
H_D#33 AC9 F10 3.01K_0402_1% BH20 SM_REXT 1 2 R47 499_0402_1%
H_D#_33 H_ADS# H_ADS# <4> SM_REXT
H_D#34 Y4 A15 BA37
HOST
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4> SM_DRAMRST# SM_DRAMRST# <14,15>
H_D#35 Y10 C19 H_ADSTB#1 <4>
2
H_D#36 H_D#_35 H_ADSTB#_1 SMRCOMP_VOL
AB6 H_D#_36 H_BNR# C9 H_BNR# <4> DPLL_REF_CLK B42 CLK_MCH_DREFCLK <16>
H_D#37 AA9 B8 D42
H_D#_37 H_BPRI# H_BPRI# <4> DPLL_REF_CLK# CLK_MCH_DREFCLK# <16>
1
0.01U_0402_25V7K
2.2U_0603_6.3V4Z
H_D#38 AB10 C11 B50
H_D#_38 H_BREQ# H_BR0# <4> DPLL_REF_SSCLK MCH_SSCDREFCLK <16>
H_D#39 AA1 E5 1 1 R48 D50
H_D#_39 H_DEFER# H_DEFER# <4> DPLL_REF_SSCLK# MCH_SSCDREFCLK# <16>
H_D#40 AC3 D6 1K_0402_1%
H_D#_40 H_DBSY# H_DBSY# <4>
C73
C74
H_D#41 AC7 AH10 R49
H_D#_41 HPLL_CLK CLK_MCH_BCLK <16> PEG_CLK CLK_MCH_3GPLL <16>
H_D#42 AD12 AJ11 P50
CLK_MCH_BCLK# <16> CLK_MCH_3GPLL# <16>
2
H_D#43 H_D#_42 HPLL_CLK# 2 2 PEG_CLK#
AB4 G11
CLK
H_D#_43 H_DPWR# H_DPWR# <5>
H_D#44 Y6 H2
H_D#_44 H_DRDY# H_DRDY# <4>
H_D#45 AD10 C7
H_D#_45 H_HIT# H_HIT# <4>
H_D#46 AA11 F8 AG55
H_D#_46 H_HITM# H_HITM# <4> DMI_RXN_0 DMI_TXN0 <19>
H_D#47 AB2 A11 AL49
C H_D#_47 H_LOCK# H_LOCK# <4> DMI_RXN_1 DMI_TXN1 <19> C
H_D#48 AD4 D8 AH54
H_D#_48 H_TRDY# H_TRDY# <4> DMI_RXN_2 DMI_TXN2 <19>
H_D#49 AE7 AL47
H_D#_49 DMI_RXN_3 DMI_TXN3 <19>
H_D#50 AD2
H_D#51 H_D#_50
AD6 H_D#_51 DMI_RXP_0 AG53 DMI_TXP0 <19>
H_D#52 AE3 K26 AK50
H_D#_52 <16> MCH_CLKSEL0 CFG_0 DMI_RXP_1 DMI_TXP1 <19>
H_D#53 AG9 L9 G23 AH52
H_D#_53 H_DINV#_0 H_DINV#0 <5> <16> MCH_CLKSEL1 CFG_1 DMI_RXP_2 DMI_TXP2 <19>
H_D#54 AG7 N7 G25 AL45
H_D#_54 H_DINV#_1 H_DINV#1 <5> <16> MCH_CLKSEL2 CFG_2 DMI_RXP_3 DMI_TXP3 <19>
H_D#55 AE11 AA7 J25
H_D#_55 H_DINV#_2 H_DINV#2 <5> T30 CFG_3
H_D#56 AK6 AG3 L25 AG49
H_D#_56 H_DINV#_3 H_DINV#3 <5> T31 CFG_4 DMI_TXN_0 DMI_RXN0 <19>
H_D#57 AF6 L27 AJ49
H_D#_57 <10> CFG5 CFG_5 DMI_TXN_1 DMI_RXN1 <19>
H_D#58 AJ9 K2 F24 AJ47
H_D#_58 H_DSTBN#_0 H_DSTBN#0 <5> <10> CFG6 CFG_6 DMI_TXN_2 DMI_RXN2 <19>
H_D#59 AH6 N3 D24 AG47
H_D#_59 H_DSTBN#_1 H_DSTBN#1 <5> <10> CFG7 CFG_7 DMI_TXN_3 DMI_RXN3 <19>
H_D#60 AF12 AA3 D26
DMI
H_D#_60 H_DSTBN#_2 H_DSTBN#2 <5> T32 CFG_8
CFG
H_D#61 AH4 AF4 J23 AF50
H_D#_61 H_DSTBN#_3 H_DSTBN#3 <5> <10> CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 <19>
H_D#62 AJ7 B26 AH50
H_D#_62 <10> CFG10 CFG_10 DMI_TXP_1 DMI_RXP1 <19>
H_D#63 AE9 L3 A23 AJ45
H_D#_63 H_DSTBP#_0 H_DSTBP#0 <5> T33 CFG_11 DMI_TXP_2 DMI_RXP2 <19>
M2 H_DSTBP#1 <5> <10> CFG12 C23 AG45 DMI_RXP3 <19>
H_DSTBP#_1 CFG_12 DMI_TXP_3
Y2 H_DSTBP#2 <5> <10> CFG13 B24
H_SWNG H_DSTBP#_2 CFG_13
B6 AF2 H_DSTBP#3 <5> T34 B22
H_RCOMP H_SWING H_DSTBP#_3 CFG_14
D4 T35 K24
H_RCOMP CFG_15
J13 H_REQ#0 <4> <10> CFG16 C25
H_REQ#_0 CFG_16
GRAPHICS VID
L13 H_REQ#1 <4> T36 L23
H_REQ#_1 CFG_17
C13 H_REQ#2 <4> T37 L33
H_REQ#_2 CFG_18
G13 H_REQ#3 <4> <10> CFG19 K32
H_REQ#_3 CFG_19
<4> H_RESET# J11 G15 H_REQ#4 <4> <10> CFG20 K34 G33
H_CPURST# H_REQ#_4 CFG_20 GFX_VID_0
<5> H_CPUSLP# G9 G37
H_CPUSLP# GFX_VID_1
F4 H_RS#0 <4> F38
H_RS#_0 GFX_VID_2
F2 H_RS#1 <4> F36
H_RS#_1 GFX_VID_3
G7 H_RS#2 <4> <19> PM_BMBUSY# J35 G35
H_RS#_2 PM_SYNC# GFX_VID_4
L17 <5,18,28> H_DPRSTP# F6
H_VREF H_AVREF PM_EXTTS#0 PM_DPRSTP#
K18 <14> PM_EXTTS#0 J39
H_DVREF PM_EXT_TS#_0
PM
PM_EXTTS#1 L39
<15> PM_EXTTS#1 PM_EXT_TS#_1
Trace < = 500mils CANTIGA GMCH SFF_FCBGA1363 R49 1 2 0_0402_5% AY39 G39
<19,21,28> PM_PWROK PWROK GFX_VR_EN +VCCP
layout note: R50 1 2 100_0402_1% BB18
<17,21> PLT_RST# RSTIN#
B <4,18> H_THERMTRIP# 1 2 K28 B
R51 0_0402_5% THERMTRIP#
Route H_SCOMP and H_SCOMP# with trace width, <19,28> PM_DPRSLPVR K36
DPRSLPVR
1
spacing and impedance (55 ohm) same as FSB data layout note:
Add R428 in 9/26
C75
AK52 R52
CL_CLK CL_CLK0 <19>
traces Place them close to U4 pin BC51. 1 CL_DATA
AK54 CL_DATA0 <19>
1K_0402_1%
A7 AW40 M_PWROK <19>
NC_1 CL_PWROK
ME
A49 AL53 CL_RST# <19>
2
+1.5V NC_2 CL_RST#
@ 0.1U_0402_16V4Z
Layout Note: Layout Note: V_DDR_MCH_REF trace 2
A52
NC_3 CL_VREF
AL55 CL_VREF
width and spacing is 20/20. A54
H_RCOMP / H_VREF / H_SWNG NC_4
1
B54 1
NC_5
1
trace width and spacing is 10/20 D55 C76 R53

R54 NC_6
G55 F34 T38 499_0402_1%
10K_0402_1% NC_7 DDPC_CTRLCLK
NC
BE55 F32 0.1U_0402_16V4Z
NC_8 DDPC_CTRLDATA T39 2
BH55 B38 HDMICLK <21>
2
+VCCP NC_9 SDVO_CTRLCLK
BK55 A37
MISC
HDMIDAT <21>
2
+VCCP DDR3_NB_REF NC_10 SDVO_CTRLDATA

BK54 C31 CLKREQ#_B <16>
NC_11 CLKREQ#
BL54 K42 MCH_ICH_SYNC# <19>
NC_12 ICH_SYNC#
1K_0402_1%
221_0603_1%
C77
0.1U_0402_16V4Z
BL52
NC_13
1
1 BL49
R55 R56 R57 NC_14 TSATN# R58
BL7 D10 1 2 54.9_0402_1% +VCCP
10K_0402_1% NC_15 TSATN#
BL4
NC_16
BL2
2 NC_17
BK2
2
H_VREF H_RCOMP H_SWNG NC_18

BK1
NC_19
BH1
NC_20
24.9_0402_1%
R59
0.1U_0402_16V4Z
BE1
NC_21
1
1
100_0402_1%
0.1U_0402_16V4Z
1 1 G1 C29 HDA_BITCLK_NB <21>

C78 R60 R61 C79 NC_22 HDA_BCLK R313
B30 HDA_RST#_NB <21>
HDA_RST#
2K_0402_1%
HDA
D28 HDA_SDIN2_NB 1 2
HDA_SDI HDA_SDIN2 <18>
+3VS A27
2 2 HDA_SDO HDA_SDOUT_NB <21>
B28 33_0402_5%
HDA_SYNC_NB <21>
2
HDA_SYNC
PM_EXTTS#0 R62 1 2 10K_0402_5%
@ Near B6 pin PM_EXTTS#1 R63 1 2 10K_0402_5%
A A
within 100 mils from NB CANTIGA GMCH SFF_FCBGA1363
Del R48. 9/27
U3

NB_GS45 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(1/6)-AGTL/DMI/DDR
GS45@ Size Document Number Rev
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
D D
<14> DDR_A_D[0..63] <15> DDR_B_D[0..63]

U3D U3E
DDR_A_D0 AP46 BC21 DDR_B_D0 AP54 BJ13
DDR_A_D1 SA_DQ_0 SA_BS_0 DDR_A_BS0 <14> DDR_B_D1 SB_DQ_0 SB_BS_0 DDR_B_BS0 <15>
AU47 BJ21 DDR_A_BS1 <14> AM52 BK12 DDR_B_BS1 <15>
DDR_A_D2 SA_DQ_1 SA_BS_1 DDR_B_D2 SB_DQ_1 SB_BS_1
AT46 BJ41 DDR_A_BS2 <14> AR55 BK38 DDR_B_BS2 <15>
DDR_A_D3 SA_DQ_2 SA_BS_2 DDR_B_D3 SB_DQ_2 SB_BS_2
AU49 AV54
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AR45 BH22 DDR_A_RAS# <14> AM54
DDR_A_D5 SA_DQ_4 SA_RAS# DDR_B_D5 SB_DQ_4
AN49 BK20 DDR_A_CAS# <14> AN53 BE21 DDR_B_RAS# <15>
DDR_A_D6 SA_DQ_5 SA_CAS# DDR_B_D6 SB_DQ_5 SB_RAS#
AV50 BL15 DDR_A_WE# <14> AT52 BH14 DDR_B_CAS# <15>
DDR_A_D7 SA_DQ_6 SA_WE# DDR_B_D7 SB_DQ_6 SB_CAS#
AP50 AU53 BK14 DDR_B_WE# <15>
DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
AW47 SA_DQ_8 AW53 SB_DQ_8
DDR_A_D9 BD50 DDR_B_D9 AY52
AW49 SA_DQ_10 DDR_A_DM[0..7] <14> BB52 SB_DQ_10
DDR_A_D11 BA49 AT50 DDR_A_DM0 DDR_B_D11 BC53
SA_DQ_11 SA_DM_0 SB_DQ_11 DDR_B_DM[0..7] <15>
DDR_A_D12 BC49 BB50 DDR_A_DM1 DDR_B_D12 AV52 AP52 DDR_B_DM0
DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
AV46 SA_DQ_13 SA_DM_2 BB46 AW55 SB_DQ_13 SB_DM_1 AY54
DDR_A_D14 BA47 BE39 DDR_A_DM3 DDR_B_D14 BD52 BJ49 DDR_B_DM2
AY50 SA_DQ_15 SA_DM_4 BB12 BC55 SB_DQ_15 SB_DM_3 BJ43
A
DDR_A_D16 BF46 BE7 DDR_A_DM5 DDR_B_D16 BF54 BH12 DDR_B_DM4
BC47 SA_DQ_17 SA_DM_6 AV10 BE51 SB_DQ_17 SB_DM_5 BD2
DDR_A_D18 BF50 AR9 DDR_A_DM7 DDR_B_D18 BH48 AY2 DDR_B_DM6
B
DDR_A_D19 SA_DQ_18 SA_DM_7 DDR_B_D19 SB_DQ_18 SB_DM_6 DDR_B_DM7
BF48 SA_DQ_19 DDR_A_DQS[0..7] <14> BK48 SB_DQ_19 SB_DM_7 AJ3
DDR_A_D20 BC43 AR47 DDR_A_DQS0 DDR_B_D20 BE53
SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] <15>
MEMORY
DDR_A_D21 BE49 BA45 DDR_A_DQS1 DDR_B_D21 BH52 AR53 DDR_B_DQS0
DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
BA43 SA_DQ_22 SA_DQS_2 BE45 BK46 SB_DQ_22 SB_DQS_1 BA53
DDR_A_D23 BE47 BC41 DDR_A_DQS3 DDR_B_D23 BJ47 BH50 DDR_B_DQS2
MEMORY
BF42 SA_DQ_24 SA_DQS_4 BC13 BL45 SB_DQ_24 SB_DQS_3 BK42
DDR_A_D25 BC39 BB10 DDR_A_DQS5 DDR_B_D25 BJ45 BH8 DDR_B_DQS4
BF44 SA_DQ_26 SA_DQS_6 BA7 BL41 SB_DQ_26 SB_DQS_5 BB2
DDR_A_D27 BF40 AN7 DDR_A_DQS7 DDR_B_D27 BH44 AV2 DDR_B_DQS6
DDR_A_D28 SA_DQ_27 SA_DQS_7 DDR_A_DQS#0 DDR_A_DQS#[0..7] <14> DDR_B_D28 SB_DQ_27 SB_DQS_6 DDR_B_DQS7
BB40 SA_DQ_28 SA_DQS#_0 AR49 BH46 SB_DQ_28 SB_DQS_7 AM2 DDR_B_DQS#[0..7] <15>
C DDR_A_D29 DDR_A_DQS#1 DDR_B_D29 DDR_B_DQS#0 C
BE43 SA_DQ_29 SA_DQS#_1 AW45 BK44 SB_DQ_29 SB_DQS#_0 AT54
DDR_A_D30 BF38 BC45 DDR_A_DQS#2 DDR_B_D30 BK40 BB54 DDR_B_DQS#1
DDR_A_D31 SA_DQ_30 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D31 SB_DQ_30 SB_DQS#_1 DDR_B_DQS#2
BE41 SA_DQ_31 SA_DQS#_3 BA41 BJ39 SB_DQ_31 SB_DQS#_2 BJ51
DDR_A_D32 BA15 BA13 DDR_A_DQS#4 DDR_B_D32 BK10 BH42 DDR_B_DQS#3
BE11 BA11 BH10 BK8
SYSTEM

BE15 SA_DQ_34 SA_DQS#_6 BA9 BK6 SB_DQ_34 SB_DQS#_5 BC3
DDR_A_D35 BF14 AN9 DDR_A_DQS#7 DDR_B_D35 BH6 AW3 DDR_B_DQS#6
DDR_A_D36 SA_DQ_35 SA_DQS#_7 DDR_B_D36 SB_DQ_35 SB_DQS#_6 DDR_B_DQS#7
SYSTEM
BB14 DDR_A_MA[0..14] <14> BJ9 AN3
DDR_A_D37 SA_DQ_36 DDR_A_MA0 DDR_B_D37 SB_DQ_36 SB_DQS#_7
BC15 BC23 BL11 DDR_B_MA[0..14] <15>
DDR_A_D38 SA_DQ_37 SA_MA_0 DDR_A_MA1 DDR_B_D38 SB_DQ_37 DDR_B_MA0
BE13 BF22 BG5 BJ15
DDR_A_D39 SA_DQ_38 SA_MA_1 DDR_A_MA2 DDR_B_D39 SB_DQ_38 SB_MA_0 DDR_B_MA1
BF16 BE31 BJ5 BJ33
BF10 BC31 BG3 BH24
BC11 BH26 BF4 BA17
BF8 BJ35 BD4 BF36
BG7 BB34 BA3 BH36
BC7 BH32 BE5 BF34
BC9 BB26 BF2 BK34
DDR
BD6 BF32 BB4 BJ37

BF12 BA21 AY4 BH40
AV6 BG25 BA1 BH16
DDR
BB6 BH34 AP2 BK36
AW7 BH18 AU1 BH38
AY6 BE25 AT2 BJ11
DDR_A_D52 SA_DQ_51 SA_MA_14 DDR_B_D52 SB_DQ_51 SB_MA_13 DDR_B_MA14
AT10 AT4 BL37
DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
AW11 AV4
AU11 AU3
AW9 AR3
AR11 AN1
AT6 AP4
AP6 AL3
AL7 AJ1
AR7 AK4
B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
AT12 AM4
AM6 AH2
AU7 AK2
SA_DQ_63 SB_DQ_63
CANTIGA GMCH SFF_FCBGA1363 CANTIGA GMCH SFF_FCBGA1363
A A

Cantiga(2/6)-DDR2 A/B CH
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
U3C Strap Pin Table

PEGCOMP trace width +VCC_PEG 000 = FSB 1066MHz
and spacing is 20/25 mils. CFG[2:0] FSB Freq select
<21> L_BKLT_CTRL D38 010 = FSB 800MHz
L_BKLT_CTRL PEGCOMP
<21> ENABLT C37 U45 1 2
R65 1 2 10K_0402_5% K38
L_BKLT_EN PEG_COMPI
T44 R64 49.9_0402_1% 011 = FSB 667MHz
+3VS L_CTRL_CLK PEG_COMPO
Others = Reserved
R66 1 2 10K_0402_5% L37 L_CTRL_DATA layout note:
<21> DDC2_CLK J37 L_DDC_CLK PEG_RX#_0 D52
<21> DDC2_DATA L35 L_DDC_DATA PEG_RX#_1 G49 Place R64 <500mils to U4 pin U45&T44. CFG[4:3] Reserved
PEG_RX#_2 K54
PEG_RX#_3
H50 0 = DMI x 2
<21> ENAVDD B36
L_VDD_EN PEG_RX#_4
M52 CFG5 (DMI select) 1 = DMI x 4
D R67
1
T42
2
2.4K_0402_1%~D
F50
H46
LVDS_IBG
LVDS_VBG
PEG_RX#_5
PEG_RX#_6
N49
P54
*
0 = The iTPM Host Interface is enable D
P44
LVDS_VREFH PEG_RX#_7
V46 CFG6
K46 Y50 1 = The iTPM Host Interface is disable
<21> TXCLK_L-
<21> TXCLK_L+
D46
B46
LVDS_VREFL
LVDSA_CLK#
PEG_RX#_8
PEG_RX#_9
V52
W49 0 =(TLS)chiper suite with no confidentiality
*
LVDSA_CLK PEG_RX#_10
LVDS
D44
LVDSB_CLK# PEG_RX#_11
AB54 CFG7 (Intel Management
B44 AD46 1 =(TLS)chiper suite with confidentiality
<21> TXOUT_L0- G45
LVDSB_CLK PEG_RX#_12
PEG_RX#_13
AC55
AE49
Engine Crypto strap) *
LVDSA_DATA#_0 PEG_RX#_14
<21> TXOUT_L1- F46 AF54
LVDSA_DATA#_1 PEG_RX#_15
GRAPHICS
<21> TXOUT_L2- G41
LVDSA_DATA#_2 CFG8 Reserved
C45 LVDSA_DATA#_3 PEG_RX_0 E51
PEG_RX_1 F48
<21> TXOUT_L0+ F44 LVDSA_DATA_0 PEG_RX_2 J55 CFG9 0 = Reverse Lane,15->0, 14->1
G47 J49 HDMI_HPD#
<21> TXOUT_L1+ LVDSA_DATA_1 PEG_RX_3 HDMI_HPD# <21>
F40 M54 (PCIE Graphics Lane Reversal) 1 = Normal Operation,Lane Number in order
<21> TXOUT_L2+
A45
LVDSA_DATA_2
LVDSA_DATA_3
PEG_RX_4
PEG_RX_5 M50
P52
*
PEG_RX_6
B40 LVDSB_DATA#_0 PEG_RX_7 U47 0 = Enable
A41 LVDSB_DATA#_1 PEG_RX_8 AA49 CFG10 (PCIE Lookback enable)
F42 V54 1 = Disable
D48
LVDSB_DATA#_2
LVDSB_DATA#_3
PEG_RX_9
PEG_RX_10 V50
AB52 CFG11 Reserved
*
PEG_RX_11
D40 LVDSB_DATA_0 PEG_RX_12 AC47
C41 AC53 CFG[13:12] (XOR/ALLZ) 00 = Reserved
PCI-EXPRESS
LVDSB_DATA_1 PEG_RX_13
G43 LVDSB_DATA_2 PEG_RX_14 AD50 01 = XOR Mode Enabled
B48 LVDSB_DATA_3 PEG_RX_15 AF52 10 = All Z Mode Enabled
11 = Normal Operation(Default)
PEG_TX#_0 L47 HDMI_C_TX2-
HDMI_C_TX1-
C1036 1
C1037 1
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
TX2D- <21> *
PEG_TX#_1 F52 2 TX1D- <21>CFG[15:14] Reserved
R68 1 2 75_0402_5% J27 P46 HDMI_C_TX0- C1038 1 2 0.1U_0402_16V4Z
TVA_DAC PEG_TX#_2 TX0D- <21>
TV
R69 1 2 75_0402_5% E27 H54 HDMI_C_CLK- C1039 1 2 0.1U_0402_16V4Z
C TVB_DAC PEG_TX#_3 TXCD- <21> C
R70 1 2 75_0402_5% G27 L55 CFG16 (FSB Dynamic ODT) 0 = Disabled
TVC_DAC PEG_TX#_4
PEG_TX#_5 T46
F26 R53 1 = Enabled
TVA_RTN PEG_TX#_6
PEG_TX#_7 U49
T54
*
PEG_TX#_8
PEG_TX#_9 Y46 CFG[18:17] Reserved
B34 TV_DCONSEL_0 PEG_TX#_10 AB46
D34 W53
TV_DCONSEL_1 PEG_TX#_11
Y54 CFG19 (DMI Lane Reversal) 0 = Normal Operation
Tie to GND. 9/28
PEG_TX#_12
PEG_TX#_13
AC49
AF46 (Lane number in Order)
*
PEG_TX#_14
AD54
PEG_TX#_15
1 = Reverse Lane
<21> D_BLUE D_BLUE J29 J47 HDMI_C_TX2+ C1040 1 2 0.1U_0402_16V4Z TX2D+ <21>
CRT_BLUE PEG_TX_0 HDMI_C_TX1+ C1041 1 0.1U_0402_16V4Z
F54 2 TX1D+ <21>
D_GREEN PEG_TX_1 HDMI_C_TX0+ C1042 1 0.1U_0402_16V4Z
G29 N47 2 <21>CFG20 (PCIE/SDVO concurrent) 0 = Only PCIE or SDVO is operational.
<21> D_GREEN
D_RED F30
CRT_GREEN PEG_TX_2
PEG_TX_3
H52
L53
HDMI_C_CLK+ C1043 1 2 0.1U_0402_16V4Z
TX0D+
TXCD+ <21>
1 = PCIE/SDVO are operating simu.
*
<21> D_RED CRT_RED PEG_TX_4
VGA
R47
PEG_TX_5
E29 R55
CRT_IRTN PEG_TX_6
T50
PEG_TX_7
<21> CRT_DDC_CLK D36 T52
CRT_DDC_CLK PEG_TX_8
<21> CRT_DDC_DATA C35 W47
R71 CRT_HSYNC_R CRT_DDC_DATA PEG_TX_9
<21> CRT_HSYNC 1 2 30.1_0402_1% J33 AA47
CRT_HSYNC PEG_TX_10 R72 @ 2.21K_0402_1%
D32 W55 <8> CFG5 1 2
R73 CRT_VSYNC_R CRT_TVO_IREF PEG_TX_11
<21> CRT_VSYNC 1 2 30.1_0402_1% G31 Y52
CRT_VSYNC PEG_TX_12 R74 @ 2.21K_0402_1%
AB50 <8> CFG6 1 2
PEG_TX_13
AE47
PEG_TX_14
2
Close to pin D32 and keep PEG_TX_15

AD52 <8> CFG7
R75 1 2 @ 2.21K_0402_1%
R76
30mil space to other 1.02K_0402_1% R77 1 2 @ 2.21K_0402_1%
part/trace. <8> CFG9
CANTIGA GMCH SFF_FCBGA1363
B R78 @ 2.21K_0402_1% B
<8> CFG10 1 2
1
R79 1 2 @ 2.21K_0402_1%
<8> CFG12
R80 1 2 @ 2.21K_0402_1%
<8> CFG13
R81 1 2 @ 2.21K_0402_1%
<8> CFG16
D_BLUE Remove R84 ~ R86 since

D_GREEN already have 75ohm of +3VS
Del R82, R83. 10/18 page17. 10/27
D_RED
R82 1 2 @ 4.02K_0402_1%
<8> CFG19
R83 1 2 @ 4.02K_0402_1%
<8> CFG20
1
1
150_0402_1%
150_0402_1%
150_0402_1%
R13
R15
R16
2
A A

Cantiga(3/6)-VGA/LVDS/TV
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
+1.05VM_DPLLA +VCCP +V1.05VM_AXF +VCCP

R84
Change to 330u_R9, 1 2 R85 1 2 0_0603_5%
BLM18PG181SN1D_0603
casue high +VCCP
10U_0805_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
1
limitation. 12/14
220U_D2_4VM_R15
@
1 1 1
U3H +
+3VS +3VS_DAC_CRT
C81
C80
C82
C83
BLM18PG181SN1D_0603 R13
VTT_1 2 2 2 2
330U_D2E_2.5VM_R9
R86 T12
VTT_2
0.47U_0603_10V7K
2.2U_0805_16V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2 1 J31 R11 1
VCCA_CRT_DAC VTT_3
+3VS_DAC_BG T10 1 1 1 1
+3VS VTT_4
0.1U_0402_16V4Z
10U_0603_6.3V
0.1U_0402_16V4Z
0.01U_0402_16V7K
R9 +
R87 VTT_5
1 1 1 1 T8
VTT_6
C87
C85
C86
C88
C84
2 1 L31 R7
CRT
BLM18PG181SN1D_0603 VCCA_DAC_BG VTT_7 2 2 2 2 2 +1.05VM_DPLLB +VCCP +1.5V_SM_CK +1.5V
0.01U_0402_16V7K
D M33 T6 D
VSSA_DAC_BG VTT_8
C89
C90
C91
C92
R5 R88
22U_0805_6.3V
2 2 2 2 VTT_9 R89
1 1 9/27 T4 1 2 1 2 0_0805_5%
VTT_10 BLM18PG181SN1D_0603
R3
VTT_11
0.1U_0402_16V4Z
+1.05VM_DPLLA J45 T2 1
VCCA_DPLLA VTT_12
2
0_0603_5%
C93
C94
220U_D2_4VM_R15
@
R1 1
VTT
2 2 VTT_13
0.1U_0402_16V4Z
10U_0805_6.3V6M
L49 +
+1.05VM_DPLLB VCCA_DPLLB +3VS_TVDAC +3VS
1 1
PLL
C96
C95
R90
install 0.1U & 10U for wavy issue. 7/29 +1.05VM_HPLL AF10
VCCA_HPLL 2 2
R91
C97
C98
+1.05VM_MPLL AE1 K30 1 2
+1.8V_TXLVDS VCCA_MPLL VCCA_TV_DAC 2 2
10U_0805_6.3V6M
BLM18PG181SN1D_0603
TV
+VCC_HDA
0.01U_0402_16V7K
0.1U_0402_16V4Z
1
change 0.1U to 22U for wavy issue. 5/20 R92 1 1
A PEG A LVDS
U43 @ 0_0402_5%
+1.5VS_PEG_BG VCCA_LVDS1 +1.05VM_HPLL +VCCP
C99
1 U41 A31 1 2
D TV/CRT HDA
VCCA_LVDS2 VCC_HDA 2
C100
C101
C102 R93
1000P_0402_50V7K 2 2
V44 VSSA_LVDS
1 2
BLM18PG181SN1D_0603
2
0.1U_0402_16V4Z
4.7U_0805_10V4Z
VCCD_QDAC N34 +1.5VS_QDAC
+1.5VS R94 1 2 0_0603_5% AJ43 1 1
VCCA_PEG_BG
VCCD_TVDAC N32 +1.5VS_TVDAC
1
C103
C104
C105
2 2
9/27 +1.05VM_PEGPLL AG43 VCCA_PEG_PLL Tie to GND. 9/27
0.1U_0402_16V4Z
2
9/27 +VCC_HDA +1.5VS
AW24 VCCA_SM_1
AU24
+VCCP +1.05VM_A_SM
AW22
AU22
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
POWER R321 1 2 0_0603_5%
+1.05VM_MPLL
R95
+VCCP +1.5VS_TVDAC +1.5VS
AU21 1 1 2 R96
VCCA_SM_5
0.1U_0402_16V4Z
AW20 BLM18PG181SN1D_0603 1 2
VCCA_SM_6
10U_0805_6.3V6M
C1045
0.1U_0402_16V4Z
AU19 BLM18PG181SN1D_0603
VCCA_SM_7
0.01U_0402_16V7K
0.1U_0402_16V4Z
C106
C107
R97 1 2 0_0805_5% AW18 Enable HDMI audio 1 1
A SM
C VCCA_SM_8 2 C
AU18 VCCA_SM_9 1 1
10U_0805_6.3V6M
4.7U_0805_10V4Z
1U_0603_10V4Z
100U_D2_6.3VM
1 1 1 1 AW16 VCCA_SM_10
AU16 VCCA_SM_11 2 2
C108
C109
+ AT16 VCCA_SM_12 2 2
C111
C112
C113
AR16 VCCA_SM_13
2 2 2
C110
AU15 VCCA_SM_14
2
AT15 VCCA_SM_15 9/27
AR15
VCCA_SM_16
AW14 M25 +V1.05VM_AXF
VCCA_SM_17 VCC_AXF_1 +1.8V_TXLVDS +1.8V
N24
AXF
VCC_AXF_2
AT24 M23 +VCCP
VCCA_SM_NCTF_1 VCC_AXF_3 R98 +VCC_PEG
AR24
VCCA_SM_NCTF_2 1 2 0_0603_5%
1000P_0402_50V7K
AT22
VCCA_SM_NCTF_3
AR22
VCCA_SM_NCTF_4
AT21 1 1 1 2
VCCA_SM_NCTF_5 C115 R99 0_1206_5%
AR21 BK24 +1.5V_SM_CK
VCCA_SM_NCTF_6 VCC_SM_CK_1
4.7U_0805_10V4Z
10U_0805_6.3V6M
220U_D2_4VM_R15
AT19 BL23 @10U_0805_6.3V6M 1
SM CK
C114
AR19 BJ23 1 1
+1.05VM_A_SM_CK VCCA_SM_NCTF_8 VCC_SM_CK_3 2 2 +
AT18 BK22
AR18 +3VS_HV
VCCA_SM_NCTF_10
C117
C118
C116
2 2 2
T41 +1.8V_TXLVDS
R100 VCC_TX_LVDS
1 2 0_0603_5% AU27
VCCA_SM_CK_4 +1.05VM_PEGPLL +VCCP
AU28 C33
VCCA_SM_CK_3 VCC_HV_1
10U_0805_6.3V6M
0.1U_0402_16V4Z
AU29 A33 L1
VCCA_SM_CK_2 VCC_HV_2
1 1 AU31 1 2
HV
VCCA_SM_CK_1
0.1U_0402_16V4Z
AT31 BLM18PG121SN1D_0603
VCCA_SM_CK_NCTF_1 +1.05VM_DMI
0.1U_0402_16V4Z
10U_0805_10V4Z
AR31 1 9/29 +VCCP
VCCA_SM_CK_NCTF_2
C119
C120
AT29 AB44 +VCC_PEG 1 1

2 2 VCCA_SM_CK_NCTF_3 VCC_PEG_1
AR29 Y44
VCCA_SM_CK_NCTF_4 VCC_PEG_2
C121
AT28 PEG AC43 R101 1 2 0_0603_5%
VCCA_SM_CK_NCTF_5 VCC_PEG_3 2
C122
C123
0.1U_0402_16V4Z
AR28 AA43
VCCA_SM_CK_NCTF_6 VCC_PEG_4 2 2
AT27 1
VCCA_SM_CK_NCTF_7
B AR27 B
VCCA_SM_CK_NCTF_8
C124
AM44 +1.05VM_DMI
VCC_DMI_1 2
AN43
VCC_DMI_2
AL43 9/29
DMI
VCC_DMI_3
+1.05VM_HPLL AH12
VCCD_HPLL
0.1U_0402_16V4Z
+1.05VM_PEGPLL AE43
VCCD_PEG_PLL +VCCP_D
C125
1
0.1U_0402_16V4Z
9/27 K14
VTTLF
VTTLF1
C126
1 M46 Y12
VCCD_LVDS_1 VTTLF2
LVDS
+1.8V R102 2 1 0_0603_5% L45 P2

2 VCCD_LVDS_2 VTTLF3 R103 1
+VCCP 2 1 2 10_0402_5% R104 1 2 0_0402_5% +3VS_HV
1U_0603_10V4Z
0.47U_0603_10V7K
0.47U_0603_10V7K
0.47U_0603_10V7K
1 D1 CH751H-40_SC76
2
1 1 1 +3VS
+1.8V_LVDS CANTIGA GMCH SFF_FCBGA1363
C127
2
C128
C129
C130
2 2 2
+1.5VS_QDAC +1.5VS
R105
1 2
BLM18PG181SN1D_0603
0.01U_0402_16V7K
0.1U_0402_16V4Z
4.7U_0603_6.3V
1 1 1
C131
C132
C133
2 2 2
install 4.7U for wavy issue. 7/29

A A

Cantiga(4/6)-PWR
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
U3G
+VCCP
3000mA
Extnal Graphic: 1210.34mA VCC_AXG_NCTF_1 T32
integrated Graphic: 1930.4mA BB36 VCC_SM_1 VCC_AXG_NCTF_2 U31
BE35 VCC_SM_2 VCC_AXG_NCTF_3 T31
+1.5V AW34 VCC_SM_3 VCC_AXG_NCTF_4 R31
U3F AW32 U29
VCC_SM_4 VCC_AXG_NCTF_5
330U_D2E_2.5VM_R9
10U_0805_6.3V6M
10U_0805_6.3V6M
0.01U_0402_16V7K
0.1U_0402_16V4Z
0.22U_0402_10V4Z
4.7U_0805_10V4Z
BK30 VCC_SM_5 VCC_AXG_NCTF_6 T29 1 1 1
1 BH30 R29
1 1 2 BF30 U28
+VCCP VCC_SM_7 VCC_AXG_NCTF_8
C137
C138
C139
C140
C134
C135
C136
+ BD30 U27
D VCC_SM_8 VCC_AXG_NCTF_9 2 2 2 D
BB30 T27
AW30 R27
2 2 2 1 VCC_SM_10 VCC_AXG_NCTF_11
AT41 BL29 U25
VCC_1 VCC_SM_11 VCC_AXG_NCTF_12
AR41 BJ29 T25
AN41 BG29 R25
AJ41 BE29 U24
AH41 BC29 U22
POWER
AD41 BA29 T22
AC41 AY29 R22
Y41 BK28 U21
W41 BH28 T21
AT40 VCC_10 BF28 VCC_SM_20 VCC_AXG_NCTF_21 R21
220U_D2_4VM_R15
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.1U_0402_16V4Z
AM40 VCC_11 BD28 VCC_SM_21 VCC_AXG_NCTF_22 AM19
10U_0805_6.3V6M
1 AL40 VCC_12 BB28 VCC_SM_22 VCC_AXG_NCTF_23 AL19

1 1 1 1 BL27 VCC_SM_23 VCC_AXG_NCTF_24 AH19
C141
C142
C143
C144
C145
+ AJ40 BJ27 AG19
VCC CORE
AH40 VCC_14 BG27 VCC_SM_25 VCC_AXG_NCTF_26 AE19
VCC SM
AG40 VCC_15 BE27 VCC_SM_26 VCC_AXG_NCTF_27 AD19
2 2 2 2 2 AE40 BC27 AC19
VCC GFX NCTF

AD40 VCC_17 BA27 VCC_SM_28 VCC_AXG_NCTF_29 W19
AC40 VCC_18 AY27 VCC_SM_29 VCC_AXG_NCTF_30 U19
AA40 VCC_19 AW26 VCC_SM_30 VCC_AXG_NCTF_31 AM18
Y40 VCC_20 BF24 VCC_SM_31 VCC_AXG_NCTF_32 AL18
AN35 VCC_21 BL19 VCC_SM_32 VCC_AXG_NCTF_33 AJ18
AM35 VCC_22 BB16 VCC_SM_33 VCC_AXG_NCTF_34 AH18
AJ35 +VCCP AG18
VCC_23 VCC_AXG_NCTF_35
AH35 VCC_24 VCC_AXG_NCTF_36 AE18
AD35 VCC_25 VCC_AXG_NCTF_37 AD18
AC35 VCC_26 VCC_AXG_NCTF_38 AC18
W35 VCC_27 W32 VCC_AXG_1 VCC_AXG_NCTF_39 AA18
AM34 VCC_28 AG31 VCC_AXG_2 VCC_AXG_NCTF_40 Y18
1U_0603_10V4Z
10U_0805_6.3V
10U_0805_6.3V
0.1U_0402_16V4Z
AL34 VCC_29 1 AE31 VCC_AXG_3 VCC_AXG_NCTF_41 W18
C
C147
C148
C149
C150
C
AJ34 VCC_30 1 1 1 1 AD31 VCC_AXG_4 VCC_AXG_NCTF_42 U18
AH34 C146 + AC31 T18
VCC_31 +VCCP 330U_D2E_2.5VM_R9 VCC_AXG_5 VCC_AXG_NCTF_43
AG34 VCC_32 AA31 VCC_AXG_6 VCC_AXG_NCTF_44 R18
AE34 VCC_33 Y31 VCC_AXG_7
2 2 2 2 2
POWER
AD34 VCC_34 W31 VCC_AXG_8
VCC_NCTF_1 AT38 AH29 VCC_AXG_9
AC34 VCC_35 VCC_NCTF_2 AR38 AG29 VCC_AXG_10
AA34 AN38 AE29
VCC_36 VCC_NCTF_3 VCC_AXG_11
AM38 AD29 AJ16
VCC_NCTF_4 VCC_AXG_12 VCC_AXG_62
Y34 AL38 AC29 AH16
VCC_37 VCC_NCTF_5 VCC_AXG_13 VCC_AXG_63
W34 AG38 AA29 AD16
AM32 AE38 Y29 AC16
AL32 AA38 W29 AA16
AJ32 Y38 AH28 U16
AH32 W38 AG28 T16
VCC GFX
AE32 U38 AE28 R16
AD32 T38 AA28 AM15
AA32 R38 AH27 AL15
AM31
VCC_46 VCC_NCTF_14
AT37 6326.84mA AG27
VCC_AXG_22 VCC_AXG_72
AJ15
AL31 AR37 AE27 AH15
AJ31 AN37 AD27 AG15
AH31 AM37 AC27 AE15
AM29 AL37 AA27 AA15
AL29 AJ37 Y27 Y15
AM28 AH37 W27 W15
AL28 AG37 AH25 U15
AJ28 AE37 AD25 T15
AM27 AD37 AC25
AL27 AC37 W25
VCC NCTF
AM25 AA37 AJ24

AL25 Y37 AH24
AJ25 W37 AG24
B VCC_59 VCC_NCTF_27 VCC_AXG_35 B
AM24 U37 AE24
N36 T37 AD24
R37 AC24
VCC_NCTF_30 VCC_AXG_38
AT35 AA24
AR35 Y24
U35 W24
AT34 AM22
AR34 AL22
U34 AJ22
VCC GFX
T34 AH22
R34 AG22
AE22
VCC_AXG_47
AD22
VCC_AXG_48
AC22
VCC_AXG_49 VCCSM_LF1
AA22 AU45
VCC_AXG_50 VCC_SM_LF1 VCCSM_LF2
VCC SM LF
AM21 BF52
AL21 BB38
AJ21 BA19
AH21 BE9
VCC_AXG_54 VCC_SM_LF5
C151 0.22U_0603_10V7K
C152 0.22U_0603_10V7K
C153 0.47U_0402_6.3V6K
C154 1U_0603_10V4Z
C155 1U_0603_10V4Z
AD21 AU9 VCCSM_LF6 1 1 1 1 1
AC21 AL9
VCC_AXG_56 VCC_SM_LF7
C156 0.1U_0402_16V4Z
C157 0.1U_0402_16V4Z
AA21 1 1
VCC_AXG_57
Y21
VCC_AXG_58 2 2 2 2 2
W21
VCC_AXG_59
AM16
CANTIGA GMCH SFF_FCBGA1363 VCC_AXG_60 2 2
AL16
VCC_AXG_61
PAD T43 AG13

VCC_AXG_SENSE
PAD T44 AE13
VSS_AXG_SENSE
A A

Cantiga(5/6)-PWR/GND
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
U3I
BA55 C43 U3J

VSS_1 VSS_100
AU55 VSS_2 VSS_101 A43
AN55 VSS_3 VSS_102 BD42 AN25 VSS_199 VSS_300 AM8
AJ55 VSS_4 VSS_103 H42 AG25 VSS_200 VSS_301 AK8
AE55 VSS_5 VSS_104 BG41 AE25 VSS_201 VSS_302 AH8
AA55 VSS_6 VSS_105 AY41 AA25 VSS_202 VSS_303 AF8
U55 VSS_7 VSS_106 AU41 Y25 VSS_203 VSS_304 AD8
N55 VSS_8 VSS_107 AM41 E25 VSS_204 VSS_305 AB8
BD54 VSS_9 VSS_108 AL41 A25 VSS_205 VSS_306 Y8
BG53 AG41 BD24 V8
VSS_10 VSS_109 VSS_206 VSS_307
AJ53 AE41 AN24 P8
AE53 AA41 AL24 M8
D VSS_12 VSS_111 VSS_208 VSS_309 D
AA53 R41 H24 K8
U53 M41 BG23 H8
N53 E41 AY23 BJ7
J53 BD40 E23 E7
G53 AU40 BD22 BF6
E53 AR40 BB22 BC5
K52 AN40 AN22 BA5
BG51 W40 Y22 AW5
BA51 U40 W22 AU5
AW51 T40 H22 AR5
AU51 R40 BL21 AN5
AR51 VSS_24 VSS_123 K40 BG21 VSS_220 VSS_321 AL5
AN51 VSS_25 VSS_124 H40 AY21 VSS_221 VSS_322 AJ5
AL51 VSS_26 VSS_125 BL39 AN21 VSS_222 VSS_323 AG5
AJ51 VSS_27 VSS_126 BG39 AG21 VSS_223 VSS_324 AE5
AG51 VSS_28 VSS_127 BA39 AE21 VSS_224 VSS_325 AC5
AE51 VSS_29 VSS_128 E39 M21 VSS_225 VSS_326 AA5
AC51 VSS_30 VSS_129 C39 E21 VSS_226 VSS_327 W5
AA51 VSS_31 VSS_130 A39 A21 VSS_227 VSS_328 U5
W51 VSS_32 VSS_131 BD38 BD20 VSS_228 VSS_329 N5
U51 AU38 H20 L5
R51
N51
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
H38
BG37
BG19
AY19
VSS_229
VSS_230
VSS_231
VSS VSS_330
VSS_331
VSS_332
J5
G5
L51 VSS_36 VSS_135 AU37 M19 VSS_232 VSS_333 C5
J51 VSS_37 VSS_136 M37 E19 VSS_233 VSS_334 BH4
G51 VSS_38 VSS_137 E37 BD18 VSS_234 VSS_335 BE3
C51 VSS_39 VSS_138 BD36 N18 VSS_235 VSS_336 U3
BK50 VSS_40 VSS_139 AW36 H18 VSS_236 VSS_337 E3
AM50 VSS_41 VSS_140 H36 BL17 VSS_237 VSS_338 BC1
K50 VSS_42 VSS_141 BL35 BG17 VSS_238 VSS_339 AW1
BG49 VSS_43 VSS_142 BG35 AY17 VSS_239 VSS_340 AR1
E49 VSS_44 VSS_143 AY35 M17 VSS_240 VSS_341 AL1
C C
C49 VSS_45 VSS_144 AU35 E17 VSS_241 VSS_342 AG1
BD48 VSS_46 VSS_145 AL35 A17 VSS_242 VSS_343 AC1
BB48 VSS_47 VSS_146 AG35 BD16 VSS_243 VSS_344 W1
AY48 VSS_48 VSS_147 AE35 AN16 VSS_244 VSS_345 N1
AV48 VSS_49 VSS_148 AA35 AG16 VSS_245 VSS_346 J1
AT48 VSS_50 VSS_149 Y35 AE16 VSS_246 VSS_347 AU43
AP48 VSS_51 VSS_150 M35 Y16 VSS_247 VSS_348 BB42
AM48 E35 W16 AW38
AK48 A35 N16 BA35
AH48 BD34 H16 L29
AF48 AU34 BG15 N28
AD48 AN34 AY15 N22
AB48 H34 AN15 N20
Y48 BL33 AD15 N14
V48 BG33 AC15 AL13
T48 AY33 R15 B10
P48 E33 M15 AN13
M48 BD32 E15
VSS_62 VSS_161 VSS_258
K48 AU32 BD14 N42
H48 AN32 H14 N40
BL47 AG32 BL13 N38
BG47 AC32 BG13 M39
E47 Y32 AY13
C47 H32 AU13
A47 B32 AR13 AJ38
VSS_69 VSS_168 VSS_265 VSS_NCTF_1
BD46 BJ31 AJ13 AH38
AY46 BG31 AC13 AD38
AM46 AY31 AA13 AC38
AK46 AN31 W13 T35
AH46 M31 U13 R35
VSS NCTF
BG45 E31 M13 AT32
AE45 N30 E13 AR32
B VSS_76 VSS_175 VSS_272 VSS_NCTF_8 B
AC45 H30 A13 U32
AA45 AN29 BD12 R32
W45 AJ29 AV12 T28
R45 M29 AP12 R28
N45 A29 AM12 AT25
E45 AW28 AK12 AR25
BD44 AN28 AB12 T24
BB44 AD28 V12 R24
AV44 AC28 P12 AN19
AK44 Y28 H12 AJ19
AH44 W28 BG11 AA19
AF44 H28 AG11 Y19
AD44 F28 E11 T19
K44 AN27 BD10 R19
H44 AJ27 AY10 AN18
BL43 M27 AP10
BG43 BF26 H10
AY43 BD26 BL9
AR43 N26 BG9
W43 H26 E9
R43 BJ25 A9 BL55
VSS_97 VSS_196 VSS_293 VSS_SCB_1
M43 AY25 BD8 BL1
VSS SCB
E43 AU25 BB8 A55
AY8 D1
VSS_296 VSS_SCB_4
AV8 B55
CANTIGA GMCH SFF_FCBGA1363 VSS_297 VSS_SCB_5
AT8 B2
VSS_298 VSS_SCB_6
AP8 A4
VSS_299 VSS_SCB_7

A A

Cantiga(6/6)-PWR/GND
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
+V_DDR3_DIMM_REF
+1.5V +1.5V
<9> DDR_A_DQS#[0..7]
<9> DDR_A_D[0..63] JP4

1 VREF_DQ VSS1 2
3 4 DDR_A_D4
<9> DDR_A_DM[0..7] DDR_A_D0 VSS2 DQ4 DDR_A_D5
5 DQ0 DQ5 6
+1.5V DDR_A_D1 7 8
<9> DDR_A_DQS[0..7] DQ1 VSS3
9 10 DDR_A_DQS#0
DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
<9> DDR_A_MA[0..14] 11 DM0 DQS0 12
1
13 VSS5 VSS6 14
R431 DDR_A_D2 15 16 DDR_A_D6
<9> DDR_A_BS[0..2] DQ2 DQ6
100_0402_1% DDR_A_D3 17 18 DDR_A_D7
+V_DDR3_DIMM_REF DQ3 DQ7
19 20
D DDR_A_D8 VSS7 VSS8 DDR_A_D12 D
21 22
2
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 24
DQ9 DQ13
25 26
VSS9 VSS10
1
1 DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 SM_DRAMRST#
29 30 SM_DRAMRST# <8,15>
C1237 R432 DQS1 RESET#
31 32
0.1U_0402_16V4Z 100_0402_1% DDR_A_D10 VSS11 VSS12 DDR_A_D14
33 34
2 DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
2
DQ11 DQ15
37 38
DDR_A_D16 VSS13 VSS14 DDR_A_D20
39 40
41 42
DQ17 DQ21
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
Layout Note: DDR_A_D24
55 VSS20 DQ28 56
DDR_A_D29
57 58
Place near JP3 DDR_A_D25 59
DQ24 DQ29
60
DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
Layout Note: Place these 4 Caps near Command 65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
and Control signals of DIMMA DDR_A_D27 69
DQ26 DQ30
70 DDR_A_D31
DQ27 DQ31
71 VSS25 VSS26 72
+1.5V
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<8> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <8>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 75 VDD1 VDD2 76
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 77 NC1 A15 78
C1245
C1246
C1247
C1248
C1239
C1240
C1241
C1242
C1243
C1244
C + C1238 DDR_A_BS2 DDR_A_MA14 C

79 BA2 A14 80
470U_D2_2.5VM_R15 81 82
DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
@ 83 84
2 2 2 2 2 2 2 2 2 2 2 DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 94
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2
95 96
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
A1 A0
99 100
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
101 102 M_CLK_DDR1 <8>
<8> M_CLK_DDR0 M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1
103 104 M_CLK_DDR#1 <8>
<8> M_CLK_DDR#0 CK0# CK1#
105 106
DDR_A_MA10 VDD11 VDD12 DDR_A_BS1
Layout Note: DDR_A_BS0
107
A10/AP BA1
108
DDR_A_RAS#
109 110 DDR_A_RAS# <9>
Place near JP3.203 & JP3.204 BA0 RAS#
111 112
DDR_A_WE# VDD13 VDD14 DDR_CS0_DIMMA#
113 114 DDR_CS0_DIMMA# <8>
<9> DDR_A_WE# DDR_A_CAS# WE# S0# M_ODT0
<9> DDR_A_CAS# 115 116 M_ODT0 <8>
CAS# ODT0
117 118
DDR_A_MA13 VDD15 VDD16 M_ODT1
119 120 M_ODT1 <8>
+0.75VS DDR_CS1_DIMMA# A13 ODT1 +V_DDR3_DIMM_REF
121 122
<8> DDR_CS1_DIMMA# S1# NC2
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMA R433 1
125 126 2 0_0402_5%
NCTEST VREF_CA
127 128 1 1
VSS27 VSS28
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
10U_0805_6.3V6M
DDR_A_D32 129 130 DDR_A_D36

DDR_A_D33 DQ32 DQ36 DDR_A_D37 C1249 C1250
131 132
DQ33 DQ37 0.1U_0402_16V4Z 2.2U_0805_16V4Z
2 2 2 2 1 133 134
DDR_A_DQS#4 VSS29 VSS30 DDR_A_DM4 2 2
135 136
137 138
DQS4 VSS31 DDR_A_D38
139 140
1 1 1 1 2 VSS32 DQ38
C1251
C1252
C1253
C1254
C1255
DDR_A_D34 141 142 DDR_A_D39

B DDR_A_D35 DQ34 DQ39 B
143 144
DQ35 VSS33 DDR_A_D44
145 146
147 148
DDR_A_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_A_DQS#5
151 152
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
155 156
157 158
159 160
DQ43 DQ47
161 162
163 164
165 166
DQ49 DQ53
167 168
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 170
171 172
DQS6 VSS43 DDR_A_D54
173 174
175 176
DDR_A_D51 177
179
DQ50
DQ51
DQ55
VSS45
178
180 DDR_A_D60
TOP Side
VSS46 DQ60
DDR_A_D56
DDR_A_D57
181
183
DQ56
DQ57
DQ61
VSS47
182
184
DDR_A_D61
DDR3
185 186 DDR_A_DQS#7
DDR_A_DM7 187
189
VSS48
DM7
DQS#7
DQS7
188
190
DDR_A_DQS7 SO-DIMM A
VSS49 VSS50
DDR_A_D58
DDR_A_D59
191
193
DQ58
DQ59
DQ62
DQ63
192
194
DDR_A_D62
DDR_A_D63 Standard
+3VS 195 196
R434 1 2 10K_0402_5% 197
199
VSS51
SA0
VSS52
EVENT#
198
200
PM_EXTTS#0
CLK_SMBDATA PM_EXTTS#0 <8> TYPE
VDDSPD SDA ICH_SMBDATA <15,16,19,21>
1 1 R435 1 2 10K_0402_5% 201
203
SA1
VTT1
SCL
VTT2
202
204
CLK_SMBCLK
+0.75VS
(4.0mm)
ICH_SMBCLK <15,16,19,21>
C1256 C1257
A 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z A
205 G1 G2 206
2 2
FOX_AS0A626-U4SN-7F +0.75VS
ME@

DDR3-SODIMM SLOT1
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
+V_DDR3_DIMM_REF
+1.5V +1.5V
JP3
1 VREF_DQ VSS1 2
1 3 4 DDR_B_D4
DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 DQ0 DQ5 6
C1303 DDR_B_D1 7 8
0.1U_0402_16V4Z DQ1 VSS3 DDR_B_DQS#0
<9> DDR_B_DQS#[0..7] 9 VSS4 DQS#0 10
2 DDR_B_DM0 11 12 DDR_B_DQS0
DM0 DQS0
<9> DDR_B_D[0..63] 13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 18
<9> DDR_B_DM[0..7] DQ3 DQ7
19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
<9> DDR_B_DQS[0..7] 21 22
D DDR_B_D9 DQ8 DQ12 DDR_B_D13 D
23 24
DQ9 DQ13
<9> DDR_B_MA[0..14] 25 26
DDR_B_DQS#1 VSS9 VSS10 DDR_B_DM1
27 28
DDR_B_DQS1 DQS#1 DM1 SM_DRAMRST#
<9> DDR_B_BS[0..2] 29 30 SM_DRAMRST# <8,14>
DQS1 RESET#
31 32
33 34
35 36
DQ11 DQ15
37 38
39 40
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS15 VSS16 DDR_B_DM2
45 DQS#2 DM2 46
DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
49 VSS18 DQ22 50
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_B_D28
57 DQ24 DQ29 58
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
Layout Note: DDR_B_D26
65 VSS23 VSS24 66
DDR_B_D30
67 DQ26 DQ30 68
Place near JP4 DDR_B_D27 69 70 DDR_B_D31
DQ27 DQ31
71 VSS25 VSS26 72
Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
+1.5V <8> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <8>
75 VDD1 VDD2 76
77 NC1 A15 78
DDR_B_BS2 79 80 DDR_B_MA14
C BA2 A14 C
81 VDD3 VDD4 82
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 DDR_B_MA12 83 84 DDR_B_MA11
A12/BC# A11
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
C1265
C1266
C1267
C1268
C1259
C1260
C1261
C1262
C1263
C1264
+ C1258 87 88
470U_D2_2.5VM_R15 DDR_B_MA8 VDD5 VDD6 DDR_B_MA6
89 A8 A6 90
@ DDR_B_MA5 91 92 DDR_B_MA4
2 2 2 2 2 2 2 2 2 2 2 A5 A4
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
101 102 M_CLK_DDR3 <8>
<8> M_CLK_DDR2 M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
103 104 M_CLK_DDR#3 <8>
<8> M_CLK_DDR#2 CK0# CK1#
105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 108
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
109 110 DDR_B_RAS# <9>
BA0 RAS#
111 112
DDR_B_WE# VDD13 VDD14 DDR_CS2_DIMMB#
Layout Note: <9> DDR_B_WE#
DDR_B_CAS#
113
WE# S0#
114
M_ODT2
DDR_CS2_DIMMB# <8>
<9> DDR_B_CAS# 115 116 M_ODT2 <8>
Place near JP4.203 & JP4.204 117
CAS# ODT0
118
DDR_B_MA13 VDD15 VDD16 M_ODT3 +V_DDR3_DIMM_REF
119 120 M_ODT3 <8>
DDR_CS3_DIMMB# A13 ODT1
121 122
<8> DDR_CS3_DIMMB# S1# NC2
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMB R436 1
125 126 2 0_0402_5%
+0.75VS NCTEST VREF_CA
127 128 1 1
129 130
DDR_B_D33 DQ32 DQ36 DDR_B_D37 C1274 C1275
131 132
DQ33 DQ37 0.1U_0402_16V4Z 2.2U_0805_16V4Z
133 134
VSS29 VSS30 2 2
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
10U_0805_6.3V6M
DDR_B_DQS#4 135 136 DDR_B_DM4

DDR_B_DQS4 DQS#4 DM4
137 138
DQS4 VSS31 DDR_B_D38
2 2 2 2 1 139 140
141 142
DDR_B_D35 DQ34 DQ39
143 144
B DQ35 VSS33 DDR_B_D44 B
145 146
1 1 1 1 2 VSS34 DQ44
C1269
C1270
C1271
C1272
C1273
DDR_B_D40 147 148 DDR_B_D45

DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
151 152
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 154
DM5 DQS5
155 156
157 158
159 160
DQ43 DQ47
161 162
163 164
165 166
DDR_B_DQS#6
167
169
DQ49
VSS41
DQ53
VSS42
168
170 DDR_B_DM6
Bottom Side
DQS#6 DM6
DDR_B_DQS6 171
173
DQS6
VSS44
VSS43
DQ54
172
174 DDR_B_D54 DDR3
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 177
179
DQ50
DQ51
DQ55
VSS45
178
180 DDR_B_D60
SO-DIMM B
VSS46 DQ60
DDR_B_D56
DDR_B_D57
181
183
DQ56
DQ57
DQ61
VSS47
182
184
DDR_B_D61
Reverse
185 186 DDR_B_DQS#7
DDR_B_DM7 187
189
VSS48
DM7
DQS#7
DQS7
188
190
DDR_B_DQS7 TYPE
VSS49 VSS50
DDR_B_D58
DDR_B_D59
191
193
DQ58
DQ59
DQ62
DQ63
192
194
DDR_B_D62
DDR_B_D63 (4.0 mm)
+3VS 195 196
R437 1 VSS51 VSS52 PM_EXTTS#1
2 10K_0402_5% 197
SA0 EVENT#
198 PM_EXTTS#1 <8>
199 200 CLK_SMBDATA
VDDSPD SDA CLK_SMBCLK ICH_SMBDATA <14,16,19,21>
1 R438 1 2 10K_0402_5% 201 202
SA1 SCL ICH_SMBCLK <14,16,19,21>
203 204 +0.75VS
C1276 VTT1 VTT2
0.1U_0402_16V4Z 205 206
A 2 G1 G2 A
FOX_AS0A626-U4RN-7F
ME@
+0.75VS

DDR3-SODIMM SLOT2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
+3VS +3VM_CK505 +VCCP +1.05VM_CK505 C212 1 CLK_48M_ICH

FSLC FSLB FSLA CPU FSB SRC PCI
Mount C157 & C166 tp solve

2
@ 5P_0402_50V8C
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz C213 1 2 CLK_14M_ICH
12P_0402_50V8J
WWAN noise issue. 1/23

1 2 1 2
R121 0_1206_5% R122 0_1206_5% C214 2 1 CLK_PCI_ICH
47P_0402_50V8J~D
47P_0402_50V8J~D
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0 0 0 266 1066 100 33.3 @ 4.7P_0402_50V8C
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 200 800 100 33.3 C229 2 1 CLK_PCI_EC
C216
C217
C218
C219
C220
C221
C222
C223
C224
C225
C226
C227
C228
@ 4.7P_0402_50V8C
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
<BOM Structure>
C1079
C1080
0 1 1 166 667 100 33.3
D D
@ @ C1048 2 1 CLK_48M_CR
@ 4.7P_0402_50V8C
+VCCP
Place close to U5
2
R123 R124 1 2 10K_0402_5% +3VS
@ 56_0402_5% R125 1 2 10K_0402_5% +3VS
CLKREQ#_B_R R126 2 1 475_0402_1% CLKREQ#_B <8>
CLKREQG_WWAN#_R R127 2 1 475_0402_1% CLKREQ_WLAN#_R R128 2 1 475_0402_1%
CLKREQG_WWAN# <21> CLKREQ_WLAN# <21>
1
CLKSATAREQ#_R R129 2 1 475_0402_1%
FSA CLKSATAREQ# <19>
2 1 1 2 R132 1 2 10K_0402_5% +3VS
MCH_CLKSEL0 <8>
R130 2.2K_0402_5% R131 1K_0402_5% R133 1 2 10K_0402_5% +3VS
1 2 +3VM_CK505 U4
<5> CPU_BSEL0
R134 0_0402_5%
6 VDDREF NC 11
1
12 VDDPCI
9/14 19 VDD48
R135 +1.05VM_CK505 23
@ 1K_0402_5% VDD96_IO
27 VDDPLL3 SCLK 10 ICH_SMBCLK <14,15,19,21>
55 9 ICH_SMBDATA <14,15,19,21>
2
VDDSRC SDATA
72 VDDCPU
PCI_STOP# 54 H_STP_PCI# <19>
CPU_STOP# 53 H_STP_CPU# <19>
CPUT0_LPR_F 71 CLK_CPU_BCLK <4>

+1.05VM_CK505 70
+VCCP CPUC0_LPR_F CLK_CPU_BCLK# <4>
31 VDDPLL3_IO CPUT1_LPR_F 68 CLK_MCH_BCLK <8>
38 VDDSRC_IO CPUC1_LPR_F 67 CLK_MCH_BCLK# <8>
C C
52 VDDSRC_IO
2
62 65 CLKREQ#_B_R
R136 VDDSRC_IO CR7#
66 VDDCPU_IO
@ 1K_0402_5% 64
CPUT2_ITP_LPR/SRCT8_LPR
CPUC2_ITP_LPR/SRCC8_LPR 63
R137
1
1K_0402_5% 61
SRCT7_LPR CLK_MCH_3GPLL <8>
FSB 1 2 60
MCH_CLKSEL1 <8> SRCC7_LPR CLK_MCH_3GPLL# <8>
1 2 CLK_PCI_EC 33_0402_1% 1 2 R142 PCI_CLK1 13 58
<5> CPU_BSEL1 <21> CLK_PCI_EC PCI CR#6
R138
0_0402_5% PCI2_TME 14 57
PCI2/TME SRCT6_LPR
1
56
R141 SRCC6_LPR
15
@ 0_0402_5% PCI3 CLKREQ_WLAN#_R
49
CR10#
50 CLK_PCIE_MCARD <21>
2
27_SEL SRCT10_LPR
16 51 CLK_PCIE_MCARD# <21>
PCI4/27_Select SRCC10_LPR
CLK_PCI_ICH 33_0402_1% 1 2 R145 ITP_EN 17 46 CLKREQG_WWAN#_R
<17> CLK_PCI_ICH PCI_F5/ITP_EN CR#11
48 CLK_PCIE_WAN <21>
SRCT11_LPR
47 CLK_PCIE_WAN# <21>
CLK_XTAL_IN SRCC11_LPR
5
X1
43
CLK_XTAL_OUT CR#9
4
X2
44
SRCT9_LPR
45
SRCC9_LPR
9/20
FSC 2 1 1 2 41
MCH_CLKSEL2 <8> CR#4 CLKREQA# <21>
R146 10K_0402_5% R147 1K_0402_5%
B B
<5> CPU_BSEL2 1 2 SRCT4_LPR
39 CLK_PCIE_LAN <21>
R148 0_0402_5% CLK_48M_ICH 33_0402_1% 1 2 R149 FSA 20 40
<19> CLK_48M_ICH USB_48MHz/FSLA SRCC4_LPR CLK_PCIE_LAN# <21>
15_0402_1% 1 2 R177
<21> CLK_48M_CR
1
37
R150 FSB CR#3
@ 2
0_0402_5% FSLB/TEST_MODE R_PCIE_ICH RP28 2
35 3 0_0404_4P2R_5% CLK_PCIE_ICH <19>
SRCT3_LPR R_PCIE_ICH#
36 1 4 CLK_PCIE_ICH# <19>
CLK_14M_ICH 33_0402_1% 1 R151 FSC SRCC3_LPR
<19> CLK_14M_ICH 2 7
2
FSLC/TEST_SEL/REF0
Install. 11/06
32 CLK_PCIE_SATA <18>
SRCT2_LPR/SATAT_LPR
33 CLK_PCIE_SATA# <18>
SRCC2_LPR/SATAC_LPR
24 CLK_MCH_DREFCLK <8>
SRCT0_LPR/DOTT_96_LPR
25 CLK_MCH_DREFCLK# <8>
SRCC0_LPR/DOTC_96_LPR
59
GNDSRC
28 MCH_SSCDREFCLK <8>
27MHz_NonSS/SRCT1_LPR/SE1
18 29 MCH_SSCDREFCLK# <8>
GNDPCI 27MHz_SS/SRCC1_LPR/SE2
14.31818MHZ_20P_1BX14318BE1A
22
GND48
CLK_XTAL_OUT 26 1
+3VS +3VS +3VS GND CK_PWRGD/PD# CK_PWRGD <19>
CLK_XTAL_IN 30
GND
2
69 21 CLKSATAREQ#_R
R153 R154 R155 GNDCPU CR#A
10K_0402_5% 10K_0402_5% 10K_0402_5% 34
GNDSRC
Y1 @
42 8
1
GNDSRC REF1
2 1
A ITP_EN 27_SEL PCI2_TME A
3 GNDREF T_PAD 73
2 2 ICS9LPRS387DKLFT MLF 72P

2
@
33P_0402_50V8J C233 C234 R156 R157 R158 397 Modify to 387
33P_0402_50V8J 10K_0402_5% 10K_0402_5% @10K_0402_5%
1 1

1
CLOCK GENERATOR
5 4 3 2 1
5 4 3 2 1
+3VS
1 2 PCI_DEVSEL#
R159 8.2K_0402_5%
1 2 PCI_STOP#
R160 8.2K_0402_5%
1 2 PCI_TRDY#
R161 8.2K_0402_5%
1 2 PCI_FRAME# U5B
R162 8.2K_0402_5% A11 G4 PCI_REQ0#
PCI_PLOCK# AD0 REQ0# PCI_GNT0#
D
1
R163
2
8.2K_0402_5%
B12
A10
AD1 PCI GNT0#
E1
A9 PCI_REQ1# D
PCI_IRDY# AD2 REQ1#/GPIO50
1 2 C12
AD3 GNT1#/GPIO51
E12
R164 8.2K_0402_5% A8 B11 PCI_REQ2#
PCI_SERR# AD4 REQ2#/GPIO52
1 2 A12 C10
R165 8.2K_0402_5% AD5 GNT2#/GPIO53 PCI_REQ3#
E10 D6
PCI_PERR# AD6 REQ3#/GPIO54 PCI_GNT3#
1 2 C11
AD7 GNT3#/GPIO55
C6
R166 8.2K_0402_5% B9
AD8
D8 D10
AD9 C/BE0#
A4 A5
AD10 C/BE1#
E8 E6
AD11 C/BE2#
A3 C9
AD12 C/BE3#
D9 AD13
C8 C3 PCI_IRDY#
+3VS AD14 IRDY#
C2 AD15 PAR B1
D7 AD16 PCIRST# T3
B3 A7 PCI_DEVSEL#
PCI_PIRQA# AD17 DEVSEL# PCI_PERR#
1 2 D11 AD18 PERR# D4
R167 8.2K_0402_5% B6 C5 PCI_PLOCK#
PCI_PIRQB# AD19 PLOCK# PCI_SERR#
1 2 D5 AD20 SERR# H5
R168 8.2K_0402_5% D3 A6 PCI_STOP#
PCI_PIRQC# AD21 STOP# PCI_TRDY#
1 2 F4 AD22 TRDY# A2
R169 8.2K_0402_5% E3 B8 PCI_FRAME#
PCI_PIRQD# AD23 FRAME#
1 2 E4 AD24
R170 8.2K_0402_5% B2 A21 PLT_RST#
PCI_PIRQE# AD25 PLTRST# CLK_PCI_ICH PLT_RST# <8,21>
1 2 C4 B5 CLK_PCI_ICH <16>
R171 8.2K_0402_5% AD26 PCICLK PCI_PME#
C1 AD27 PME# T1 PCI_PME# <21>
1 2 PCI_PIRQF# D1
R172 47K_0402_5% AD28
E2 AD29
1 2 PCI_PIRQG# J4
R173 8.2K_0402_5% AD30
H2 AD31
2 1 PCI_PIRQH#
R174 8.2K_0402_5% Interrupt I/F
C PCI_REQ0# PCI_PIRQA# PCI_PIRQE# C
1 2 F1 PIRQA# PIRQE#/GPIO2 G3
R175 8.2K_0402_5% PCI_PIRQB# F5 G1 PCI_PIRQF#
PCI_REQ1# PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
1 2 F2 PIRQC# PIRQG#/GPIO4 F3
R176 8.2K_0402_5% PCI_PIRQD# C7 H4 PCI_PIRQH#
PCI_REQ2# PIRQD# PIRQH#/GPIO5
1 2
R178 8.2K_0402_5% ICH9-M SFF ES_FCBGA569
1 2 PCI_REQ3#
R179 8.2K_0402_5%
A16 swap override Strap Boot BIOS Strap Place closely pin B10
B B
Low= A16 swap override Enble CLK_PCI_ICH
PCI_GNT3# High= Default* PCI_GNT0# SPI_CS#1 Boot BIOS Location
1
@
R180
10_0402_5%
0 1 SPI
2
PCI_GNT3# 1
@
1 0 PCI C235
1
8.2P_0402_50V
2
R181
@ 1K_0402_5% 1 1 LPC *
2
PCI_GNT0#
<19> KBC_SPI_CS1#
1
R182 R183
1K_0402_5% @ 1K_0402_5%
@
2
A A
DEL J3. 9/29

ICH9(1/4)-PCI/INT
5 4 3 2 1
5 4 3 2 1
+RTCVCC
1 2 LAN100_SLP
R184 330K_0402_1%
1 2 SM_INTRUDER#
R185 1M_0402_5%
1 2 ICH_INTVRMEN
R186 330K_0402_1%
0_0402_5%
0_0402_5%
R188
R189
1 2 ICH_SRTCRST#
2
R187 20K_0402_5%
Change from 180K to 20K C236
1
& 0.1u to 1u. 9/29
1U_0603_10V4Z @ @
1
D 2 D
ICH_RSVD HDA_SDOUT_CODEC Description <21> ICH_RTCRST#
0 0 RV U5A
LPC_AD[0..3] <21>
ICH_RTCX1 LPC_AD0 9/27
0 1 XOR ICH_RTCX2
F25
G25
RTCX1
RTCX2
FWH0/LAD0
FWH1/LAD1
H3
J3 LPC_AD1
R318 LPC_AD2
1 0 Normal(D) +RTCVCC 1 2 ICH_RTCRST# G24 RTCRST#
FWH2/LAD2
FWH3/LAD3
K5
L3 LPC_AD3 Del PU R203~R204 9/27
20K_0402_5% ICH_SRTCRST#
1 1 PCIE Bit1 C24 for H_DPRSTP# &
RTC
LPC
SM_INTRUDER# SRTCRST#
C23 INTRUDER# FWH4/LFRAME# J2 LPC_FRAME# <21>
XOR CHAIN ENTRANCE STRAP:RSVD 1 H_DPSLP#. +VCCP
1
C1044 CLRP1 ICH_INTVRMEN E25 H1
+3VS SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
D25 LAN100_SLP LDRQ1#/GPIO23 J1 T46 PAD
1U_0603_10V4Z
2
2 G22 N3 GATEA20
HDA_SDOUT GLAN_CLK A20GATE GATEA20 <21>
1 2 AB23 R192
A20M# H_A20M# <4>
R191 @ 1K_0402_5% D14 56_0402_5%
ICH_RSVD LAN_RSTSYNC H_DPRSTP_R# R194
1 2 ICH_RSVD <19> AE23 1 2 0_0402_5% H_DPRSTP# <5,8,28>
R193 @ 1K_0402_5% DPRSTP#
A14 AE24 H_DPSLP# <5>
1
LAN / GLAN
LAN_RXD0 DPSLP#
D12 LAN_RXD1
B14 AD25 H_FERR#_R R195 1 2 56_0402_5% H_FERR#
LAN_RXD2 FERR# H_FERR# <4>
D13 LAN_TXD0 CPUPWRGD AE22 H_PWRGOOD <5>
C13 LAN_TXD1
Place Close to U8.
Add C599 ~ C602 to solve WWAN noise issue. 1/23 A13 LAN_TXD2 IGNNE# AD23 H_IGNNE# <4>
+3VS
CPU
PAD T47 D15 GPIO56 INIT# AE21 H_INIT# <4>
AD24 +VCCP GATEA20 R196 1 2 10K_0402_5%
C INTR KB_RST# H_INTR <4> KB_RST# R197 C
H22 GLAN_COMPI RCIN# L1 KB_RST# <21> 1 2 10K_0402_5%
@ C1047 12P_0402_50V8J +1.5VS R198 1 2 24.9_0402_1% GLAN_COMP H21 GLAN_COMPO
1
Remove R227 & C199 HDA_BITCLK 1 2 AD21
HDA_BITCLK AE7 NMI H_SMI# H_NMI <4>
<21> HDA_BITCLK AC21 R201
HDA_SYNC HDA_BIT_CLK SMI# H_SMI# <4>
AB7 56_0402_5%
<21> HDA_SYNC HDA_SYNC H_STPCLK#
STPCLK# AC25 H_STPCLK# <4>
HDA_RST# AA7
<21> HDA_RST#
2
HDA_RST# THRMTRIP_ICH# R206
AC23 1 2 54.9_0402_1% H_THERMTRIP# <4,8>
THRMTRIP#
<21> HDA_SDIN0 AB6
HDA_SDIN0
placed within 2" from
<21> HDA_SDIN1 AE6 AC22 T48 PAD ICH9M
HDA_SDIN1 TP11
<8> HDA_SDIN2 AC6
IHDA
HDA_SDIN2
AA5
HDA_SDIN3 SATA_RXN2_C
AD12 SATA_RXN2_C <21>
HDA_SDOUT SATA4RXN SATA_RXP2_C
<21> HDA_SDOUT AC7 AE12 SATA_RXP2_C <21>
HDA_SDOUT SATA4RXP SATA_TXN2_RC1056 SATA_TXN2_CR
SATA4TXN
AB12 1 2 0.01U_0402_16V7K SATA_TXN2_CR <21>
AD8 AA12 SATA_TXP2_RC1065 1 SATA_TXP2_CR
2 0.01U_0402_16V7K
HDA_DOCK_EN#/GPIO33 SATA4TXP SATA_TXP2_CR <21>
PAD T49 AB8
HDA_DOCK_RST#/GPIO34 0408
+3VS 2 1 SATA5RXN
AC11
R209 10K_0402_5% AC9 AD11
<21> IDE_LED# SATALED# SATA5RXP
AB10
SATA_RXN0_C SATA5TXN
<21> SATA_RXN0_C AE14 AA10
SATA_RXP0_C SATA0RXN SATA5TXP
<21> SATA_RXP0_C AD14
SATA0RXP
SATA
SATA_TXN0_CR C1051 1 SATA_TXN0_R
2 0.01U_0402_16V7K AC15 AC16 CLK_PCIE_SATA#
<21> SATA_TXN0_CR SATA0TXN SATA_CLKN CLK_PCIE_SATA# <16>
SATA_TXP0_CR C1052 1 SATA_TXP0_R
2 0.01U_0402_16V7K AD15 AB16 CLK_PCIE_SATA
<21> SATA_TXP0_CR SATA0TXP SATA_CLKP CLK_PCIE_SATA <16>
SATA_RXN1_C AD13 AD10
<21> SATA_RXN1_C SATA1RXN SATARBIAS#
SATA_RXP1_C AC13 AE10 R212 1 2 24.9_0402_1%
<21> SATA_RXP1_C SATA1RXP SATARBIAS
SATA_TXN1_CR C1053 1 SATA_TXN1_R
2 0.01U_0402_16V7K AA14
<21> SATA_TXN1_CR SATA_TXP1_CR C1054 1 SATA_TXP1_R
2 0.01U_0402_16V7K AB14
SATA1TXN Within 500 mils
<21> SATA_TXP1_CR SATA1TXP
ICH9-M SFF ES_FCBGA569
B ICH_RTCX1 B
R215
1 2 ICH_RTCX2
10M_0402_5%
C246
C247
Y2
4
1 1
32.768KHZ_12.5P_1TJS125BJ2A251
OUT
IN
2 2
12P_0402_50V8J
12P_0402_50V8J
NC
NC
2
A A

ICH9(2/4)_LAN,HD,IDE,LPC
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
+3VS
+3VALW
1 2 GPIO48
1
R271 10K_0402_5%
1 2 GPIO1
R220 10K_0402_5% R223 R224
1 2 SIRQ 2.2K_0402_5% 2.2K_0402_5%
R222 10K_0402_5% U5C
2
1 2 PM_CLKRUN# ICH_SMB_CLK C18 SMBCLK SATA0GP/GPIO21 AE19 GPIO21
R225 8.2K_0402_5% ICH_SMB_DATA C15 AA18 HDD_HALTLED
SMBDATA SATA1GP/GPIO19
1 2 THERM_SCI# LINKALERT# B21 AE20 NPCI_RST#
SATA
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
GPIO
SMB
R227 @ 8.2K_0402_5% 9/21 ME__EC_CLK1 E18 AA20 GPIO37 PM_PWROK 1 2 M_PWROK
SMLINK0 SATA5GP/GPIO37
1 2 GPIO22 ME__EC_DATA1 A24 R221 0_0402_5%
R231 8.2K_0402_5% SMLINK1 CLK_14M_ICH
K1 CLK_14M_ICH <16>
+3VS CLK14
1 2 NPCI_RST# EC_SWI# C20 AB5 CLK_48M_ICH
Clocks
D <21> EC_SWI# RI# CLK48 CLK_48M_ICH <16> D
R232 10K_0402_5%
1 2 GPIO17 T5
SUS_STAT#/LPCPD# SUSCLK
R3 ICH_SUSCLK T50 PAD
R233 @ 8.2K_0402_5% XDP_DBRESET# C25
<4> XDP_DBRESET# SYS_RESET#
1
1 2 GPIO37 D18 SLP_S3#
PM_BMBUSY# SLP_S3# SLP_S4# SLP_S3# <21>
R237 8.2K_0402_5% R235 R236 L2 B20
<8> PM_BMBUSY# PMSYNC#/GPIO0 SLP_S4# SLP_S4# <21>
1 2 GPIO18 @ 10K_0402_5% @ 10K_0402_5% D16 SLP_S5#
LID_SW# SLP_S5# SLP_S5# <21>
R238 10K_0402_5% <21> LID_SW# A23
SMBALERT#/GPIO11
1 2 GPIO57 Add R621 in 12/03. E14 S4_STATE#
PM_PWROK <8,21,28>
2
R239 @ 10K_0402_5% R444 1 H_STP_PCI# S4_STATE#/GPIO26
<16> H_STP_PCI# 2 0_0402_5% B15
STP_PCI#/GPIO15 R241 1 100K_0402_5%
SYS GPIO
<16> H_STP_CPU# A20 D23 2
+3VALW STP_CPU#/GPIO25 PWROK
PM_CLKRUN# M5 M1 DPRSLPVR 1 2
CLKRUN#/GPIO32 DPRSLPVR/GPIO16 PM_DPRSLPVR <8,28>
R243 0_0402_5%
2 LINKALERT# PCIE_WAKE# ICH_LOW_BAT#
Power MGT
1 <21> PCIE_WAKE# C21 WAKE# BATLOW# C16
R244 10K_0402_5% SIRQ L4
<21> SIRQ SERIRQ
1 2 PCIE_WAKE# <21> THERM_SCI#
THERM_SCI# AD20 U4 ON/OFFBTN# <21>
LAN_RST 2 1
R245 10K_0402_5% THRM# PWRBTN# 10K_0402_5% R273
1 2 EC_SWI# <21,28> VGATE
R247 1 2 0_0402_5% VRMPWRGD B24 D22 LAN_RST
R246 10K_0402_5% R248 1 100K_0402_5% VRMPWRGD LAN_RST#
2
1 2 XDP_DBRESET# PAD T51 A19 D19 EC_RSMRST#R 1 2
R250 1K_0402_5% TP12 RSMRST# R453 10K_0402_5%
1 2 S4_STATE# GPIO1 AE16 U1 CK_PWRGD_R 1 2 CK_PWRGD <16>
R252 10K_0402_5% <21> GPIO1 GPIO6 GPIO1 CK_PWRGD R253 0_0402_5%
AE18 GPIO6
<21> GPIO6
1 2 ICH_LOW_BAT# PAD T55 AD18 T4 M_PWROK
M_PWROK <8>
R254 10K_0402_5% GPIO7 CLPWROK
<21> EC_SMI# B25 GPIO8
1 2 GPIO24 <21> EC_SCI# C14 GPIO12 SLP_M# B23
R256 10K_0402_5% D20 R257
GPIO13
1 2 AC_IN GPIO17 AE17 GPIO17 CL_CLK0 C22 CL_CLK0
CL_CLK0 <8>
3.24K_0402_1%
R258 @ 100K_0402_5% GPIO18 K3 A18 1 2 +3VS
GPIO18 CL_CLK1
0.1U_0402_16V4Z
1 2 ME__EC_CLK1 PAD T52 AC8 GPIO20
1
453_0402_1%
R259 10K_0402_5% GPIO22 AC19 E22 CL_DATA0
SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <8>
1 2 ME__EC_DATA1 D17 B18
Controller Link
PAD T53 1
GPIO
C GPIO27 CL_DATA1
2 R260
R261 10K_0402_5% C
PAD T54 E20 GPIO28
RP29 M4 F21 CL_VREF0_ICH
<16> CLKSATAREQ# SATACLKREQ#/GPIO35 CL_VREF0
C263
5 4 USB_OC#7 GPIO38 AB18 A17
USB_OC#5 GPIO39 SLOAD/GPIO38 CL_VREF1 2
6 3 AC18 SDATAOUT0/GPIO39
7 2 USB_OC#0 GPIO48 AB19 C17 CL_RST#
USB_OC#4 <21> GPIO48 SDATAOUT1/GPIO48 CL_RST0# CL_RST# <8>
8 1 AC20 GPIO49 CL_RST1# B17
GPIO57 A16
10K_1206_8P4R_5% R264 1 GPIO57/CLGPIO5 GPIO24
+3VS 2 @ 1K_0402_5% A22 GPIO24 <21>
RP30 SB_SPKR MEM_LED/GPIO24
5 4 USB_OC#1
<21> SB_SPKR
<8> MCH_ICH_SYNC#
MCH_ICH_SYNC#
K4
AB20
SPKR
MCH_SYNC#
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
E16
A15 AC_IN
AC_IN <21>
RSMRST circuit
6 3 USB_OC#6 <18> ICH_RSVD
ICH_RSVD C19
TP3 WOL_EN/GPIO9
D21 WOL_EN
MISC
7 2 GPIO44 AB17 @ R454
TP8
8 1 USB_OC#2 AC17
TP9 Add WOL_EN back. 10/10 0_0402_5%
PAD T59 AD17 1 2
10K_1206_8P4R_5% TP10
ICH9-M SFF ES_FCBGA569
1 2 USB_OC#10 U5D 3 1 EC_RSMRST#R
C
<21> EC_RSMRST#
R281 10K_0402_5% GLAN_RXN DMI_RXN0 Q26
E
<21> GLAN_RXN T25 PERN1 V25 DMI_RXN0 <8>
DMI0RXN
1 2 USB_OC#11 GLAN_RXP T24 PERP1 V24 DMI_RXP0 BAV99DW-7_SOT363 MMBT3906_SOT23-3
Direct Media Interface

<21> GLAN_RXP DMI0RXP DMI_RXP0 <8>
R282 10K_0402_5% C271 1 2 0.1U_0402_10V7K GLAN_TXN_C R24 PETN1 U24 DMI_TXN0 1 2
B
<21> GLAN_TXN DMI_TXN0 <8> +3VALW
1 2
DMI0TXN
1 2 USB_OC#9 <21> GLAN_TXP C272 1 2 0.1U_0402_10V7K GLAN_TXP_C R23 PETP1 U23 DMI_TXP0
DMI_TXP0 <8> R455 4.7K_0402_5%
DMI0TXP
2
R272 10K_0402_5%
1 2 LID_SW# <21> PCIE_RXN2
PCIE_RXN2 P25 W23 DMI_RXN1 DMI_RXN1 <8> @ D13B
R269 10K_0402_5% PCIE_RXP2 PERN2 DMI1RXN DMI_RXP1 R456
<21> PCIE_RXP2 P24 W24 DMI_RXP1 <8>
PERP2 DMI1RXP
1 2 GPIO42 <21> PCIE_TXN2 C265 1 2 0.1U_0402_10V7K PCIE_C_TXN2 P21 WLAN V21 DMI_TXN1
DMI_TXN1 <8> 2.2K_0402_5% D13A
R270 10K_0402_5% C266 1 0.1U_0402_10V7K PCIE_C_TXP2 PETN2 DMI1TXN DMI_TXP1 BAV99DW-7_SOT363
<21> PCIE_TXP2 2 P22 V22 DMI_TXP1 <8>
1
PETP2 DMI1TXP
1 2 WOL_EN R457
6
R277 10K_0402_5% N23 Y24 DMI_RXN2 DMI_RXN2 <8> 1 2
PERN3 DMI2RXN DMI_RXP2
N24 Y25
PCI-Express
PERP3 DMI2RXP DMI_RXP2 <8>
M21 EXP Y21 DMI_TXN2 2.2K_0402_5%
PETN3 DMI2TXN DMI_TXN2 <8>
M22 Y22 DMI_TXP2
PETP3 DMI2TXP DMI_TXP2 <8>
B PCIE_RXN4 M25 DMI_RXN3 B
<21> PCIE_RXN4 AB24 DMI_RXN3 <8>
PCIE_RXP4 PERN4 DMI3RXN DMI_RXP3
<21> PCIE_RXP4 M24 AB25 DMI_RXP3 <8>
PERP4 DMI3RXP
<21> PCIE_TXN4 C269 1 2 0.1U_0402_10V7K PCIE_C_TXN4 L24 PETN4 WWAN DMI3TXN
AA23 DMI_TXN3
DMI_TXN3 <8>
<21> PCIE_TXP4 C270 1 2 0.1U_0402_10V7K PCIE_C_TXP4 L23 PETP4 DMI3TXP
AA24 DMI_TXP3
DMI_TXP3 <8>
K24 T21 CLK_PCIE_ICH#
+3VS PERN5 DMI_CLKN CLK_PCIE_ICH CLK_PCIE_ICH# <16>
K25 T22 CLK_PCIE_ICH <16>
PERP5 DMI_CLKP
K21
PETN5
K22
PETP5 DMI_ZCOMP
AB21 Within 500 mils
1 2 GPIO38 DMI_IRCOMP
AB22 DMI_IRCOMP R276 1 2 24.9_0402_1% +1.5VS
R262 8.2K_0402_5% H24
PERN6/GLAN_RXN
2 GPIO21
GLAN
1 H25 AE2 USB20_N0 <21>
R234 8.2K_0402_5% PERP6/GLAN_RXP USBP0N
J24 AD1 USB20_P0 <21>
PETN6/GLAN_TXN USBP0P
1 2 HDD_HALTLED J23 AD3 USB20_N1 <21>
R230 47K_0402_5% PETP6/GLAN_TXP USBP1N
AD4 USB20_P1 <21>
USBP1P
1 2 GPIO39 E24 AC2 USB20_N2 <21>
R240 8.2K_0402_5% SPI_CLK USBP2N
E23 AC3 USB20_P2 <21>
SPI_CS0# USBP2P
F23 AC5 USB20_N3 <21>
<17> KBC_SPI_CS1# SPI_CS1#/GPIO58/CLGPIO6 USBP3N
1 2 GPIO38 AB4 USB20_P3 <21>
@R279
@ R279 10K_0402_5% USBP3P
F22
SPI_MOSI USBP4N
AB2 USB20_N4 <21> Place closely pin AF3 Place closely pin H1
SPI
1 2 GPIO21 G23 AB1 USB20_P4 <21>

@R280
@ R280 10K_0402_5% SPI_MISO USBP4P
AA3 USB20_N5 <21>
USBP5N
1 2 HDD_HALTLED <21> USB_OC#0
USB_OC#0 P4 AA2 USB20_P5 <21>
CLK_48M_ICH CLK_14M_ICH
@ R242 47K_0402_5% USB_OC#1 OC0#/GPIO59 USBP5P
<21> USB_OC#1 N4 Y1 USB20_N6 <21>
OC1#/GPIO40 USBP6N
1 2 GPIO39 <21> USB_OC#2
USB_OC#2 N1 USB Y2 USB20_P6 <21>
OC2#/GPIO41 USBP6P
1
@R285
@ R285 10K_0402_5% GPIO42 P5 W2 @ @
<21> GPIO42 OC3#/GPIO42 USBP7N USB20_N7 <21>
USB_OC#4 P1 W3 R283 R284
USB_OC#5 OC4#/GPIO43 USBP7P USB20_P7 <21>
P2 V1 10_0402_5% 10_0402_5%
USB_OC#6 OC5#/GPIO29 USBP8N USB20_N8 <21>
M3 V2 USB20_P8 <21>
+3VS USB_OC#7 OC6#/GPIO30 USBP8P
M2 Y5
2
GPIO44 OC7#/GPIO31 USBP9N
P3 Y4
<21> GPIO44 USB_OC#9 OC8#/GPIO44 USBP9P
A
R1 OC9#/GPIO45 USBP10N U3 1 @ 1 @ A
R275 USB_OC#10 R4 U2 C273 C274
OC10#/GPIO46 USBP10P
1
2.2K_0402_5% USB_OC#11 R2 V4
R274 OC11#/GPIO47 USBP11N 4.7P_0402_50V8C 4.7P_0402_50V8C
USBP11P V5
2.2K_0402_5% Q8 USBRBIAS 2 2
AE5 USBRBIAS
RHU002N06_SOT323 AD5 USBRBIAS#
1
Within 500 mils

2
2
S
ICH_SMBDATA 3 1 ICH_SMB_DATA ICH9-M SFF ES_FCBGA569

<14,15,16,21> ICH_SMBDATA
R287
S
ICH_SMBCLK 3 1 ICH_SMB_CLK 22.6_0402_1%

<14,15,16,21> ICH_SMBCLK
2006/02/20 2009/02/20 Title
G
Issued Date Deciphered Date

2
+3VS Q9
RHU002N06_SOT323 ICH9(3/4)_DMI,USB,GPIO,PCIE
G
2
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
+RTCVCC +VCCP U5E

20 mils U5F B4 VSS[001] VSS[107] U5
G17 VCCRTC VCC1_05[01] L11 B7 VSS[002] VSS[108] U10
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VCC1_05[02] L12 B10 VSS[003] VSS[109] W11
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 ICH_V5REF_RUN G7 L13 B13 U14
V5REF VCC1_05[03] VSS[004] VSS[110]
C275
C276
VCC1_05[04] L14 1 1 B16 VSS[005] VSS[111] W16
ICH_V5REF_SUS U7 L15 B19 U21
V5REF_SUS VCC1_05[05] VSS[006] VSS[112]
VCC1_05[06] M11 B22 VSS[007] VSS[113] U22
2 2
C277
C278
J19 VCC1_5_B[01] VCC1_05[07] M15 D2 VSS[008] VSS[114] U25
+1.5VS_PCIE_ICH K18 N11 2 2 D24 V3
VCC1_5_B[02] VCC1_05[08] VSS[009] VSS[115]
K19 VCC1_5_B[03] VCC1_05[09] N15 E5 VSS[010] VSS[116] V8
L18 VCC1_5_B[04] VCC1_05[10] P11 E7 VSS[011] VSS[117] V19
L19 P15 E9 V23
R289 VCC1_5_B[05] VCC1_05[11] VSS[012] VSS[118]
40 mils M18
VCC1_5_B[06] VCC1_05[12]
R11 E11
VSS[013] VSS[119]
W1
+1.5VS 1 2 M19
VCC1_5_B[07] VCC1_05[13]
R12 E13
VSS[014] VSS[120]
W4
D BLM18PG181SN1D_0603 D
N18 R13 E15 W5
VCC1_5_B[08] VCC1_05[14] VSS[015] VSS[121]
10U_0603_6.3V6M
10U_0603_6.3V6M
2.2U_0402_6.3V6M
1 1 1 N19 R14 E17 W7
VCC1_5_B[09] VCC1_05[15] VSS[016] VSS[122]
220U_D2_4VM_R15
1 P18 R15 E19 W9
VCC1_5_B[10] VCC1_05[16] VSS[017] VSS[123]
R18
VCC1_5_B[11] 9/29 E21
VSS[018] VSS[124]
W15
C279
C280
C281
+ T18 R290 F24 W19
2 2 2 VCC1_5_B[12] VSS[019] VSS[125]
T19 1 2 +1.5VS G2 W21
VCC1_5_B[13] VCC_DMI VSS[020] VSS[126]
C282
1U_0603_10V4Z
0.01U_0402_16V7K
U18 G5 W22
CORE
2 VCC1_5_B[14] VSS[021] VSS[127]
U19
VCC1_5_B[15] 1 1 MBK1608301YZF 0603 G10
VSS[022] VSS[128]
W25
1U_0603_10V4Z
G13 Y3
VSS[023] VSS[129]
1 G16 Y23
VSS[024] VSS[130]
C283
C284
G19 AA1
2 2 VSS[025] VSS[131]
G21 VSS[026] VSS[132] AA4
C285
H10 VSS[027] VSS[133] AA6
2 H12 AA8
+1.5VS_DMIPLL VSS[028] VSS[134]
VCCDMIPLL P19 H18 VSS[029] VSS[135] AA11
9/29 9/29 +VCCP
H23 VSS[030] VSS[136] AA13
T17 R292 J5 AA15
+5VS +3VS +5VALW +3VALW VCC_DMI[1] VCC_DMI VSS[031] VSS[137]
VCC_DMI[2] U17 1 2 +VCCP J9 VSS[032] VSS[138] AA16
(DMI) J10 AA17
MBK1608301YZF 0603 VSS[033] VSS[139]
V_CPU_IO[1] V16 J11 VSS[034] VSS[140] AA19
1
2
V_CPU_IO[2] U16 J12 VSS[035] VSS[141] AA21
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
R293 D5 R294 D6 J13 AA22
VSS[036] VSS[142]
VCC3_3[01] V18 +3VS 1 1 J15 VSS[037] VSS[143] AA25
100_0402_5% CH751H-40_SC76 100_0402_5% CH751H-40_SC76 J21 AB3
VSS[038] VSS[144]
VCCA3GP
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AE9 J22 AB9
2
1 VCC3_3[02] VSS[039] VSS[145]
C286
ICH_V5REF_SUS 1 1 1 J25 AB11
2 2 VSS[040] VSS[146]
C287
ICH_V5REF_RUN 20 mils K2 AB13
VSS[041] VSS[147]
20 mils K9 VSS[042] VSS[148] AB15
C288
C289
C290
1 1 VCC3_3[03] AA9 K10 VSS[043] VSS[149] AC24
C291 C292 V14 2 2 2 K11 AC1
VCC3_3[04] +3VS VSS[044] VSS[150]
VCC3_3[05] W14 K12 VSS[045] VSS[151] AC4
C
9/19 2
1U_0402_6.3V6K
2
0.1U_0402_16V4Z K13 VSS[046] VSS[152] AC10
C
VCCP_CORE
K15 VSS[047] VSS[153] AC12
0.1U_0402_16V4Z
VCC3_3[06] G8 K17 VSS[048] VSS[154] AC14
VCC3_3[07] H7 1 K23 VSS[049] VSS[155] AD2
VCC3_3[08] H8 L5 VSS[050] VSS[156] AD6
L9 VSS[051] VSS[157] AD9
C293
@ R322 1 2 0_0603_5% +3VS L10 AD16
2 VSS[052] VSS[158]
L16 VSS[053] VSS[159] AD19
+1.5VS_VCCSATAPLL R323 1 2 0_0603_5% L17 AD22
+1.5VS VSS[054] VSS[160]
PCI
L21 AE3
VSS[055] VSS[161]
AD7 L22 AE4
VCCHDA VSS[056] VSS[162]
0.1U_0402_16V4Z
R296 R319 180_0402_1% L25 AE11
VSS[057] VSS[163]
+1.5VS 1 2 W17 V10 1 2 +3VALW M9 AE13
VCCSATAPLL VCCSUSHDA VSS[058] VSS[164]
0.1U_0402_16V4Z
MBK1608301YZF 0603 1 M10 AE15
VSS[059] VSS[165]
1
+1.5VS U13 T7 VCCSUS1_05_ICH_1 T60 1 1 2 +3VALW M12 V17
VCC1_5_A[01] VCCSUS1_05[1] VSS[060] VSS[166]
10U_0603_6.3V6M
1U_0603_10V4Z
1U_0402_6.3V6K
1 1 V13 H15 VCCSUS1_05_ICH_2 T61 R320 R324 0_0603_5% M13 AE8

VCC1_5_A[02] VCCSUS1_05[2] VSS[061] VSS[167]
C294
1 W13
VCC1_5_A[03] 150_0402_1%@ +1.5VALW 2
M14
VSS[062] VSS[168]
V9
ARX
C296
C295
H16 VCCSUS1_5_ICH_1 T62 M16 J16
VCCSUS1_5[1] 2 VSS[063] VSS[169]
C297
M17
2
2 2 VSS[064]
C298
V7 VCCSUS1_5_ICH_2 T63 M23

2 VCCSUS1_5[2] VSS[065]
N2
VSS[066]
N5
VSS[067]
G14 +3VALW N9
VCCSUS3_3[01] VSS[068]
U12 G15 N10
VCC1_5_A[04] VCCSUS3_3[02] VSS[069]
1U_0603_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V12 H14 N12
VCC1_5_A[05] VCCSUS3_3[03] VSS[070]
VCCPSUS
1 W12 1 1 N13
VCC1_5_A[06] +3VALW VSS[071]
ATX
N14
VSS[072]
N16
VSS[073]
C299
C300
C301
W8 N17
2 VCCSUS3_3[04] 2 2 VSS[074]
N21
VSS[075]
4.7U_0603_6.3V6K
J7 N22
J8 1 N25
W10 K7 P9
B VCC1_5_A[07] VCCSUS3_3[07] VSS[078] B
0.1U_0402_16V4Z
K8 P10
1 U15 L7 P12
VCC1_5_A[08] VCCSUS3_3[09] 2 VSS[080]
C302
V15 L8 P13
VCC1_5_A[09] VCCSUS3_3[10] VSS[081]
M7 P14
W18 M8 P16
2 VCC1_5_A[10] VCCSUS3_3[12] VSS[083]
C303
N7 P17
VCCPUSB
G9 N8 P23
VCC1_5_A[11] VCCSUS3_3[14] VSS[085]
H9 P7 R5
VCC1_5_A[12] VCCSUS3_3[15] VSS[086]
P8 R7
+1.5VS_USBPLL VCCSUS3_3[16] VSS[087]
V11 R8
VCC1_5_A[13] VSS[088]
U11
VCC1_5_A[14] 9/21 R9
VSS[089]
C304 R10
R298 0.1U_0402_16V4Z VSS[090]
R16
VCCCL1_05_ICH 1 VSS[091]
+1.5VS 1 2 U8 G18 2 R17
VCCUSBPLL VCCCL1_05 VSS[092]
R19
VSS[093]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
MBK1608301YZF 0603 1 1 T9 H17 1 2 R21 A1

VCC1_5_A[15] VCCCL1_5 VSS[094] VSS_NCTF[01]
USB CORE
U9 C305 1U_0402_6.3V6K R22 A25

VCC1_5_A[16] VSS[095] VSS_NCTF[02]
J14 R25 AE1
VCCCL3_3[1] +3VS 9/21 VSS[096] VSS_NCTF[03]
C306
C307
K14 T2 AE25
2 2 C308 VCCCL3_3[2] VSS[097] VSS_NCTF[04]
T8
0.1U_0402_16V4Z VSS[098]
T10
+3VS VCC_LAN1_05_INT_ICH VSS[099]
2 1 G11
VCCLAN1_05[1]
T11
VSS[100]
H11 T12
R303 VCCLAN1_05[2] VSS[101]
T13
VSS[102]
1 2 G12 T14
R304 VCCLAN3_3[1] VSS[103]
H13 T15
MBK1608301YZF 0603 MBK1608301YZF 0603 VCCLAN3_3[2] VSS[104]
T16
+1.5VS_GLAN VSS[105]
+1.5VS 1 2 J17 T23
VCCGLANPLL VSS[106]
0.1U_0402_16V4Z
1
GLAN POWER
H19 ICH9-M SFF ES_FCBGA569

+1.5VS_PCIE_ICH VCCGLAN1_5[1]
10U_0603_6.3V6M
1 J18
VCCGLAN1_5[2]
C309
2
10U_0603_6.3V6M
A A
1
C310
2
+3VS K16 VCCGLAN3_3
C311
2 ICH9-M SFF ES_FCBGA569

ICH9(4/4)_POWER&GND
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
B+
HDI_B_DET
0.1U_0603_50V4Z~D
JP6
+RTCVCC 1 2
VS B+ +5VS +5VS
1 3 B+ +5VALW 4 +5VALW
C1033
2.2U_0603_6.3V4Z
5 B+ +VL 6 VL
1 7 B+ +3VALW 8 +3VALW
9 B+ +3VS 10 +3VS
2
C1055
11 B+ +3VS 12
13 14
2 B+ +3VS
15 16 VR_ON <28>
RESERVED VR_ON
17 18
D +RTCVCC GND HDI_B_DET/GND D
19 20
GND GND
21 22
GND GND
<28> MAINPWON 23 24
MAINPWON GND
25 26 SB_SPKR <19>
+RTCVCC SB_SPKR
<18> ICH_RTCRST# 27 28 HDA_RST# <18>
ICH_RTCRST# HDA_RST#
<19> GPIO1 29 30 HDA_SDOUT <18>
GPIO1 HDA_SDOUT R314
<4> EC_SMB_DA2 31 32 HDA_SYNC <18>
EC_SMB_DA2 HDA_SYNC HDA_BITCLK
<4> EC_SMB_CK2 33 34 HDA_BITCLK <18> <8> HDA_BITCLK_NB 1 2
EC_SMB_CK2 HDA_BITCLK
<19> GPIO6 35 36 HDA_SDIN0 <18>
GPIO6 HDA_SDIN0
GPIO <19> GPIO48 37
GPIO48 HDA_SDIN1
38 HDA_SDIN1 <18>
33_0402_5%
39 40 IDE_LED# <18> R315
<19> EC_SMI# EC_SMI# DE_LED# HDA_RST#
<10> L_BKLT_CTRL 41 L_BKLT_CTRL SATA0TXP 42 SATA_TXP0_CR <18> <8> HDA_RST#_NB 1 2
<19> PCIE_TXP4 43 PETP4 SATA0TXN 44 SATA_TXN0_CR <18>
45 46 33_0402_5%
<19> PCIE_TXN4 PETN4 GND
47 48 R316
GND THERM_SCI# THERM_SCI# <19>
HDA_SDOUT
<19> PCIE_RXP4 49 PERP4 GPIO42 50 GPIO42 <19> GPIO <8> HDA_SDOUT_NB 1 2
WWAN <19> PCIE_RXN4 51 PERN4 GND 52
53 54 33_0402_5%
GND SATA1TXP SATA_TXP1_CR <18>
55 56 R317
<19> PCIE_TXP2 PETP2 SATA1TXN SATA_TXN1_CR <18> HDA_SYNC
<19> PCIE_TXN2 57 PETN2 GND 58 <8> HDA_SYNC_NB 1 2
59 GND 1.5VS 60 +1.5VS
WLAN <19> PCIE_RXP2 61 PERP2 1.5VS 62 33_0402_5%
<19> PCIE_RXN2 63 PERN2 GND 64
65 GND SATA2TXP 66 SATA_TXP2_CR <18>
<19> GLAN_TXN 67 PETN1 SATA2TXN 68 SATA_TXN2_CR <18> SATA
LAN <19> GLAN_TXP 69 PETP1 GND 70
71 GND SATA2RXP 72 SATA_RXP2_C <18>
<19> GLAN_RXN 73 PERN1 SATA2RXN 74 SATA_RXN2_C <18>
<19> GLAN_RXP 75 PERP1 GND 76
77 GND SATA0RXP 78 SATA_RXP0_C <18>
<19> SLP_S4# 79 SLP_S4# SATA0RXN 80 SATA_RXN0_C <18>
<19,28> VGATE 81 VGATE GND 82
C C
<19> EC_RSMRST# 83 PM_RSMRST# USB20_P7 84 USB20_P7 <19>
<19> LID_SW# 85 LID_SW# USB20_N7 86 USB20_N7 <19>
<19> GPIO24 87 GPIO24 GND 88
<8,19,28> PM_PWROK 89 PM_PWROK SATA1RXP 90 SATA_RXP1_C <18>
<19> EC_SWI# 91 EC_SWI# SATA1RXN 92 SATA_RXN1_C <18>
<22,26,27,29> SUSP# 93 SUSP# GND 94
<19> AC_IN 95 AC_IN USB20_P5 96 USB20_P5 <19>
<19> USB_OC#2 97 98 USB20_N5 <19>
USB_OC2# USB20_N5
<19> USB_OC#1 99 100
USB_OC1# GND
<19> USB_OC#0 101 102 USB20_P4 <19>
USB_OC0# USB20_P4
<19> ON/OFFBTN# 103 104 USB20_N4 <19>
ON/OFFBTN# USB20_N4
<19> SLP_S5# 105 106
SLP_S5# GND
<19> SLP_S3# 107 108 USB20_P3 <19>
SLP_S3# USB20_P3
<19> EC_SCI# 109 110 USB20_N3 <19>
EC_SCI# USB20_N3
<8,17> PLT_RST# 111 112
PLT_RST# GND
<22,25,29> SYSON 113 114 GPIO44 <19>
SYSON GPIO44
<18> LPC_AD0 115
LPC_AD0 GND
116 USB
<18> LPC_AD1 117 118 USB20_P8 <19>
LPC_AD1 USB20_P8
<18> LPC_AD2 119 120 USB20_N8 <19>
LPC_AD2 USB20_N8
<18> LPC_AD3 121 122
LPC_AD3 GND
<18> LPC_FRAME# 123 124 USB20_P6 <19>
LPC_FRAME# USB20_P6
<19> SIRQ 125 126 USB20_N6 <19>
SIRQ USB20_N6
<18> KB_RST# 127 128
KB_RST# GND
<18> GATEA20 129 130 USB20_P1 <19>
GATEA20 USB20_P1
<16> CLKREQG_WWAN# 131 132 USB20_N1 <19>
CLKREQG_WWAN# USB20_N1
133 134
RESERVED GND
<10> HDMI_HPD# 135 136 USB20_P2 <19>
HDMI_HPD# USB20_P2
<16> CLK_PCI_EC 137 138 USB20_N2 <19>
CLK_PCI_EC USB20_N2
139 140
GND GND
<8> HDMIDAT 141 142 USB20_P0 <19>
HDMIDAT USB20_P0
<8> HDMICLK 143 144 USB20_N0 <19>
HDMICLK USB20_N0
145 146
B GND GND B
<10> TX2D+ 147 148 ENABLT <10>
TX2D+ ENABLT
<10> TX2D- 149 150 ENAVDD <10>
TX2D- ENAVDD
151 152 DDC2_DATA <10>
GND L_DDC_DATA
<10> TX1D+ 153 154 DDC2_CLK <10>
TX1D+ L_DDC_CLK
HDMI <10> TX1D- 155
TX1D- CRT_VSYNC
156 CRT_VSYNC <10>
157 158 CRT_HSYNC <10>
GND CRT_HSYNC
<10> TX0D+ 159 160
TX0D+ GND
<10> TX0D- 161 162 CRT_DDC_DATA <10>
TX0D- CRT_DDC_DATA
163 164 CRT_DDC_CLK <10>
GND CRT_DDC_CLK
<10> TXCD+ 165 166
TXCD+ GND
<10> TXCD- 167 168 D_RED <10>
TXCD- CRT_RED
169 170
GND GND
<16> CLKREQ_WLAN# 171 172 D_GREEN <10>
CLKREQ_WLAN# CRT_GREEN
<14,15,16,19> ICH_SMBDATA 173 174
ICH_SMBDATA GND
<14,15,16,19> ICH_SMBCLK 175 176 D_BLUE <10>
ICH_SMBCLK CRT_BLUE
<19> PCIE_WAKE# 177 178
PCIE_WAKE# GND
<17> PCI_PME# 179 180 TXOUT_L1+ <10>
PCI_PME# LCDSA_DATA_1
<16> CLK_48M_CR 181 182 TXOUT_L1- <10>
CLK_48M_CR LCDSA_DATA#_1
<16> CLKREQA# 183 184
CLKREQA# GND
<16> CLK_PCIE_WAN# 185 186 TXOUT_L0+ <10>
CLK_PCIE_WAN# LCDSA_DATA_0
WWAN_CLK <16> CLK_PCIE_WAN 187
CLK_PCIE_WAN LCDSA_DATA#_0
188 TXOUT_L0- <10>
189
GND GND
190 LVDS
<16> CLK_PCIE_MCARD# 191 192 TXOUT_L2+ <10>
CLK_PCIE_MCARD# LCDSA_DATA_2
WLAN_CLK <16> CLK_PCIE_MCARD 193
CLK_PCIE_MCARD LCDSA_DATA#_2
194 TXOUT_L2- <10>
195 196
HDI_B_DET/GND GND
<16> CLK_PCIE_LAN# 197 198 TXCLK_L+ <10>
CLK_PCIE_LAN# LCDSA_CLK
LAN_CLK <16> CLK_PCIE_LAN 199
CLK_PCIE_LAN LCDSA_CLK#
200 TXCLK_L- <10>
A A
HDI_B_DET
0409
FPC_O0P45X2P35

LCD CONN & Q-Switch & GPIO Ext.
5 4 3 2 1
5 4 3 2 1
+5VALW +5VALW
1
+1.5V +VCCP R307 R308
100K_0402_5% 100K_0402_5%
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2
2
SYSON# SUSP
3
D D
2 2 2
Q17A Q17B
C241 C240 C239
33P_0402_50V8J 33P_0402_50V8J 33P_0402_50V8J SYSON 2 5 SUSP#
1 1 1 <21,25,29> SYSON SUSP# <21,26,27,29>
@ @ @
4
+1.8V +VCCP +1.5V +0.75VS
1
H1 H2 H3 H4 H8
R309 R310 R311 R312 HOLEA HOLEA HOLEA HOLEA HOLEA
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%

Modify to 4.0mm
1
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
C C
3
Q18A Q18B Q19A Q19B H5 H6 H7 H11 H12
H10 H9 HOLEA HOLEA HOLEA HOLEA HOLEA
SUSP 2 SUSP 5 SYSON# 2 SUSP 5 HOLEA HOLEA
1
1
1
FM1 FM2 FM3 FM4
+1.5V to +1.5VS 1 1 1 1
+1.5V +1.5VS
U13
8 1
D S
7 2 1 1
D S
2
6 3 C1176 C1177
D S
10U_0805_10V4Z
1U_0603_10V4Z
1 5 4 R395
D G
10U_0805_10V4Z
C1178
B SI4800BDY-T1-E3_SO8 2 2 470_0603_5% B
1
2
1
D
2 SUSP
G
S Q24
3
2N7002_SOT23
+1.5VS_GATE
B+
R396
0.1U_0603_25V7K
100K_0402_5%
2
1 1
1
D R443 C1180
SUSP 2 0_0402_5% C1281 0.1U_0603_25V7K
G @ @
Q25 S 2 2
3
2N7002_SOT23
A A

LEDS & LID
Custom LS-5581P 2.0
5 4 3 2 1
5 4 3 2 1
D ate D escrebtion R ev.

4/16 R elaese L S5581P R 01 schem atic. 01
5/8 R 53 change to 499 O hm
D
R 68,R 69,R 70 im plem ent 75O hm D
A dd C 1303 for D D R 3 request

C hange R 149,R 177 from 33 to 15O hm
C hange C 233,C 234 from 33P to 22P
R 153 im plem ent 10K _O hm and R 156 rem ove
A dd C 1079,C 1080 for E M I
D elete R 249,R 255,R 267,R 268 for optionU SB and G P IO
D elete C 1066,C 1067,C 1068,C 1069,C 1070,C 1071 for SA TA A C cap
A dd V L voltage on JP 6.6 for O C P use
M odify SB V C C SU SH D A pow er level
M odify SB G L A N from P C IE 4 to P C IE 1
C C
D elete R 265,C 264,C 266 for C L _R E F 1

D elete R 240 for H _STP _C P U # and A dd R 444 for H _STP _P C I#
C hange R 221 connect from V G A TE to P M _P W R O K
C hange R 240 from H _STP _C P U # to H _STP _P C I#
C hange E C _SC I# from G P IO 7 to G P IO 12
D elete T56,T57,T58,R 263 for no use
A dd R 281,R 282 for U SB O C # pull high
A dd R 242,R 285 for P roject ID define
M odify H 5,H 6,H 7,H 11,H 12 footprint for M E recom m and
D elete R 251 and A dd Q 26,D 13,R 453-R 457 for R SM R ST# function
B
D elete U SB 9 pair on SB for not use B
M odify C L K _P C I_E C from U 4.15 to U 4.13

M odify pow er plane from + 1.8V S to + 1.8V for N B use
C hange N am e from D D R 3_D IM M _R E F to D D R 3_N B _R E F for D D R 3 recom m and
C hange D D R P M _E X TTS# 1 from not use to JP 3
D el R 106 for Intel R ecom m and for H D M I setting
A A

HW Changed-List History-1
5 4 3 2 1
5 4 3 2 1
AC VIN LM393
D Adapter Thermal D
in Protector
Page37
Page39
+5VALW
ADP_EN# SWITCH PWR_GD
EN0 2VREF_51125
B+
VDD VR_ON
EN0
+3VALWP 3A
B+
TPS51125 ISL6261ACRZ-T
DC/DC DC/DC
(3V/5V) (CPU_CORE)
+5VALWP 4.5A
C 51125_PWR Page47 C
Page39
CPU_CORE
+0.9VP 2A (ICCDES=18A)
B+ G2992
BQ24740 TPS51117
Charger DC/DC Page42 +1.05VCCP 8A
(1.8V) SLP_S3# EN1 TPS51117
Page41 +1.8VP 8A
SLP_S4# EN_PSV DC/DC
Page40 (1.05V)
B+ Page41
B B
EN2 TPS51117
DC/DC +1.5ALWP 4A
B+ (1.5V)
Switch SLP_S3#
B+ EN2
ISL6263 Page42
DC/DC VGA_COREP 5A
(VGA_CORE)
GFXVN_EN
Page45
Battery
A A
Title
POWER BLOCK DIAGRAM

5 4 3 2 1
A B C D
1 1
PR400
0_0402_5%
+1.5V_B+ PL400
1 2 1.5V_EN
<21,22,29> SYSON
HCB1608KF-121T30_0603
1 2 B+
1
PC400
2200P_0402_50V7K
0.1U_0402_25V6
@0.1U_0402_16V7K
4.7U_0805_25V6M
4.7U_0805_25V6-K
2
1
PC401
PC402
PC403
PC404
PR401 PC405
2
5
6
7
8
0_0402_5% 0.1U_0402_10V7K
BST_1.5V
1 2 BST_1.5V-11 2
2 2
15
14
PQ400
1
PU400 4
PR402 AO4466_SO8
PR403
EN_PSV
TP
VBST
255K_0402_1% 0_0402_5% +1.5VP
1 2 2 13 UG_1.5V 1 2 UG1_1.5V PL401
PR405 TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
+1.5VP
3
2
1
1 2 1.5V_VOUT 3 VOUT LL 12 LX_1.5V 1 2
100_0402_1% PR404 0_0402_5%
+5VALW +5VALW 1 2 1.5V_VF5FILT 4 11 1.5V_TRIP 1 PR406 2 13.7K_0402_1%
V5FILT TRIP
1
PR407 10.5K_0402_1%
1 2 1.5V_VFB 5 10 +5VALW
VFB V5DRV
5
6
7
8
PR408
+1.5VP 1
1
1
6 9 LG_1.5V 4.7_1206_5%
PGOOD DRVL
1
PGND
PC406
GND
PC407 PQ401 +
2
1 2 4.7U_0805_10V6K AO4710_SO8
2
2
4.7U_0603_6.3V6K PC408 PC409 PC410
2
1
@10P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_6.3V6K 2 220U_B2_2.5VM_R25M
4
7
8
1
PC411
@22P_0402_50V8J
2
PR409 680P_0603_50V8J
PC412
2
10K_0402_1%
1
3
2
1
2
PR410
100K_0402_1%
1 2 +1.5VP
1
<8> 1.5V_PGOOD
PC413
3 @ 0.47U_0402_6.3V6K 3
2
PJP400
+1.5VP 2 2 1 1 +1.5V
@ JUMP_43X118
4 4

1.5VP
A B C D
5 4 3 2 1
D D
PR516 PL501
2 1 VCCP_B+
<21,22,27,29> SUSP# HCB1608KF-121T30_0603
0_0402_5% PC519 1 2 B+
1
@1000P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2
1
PC504
PC505
PC506
PC507
PR511 PC511
2
5
6
7
8
0_0402_5% 0.1U_0402_10V7K
BST_VCCP 1 2 1 2
15
14
PQ502
1
PU501 4 AO4466_SO8
PR524 PR509
VBST
EN_PSV
TP
255K_0402_1% 0_0402_5% +1.05VCCP
C 1 2 2 13 UG_VCCP 1 2 UG1_VCCP PL503 C
TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
3
2
1
+1.05VCCP 1 2 3 12 LX_VCCP 1 2
PR519 0_0402_5% VOUT LL
+5VALW 1 PR517 13.7K_0402_1%
+5VALW 2 4 V5FILT TRIP 11 1 2
5
6
7
8
1
PR518 PR503
1 2 5 10 +5VALW PQ504
100_0402_1% VFB V5DRV
1
PR513
+1.05VCCP 4.12K_0402_1% 1
1
<BOM Structure> 6 9 LG_VCCP PC521 4.7_1206_5%

PGOOD DRVL
1
PGND
PC520 4.7U_0805_10V6K +
GND
2
4.7U_0603_6.3V6K 1 2 4
2
<BOM Structure> PC526 PC514 PC515
2
1
@10P_0402_50V8J TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_6.3V6K 2 220U_B2_2.5VM_R25M
8
1
PC517
@22P_0402_50V8J
2
PR504 AO4710_SO8 680P_0603_50V8J
PC527
3
2
1
2
10K_0402_1%
1
2
B B
PJP500
+1.05VCCP 1 2 +VCCP (8A,120mils ,Via NO.= 6)

PAD-OPEN 4x4m
A A

1.05VCCP
5 4 3 2 1
A B C D
1 1
+1.5V
PU600
1 6
VIN VCNTL +5VALW
10U_0805_6.3V6M
10U_0805_10V4Z
2 GND NC 5
1
PC600
PC601
2 3 VREF NC 7 2
1
2
2
4 8 PC602
PR600 VOUT NC 1U_0603_10V6K
2
1K_0402_1% 9
2
+5VALW TP
G2992F1U_SO8
1
PR601 +0.75VSP
0.1U_0402_10V7K
10K_0402_5%
D
1
PR602
1
2 1K_0402_1%
G PC604
2
10U_0805_6.3V6M
PC603
S
2
D
1
1 2 2 PQ601
<21,22,26,29> SUSP# PR603 G SSM3K7002FU_SC70-3 PQ600
1
S SSM3K7002FU_SC70-3
0_0402_5%
3
PC605 2
@0.1U_0402_16V7K
3 3
PJP600
+0.75VSP 1 2 +0.75VS (2A,80mils ,Via NO.= 4)

PAD-OPEN 3x3m
4 4

0.75VSP
A B C D
5 4 3 2 1
+VCCP
2
PR200 PR202
@ 68_0402_5% 0_0402_5%
<8,19> PM_DPRSLPVR 1 2 +5VALW
<5>
<5>
<5>
<5>
<5>
<5>
<5>
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
+CPU_B+
<21>
PR203 PL200
VR_ON
0_0402_5% HCB2012KF-121T50_0805
2
<5,8,18> H_DPRSTP# 1 2 1 2 B+
2200P_0402_50V7K
0.1U_0603_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
D PR204 D
<21>
H_PROCHOT# VR_ON 1_0603_5%
1
PR205
PC201
PC202
PC204
PC205
PC206
0_0402_5%
+3VALW 1 2
2
1U_0603_6.3V6M
1
1
PR208 0_0402_5%
1
1U_0603_10V6K
0.01U_0402_16V7K
PC208
PC209
PC210
PR229
5
6
7
8
@ 0_0402_5%
2
PR207
1.91K_0402_1%
2
2
2
PQ200
<19,21> VGATE 4 NTMS4816NR2G_SO8
1
41
40
39
38
37
36
35
34
33
32
31
PR209 PU200
3
2
1
@ 0_0402_5%
3V3
DPRSTP#
VID6
VID5
VID4
VID3
GND PAD
PGOOD
CLK_EN
DPRSLPVR
VR_ON
PC211
1 PC200
0.22U_0603_10V7K
PL201
@0.1U_0402_16V7K 0.45UH_ETQP4LR45XFC_25A_-25+20%
2
1 FDE VID2 30 1 2 1 2 1 2 +VCC_CORE

2
PR210 @40.2K_0402_1%
<8,19,21> PM_PWROK 1 2 2 PMON 29 PR212
VID1
1
PR211 147K_0402_1% 0_0603_5%
1
1 2 3 RBIAS VID0 28
PR213
H_PROCHOT# 4 27 4.7_1206_5% PR214
<4> H_PROCHOT# VR_TT# VCCP
PH201 @100K_0603_1%_TH11-4H104FT PQ201 7.68K_0805_1%
PR215
2
1 2 1 2 5 26 LGATE_CPU1 4 NTMFS4946NT1G_SO8FL-5
NTC LGATE
2 VSUM
@4.22K_0402_1%
1 2 6 25
SOFT VSSP
1
C PC2120.015U_0603_25V7K C
7 24 PHASE_CPU1
3
2
1
OCSET PHASE
PR216 PC213
2
14.7K_0402_1% 8 23 UGATE_CPU1 680P_0603_50V8J
VW UGATE
1 2
9 22 BOOT_CPU1
COMP BOOT
DROOP
10 21
FB NC
VSUM
VDIFF
2
VSEN
VDD
RTN
DFB
VSS
2
VIN
VO
PR217
PC214 ISL6261ACRZ-T_QFN40_6X6
6.81K_0402_1%
1000P_0402_50V7K
11
12
13
14
15
16
17
18
19
20
1
1
PR218 464K_0402_1%
2 1 1 2
PC215 150P_0402_50V8J
PH3 under CPU botten side :
1 2 +5VALW CPU thermal protection at 89 degree C
1 2 PR219
1
10_0603_5% Recovery at 70 degree C
PC216 47P_0402_50V8J PC217
1U_0603_10V6K
2
PR221 PC218
VL VL
330_0402_1% 390P_0402_50V7K PR220
1 2 1 2 10_0603_5% VL
100K_0603_1%_TH11-4H104FT
1 2 +CPU_B+
0.01U_0402_25V7K
1
PR222
2
PC219
1
2.21K_0402_1%
PC64
B 0.22U_0603_25V7K PR28 B
1 2
2
PH1
100K_0402_1%
PC220 1000P_0603_50V7K
2
<5> VCCSENSE 1 2 1 2 PR29
MAINPWON <21>
1
<BOM Structure>
2
PR223 VSUM 100K_0402_1%
1
1
PC224 0.1U_0402_10V7K
PC225 0.1U_0402_10V7K
0_0402_5% TM-2 1 2
PR226 4.53K_0402_1%
PC221 PR224 PR30

1
1000P_0402_50V7K 3.57K_0402_1% 18K_0402_1%

2
8
1 2
1
PH D
1 2 3
P
2 2
+
2
PR225 1 TM-3 2 PQ4

<5> VSSSENSE O
0_0402_5% PC223 330P_0402_50V7K TM_REF1 2 G 2N7002KW_SOT323-3
2
G
1
1 2 PU7A S
PH200
1
3
PC222 LM393DG_SO8
10KB_0603_5%_ERTJ1VR103J
4
330P_0402_50V7K 1 2 1 2
2
1000P_0402_50V7K
11.8K_0402_1%
PR227 PR228 2008-07-17
1
0.22U_0402_6.3V6K
1K_0402_1% 11K_0402_1%
1
PR33
2 1 VL
PC18
PC19
+VCC_CORE PR34
8
100K_0402_1%
2
5
P
PR35 +
7
100K_0402_1% O
6
2
G
PU7B
2
PC226 LM393DG_SO8
4
0.22U_0603_10V7K
1
A A

CPU_CORE
Custom LS-5581P 2.0
5 4 3 2 1
A B C D
1 1
+3VALW +5VALW
1
PC701 PC702
10U_0805_6.3V6M 1U_0402_6.3V6K
2
2 2
PU701
6 VCNTL
5 VIN VOUT 3 +1.8VP
PR701 9 4
VIN VOUT
1
0_0402_5%
1
<21,22,25> SYSON 1 2 8 EN
7 2 PR702 PC705
GND
PR704 POK FB 4.64K_0402_1% PC704 10U_0805_6.3V6M
2
@ 0_0402_5% 0.01U_0402_25V7K
2
<21,22,26,27> SUSP# 1 2 APL5913-KAC-TRL_SO8
1
1
PC703
0.47U_0402_6.3V6K PR703
2
3.65K_0402_1%
2
PJP701
+1.8VP 1 2 +1.8V
PAD-OPEN 4x4m
3 3
4 4

1.8VP
A B C D
5 4 3 2 1
Version change list (P.I.R. List) Power section Page 1 of 1
Item Reason for change PG# Modify List Date Phase
1 change OTP 89 degree protect B change PR33=11.8k PR30=18k PR29=100k PR28=100K

70 degree recover
D D
2 Change 1.8vp sequence to SYSON

B Del PR704
3 Change 1.5vp Voltage set for hw request B change PR407 to 10.5K
4 change PR405 PR518 to 100

For slove RT8209 issue B PC406 PC520 to 4.7U
5 modify PQ600 PQ601 PN follow C38 bom C modify 2N7002 from Rohm to toshiba
8
9
C C
10
11
12
13
14
15
16
17
B B
18
19
20
A A
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10
GM VGA_CORE
Custom LS-5581P
5 4 3 2 1
www.s-manuals.com

Compal La-5581p R2.0 Schematics PDF

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A B C D E

Part Number = DA80000FB20

Cantiga_GS45/GS40 +ICH9-M SFF

ULV core logic board 3

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

( O MEANS ON X MEANS OFF )

@ : means just reserve , no build

SMBUS Control Table

Descrebtion Descrebtion Descrebtion

USB port 1 BT Module PCI-e port 1 WLAN Conn. SATA port 1

USB port 2 cardreader PCI-e port 2 SATA port 2 WWAN/SSD

USB port 3 USB connector PCI-e port 3

USB port 4 WLAN Conn. PCI-e port 4

USB port 5 WWAN/SSD PCI-e port 5 LAN

USB port 6 USB connector

USB port 7 CMOS

USB port 8 Fingerprint

I2C / SMBUS ADDRESSING

DEVICE HEX ADDRESS

07/06 Add U1 SA00003BZ10 for 3500@

F10 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8

Security Classification Compal Secret Data Compal Electronics, Inc.

Near pin D34

Close to CPU pin

Close to CPU pin AW43

BD20 VCC_213 VCCP_133 AE7

AF38 VCCP_017 VCCP_142 AR9

Size Document Number

Tuesday, July 21, 2009

U1D U1E +VCC_CORE Mid Frequence Decoupling

H_A#[3..35] <4> U3B

DDR CLK/ CONTROL/COMPENSATION

trace width and spacing is 10/20 D55 C76 R53

+VCCP DDR3_NB_REF NC_10 SDVO_CTRLDATA

H_VREF H_RCOMP H_SWNG NC_18

1 1 G1 C29 HDA_BITCLK_NB <21>

Security Classification Compal Secret Data Compal Electronics, Inc.

<14> DDR_A_D[0..63] <15> DDR_B_D[0..63]

DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5

BD6 BF32 BB4 BJ37

Security Classification Compal Secret Data Compal Electronics, Inc.

U3C Strap Pin Table

Close to pin D32 and keep PEG_TX_15

D_BLUE Remove R84 ~ R86 since

Security Classification Compal Secret Data Compal Electronics, Inc.

+1.05VM_DPLLA +VCCP +V1.05VM_AXF +VCCP

AT29 AB44 +VCC_PEG 1 1

+1.8V R102 2 1 0_0603_5% L45 P2

install 4.7U for wavy issue. 7/29

Security Classification Compal Secret Data Compal Electronics, Inc.

1 AL40 VCC_12 BB28 VCC_SM_22 VCC_AXG_NCTF_23 AL19

VCC GFX NCTF

AM25 AA37 AJ24

PAD T43 AG13

CANTIGA GMCH SFF_FCBGA1363

Security Classification Compal Secret Data Compal Electronics, Inc.

BA55 C43 U3J

CANTIGA GMCH SFF_FCBGA1363