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Mbist Summary

MBIST (Memory Built-In Self-Test) allows memory chips to test themselves for faults and potentially repair faulty bits. It uses algorithms like checkerboard and marching patterns to detect faults like stuck-at, transition delays, and coupling faults. MBIST integrates test pattern generation and response analysis circuits to thoroughly check memories. BIRA (Built-In Repair Analysis) circuitry identifies repairable faults and their repair signatures which are stored in eFuses to map out faulty bits and repair memories using redundant rows and columns.

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Roshan Raju
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284 views3 pages

Mbist Summary

MBIST (Memory Built-In Self-Test) allows memory chips to test themselves for faults and potentially repair faulty bits. It uses algorithms like checkerboard and marching patterns to detect faults like stuck-at, transition delays, and coupling faults. MBIST integrates test pattern generation and response analysis circuits to thoroughly check memories. BIRA (Built-In Repair Analysis) circuitry identifies repairable faults and their repair signatures which are stored in eFuses to map out faulty bits and repair memories using redundant rows and columns.

Uploaded by

Roshan Raju
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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# MBIST
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automated test strategy


reduce ATE (Automatic Test Equipment) time and cost
testing memory faults and its self-repair capabilities

4X increase in memory size every 3 years

Memory faults behave differently than classical Stuck-At faults


the fault models are different in memories (due to its array structure) than in the
standard logic design
apart from fault detection and localization, self-repair of faulty cells through
redundant cells is also implemented

Challenge:
it requires test logic to multiplex and route memory pins to external pins
requires very large external pattern sets for acceptable test coverage due to
the size and density of the cell array-and its associated faults

MBIST:
self-testing and repair mechanism
set of algorithms to detect possibly all the faults
stuck-at (SAF),
transition delay faults (TDF),
coupling (CF) or
neighborhood pattern sensitive faults (NPSF)
Address decoder faults

inbuilt clock, address and data generators


read/write controller logic

memory cell performance has to be analyzed in the context of the array


structure
two fundamental components: the ‘storage node’ and ‘select device’

row and address decoders determine the cell address that needs to be accessed
corresponding row and column get selected
which then get connected to sense amplifier
sense amplifier amplifies and sends out the data

write:
can access the required cell where the data needs to be written
Special circuitry is used to write values in the cell from the data bus
For the decoders, we test the soc verification functionality
whether they can access the desired cells based on the address in the
address bus
For the amplifier and the driver, check if they can pass the values to
and from the cells correctly

Testing:
implements a finite state machine (FSM)
to generate stimulus and
analyze the response coming out of memories
This extra self-testing circuitry
acts as the interface between high-level system and memory

MBIST Algorithms:
Checkerboard :
1s and 0s are written into alternate memory locations
checkerboard pattern is mainly used for activating failures resulting from
leakage,
shorts between cells,
and SAF
Steps:
Write checkerboard with up addressing order
Read checkerboard with up addressing order
Write inverse checkerboard with up addressing order
Read inverse checkerboard with up addressing order

March :
various types of March tests with different fault coverages
applies patterns that “march” up and down the memory address
while writing values to and reading values from known memory locations
retrive proper parameters from the memory model,
also determine the size and the word length of memory
targets faults like
Stuck-At,
Transition,
Address faults,
Inversion, and
Idempotent coupling faults
Steps:
increasing address:
write 0s with up addressing order (to initialize)
Read 0s, write 1s with up addressing order
Read 1s, write 0s with up addressing order
decreasing address:
Read 0s, write 1s with down addressing order
Read 1s, write 0s with down addressing order
Read 0s with down addressing order

BISR:
Memories occupy a large area
but have a smaller feature size
=> memories have a significant impact on yield
redundant or spare rows and columns to avoid yield loss
row repair and column repair
Memory repair:
1.analyze the failures diagnosed by the MBIST Controller
(during the test for repairable memories)
2.determine the repair signature to repair the memories
(All repairable memories have repair registers which hold the repair
signature)

BIRA:
to calculate the repair signature based on
memory failure data
and implemented memory redundancy scheme
also determines if memory is repairable in production testing environments

repair signature will be stored in the BIRA registers


repair signature is then passed on to the repair register’s scan chain
for subsequent Fusebox programming

reading and writing of a Fusebox is controlled through


TAP (Test Access Port) and
dedicated repair registers scan chains connecting memories to fuses

repair information is then


scanned out of the scan chains,
compressed,
and is burnt on-the-fly
into the eFuse array by applying high voltage pulses

On-chip reset,
the repair information from the eFuse is automatically loaded
and decompressed in the repair registers,
which are directly connected to the memories

results in all memories with redundancies being repaired

BIST is run on the repaired memories which verify the correctness of memories

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