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    Btech Cs 3 Sem Computer Organization and Architecture kcs302 2022

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    Harshit dubey
    This document contains a computer organization and architecture exam with 7 sections. Section 1 contains 10 short answer questions about computer components, microprogramming, control statements, combinational logic, bus arbitration, transfer rates, register operations, memory types, and instruction formats. Section 2 contains 3 long answer questions about bus systems, handshaking transfers, array multiplication, and cache memory. Sections 3-7 each contain 2 long answer questions about floating point representation, Booth's algorithm, bus organization, address mapping, I/O communication, asynchronous transfers, stack operations, and microprogrammed control.

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    Btech Cs 3 Sem Computer Organization and Architecture kcs302 2022

    Uploaded by

    Harshit dubey
    146 views2 pages
    This document contains a computer organization and architecture exam with 7 sections. Section 1 contains 10 short answer questions about computer components, microprogramming, control statements, combinational logic, bus arbitration, transfer rates, register operations, memory types, and instruction formats. Section 2 contains 3 long answer questions about bus systems, handshaking transfers, array multiplication, and cache memory. Sections 3-7 each contain 2 long answer questions about floating point representation, Booth's algorithm, bus organization, address mapping, I/O communication, asynchronous transfers, stack operations, and microprogrammed control.

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    btech-cs-3-sem-computer-organization-and-architecture-kcs302-2022

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    This document contains a computer organization and architecture exam with 7 sections. Section 1 contains 10 short answer questions about computer components, microprogramming, control statements, combinational logic, bus arbitration, transfer rates, register operations, memory types, and instruction formats. Section 2 contains 3 long answer questions about bus systems, handshaking transfers, array multiplication, and cache memory. Sections 3-7 each contain 2 long answer questions about floating point representation, Booth's algorithm, bus organization, address mapping, I/O communication, asynchronous transfers, stack operations, and microprogrammed control.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    146 views2 pages

    Btech Cs 3 Sem Computer Organization and Architecture kcs302 2022

    Uploaded by

    Harshit dubey
    This document contains a computer organization and architecture exam with 7 sections. Section 1 contains 10 short answer questions about computer components, microprogramming, control statements, combinational logic, bus arbitration, transfer rates, register operations, memory types, and instruction formats. Section 2 contains 3 long answer questions about bus systems, handshaking transfers, array multiplication, and cache memory. Sections 3-7 each contain 2 long answer questions about floating point representation, Booth's algorithm, bus organization, address mapping, I/O communication, asynchronous transfers, stack operations, and microprogrammed control.

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    of 2

    Printed Page: 1 of 2 

    Subject Code: KCS302


    0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

    BTECH
    (SEM III) THEORY EXAMINATION 2021-22
    COMPUTER ORGANIZATION AND ARCHITECTURE
     
    Time: 3 Hours Total Marks: 100
    Note: Attempt all Sections. If you require any missing data, then choose suitably.

    SECTION A
    1. Attempt all questions in brief. 2x10 = 20
    Qno Questions CO
    (a) List and briefly define the main structural components of a computer. CO1
    (b) Differentiate between horizontal and vertical microprogramming. CO3
    (c) Represent the following conditional control statements by two register CO1
    transfer statements with control functions.
    If(P=1) then (R1 R2) else if (Q=1) then (R1R3)
    (d) Design a 4-bit combinational incremental circuit using four full adder CO2
    circuits.
    (e) Differentiate between Daisy chaining and centralized parallel CO5
    arbitration.
    (f) What is the transfer rate of an eight-track magnetic tape whose speed is CO5
    120 inches per second and whose density is 1600 bits per inch?
    (g) Register A holds the binary values 10011101.What is the register value CO2
    after arithmetic shift right? Starting from the initial number 10011101,
    determine the register value after arithmetic shift left, and state whether
    there is an overflow.
    (h) What is an Associative memory? What are its advantages and CO4
    disadvantages?
    (i) Differentiate between static RAM and Dynamic RAM. CO4
    (j) What are the different types of instruction formats? CO3

    SECTION B
    2. Attempt any three of the following: 10x3 = 30
    Qno Questions CO
    (a) A digital computer has a common bus system for 8 registers of 16 bit CO1
    each. The bus is constructed using multiplexers.
    I. How many select input are there in each multiplexer?
    II. What is the size of multiplexers needed?
    III. How many multiplexers are there in the bus?
    (b) Explain destination-initiated transfer using handshaking method. CO5
    (c) Explain 2-bit by 2-bit Array multiplier. Draw the flowchart for divide CO2
    operation of two numbers in signed magnitude form.
    (d) A digital computer has a memory unit of 64K X 16 and a cache CO4
    memory of 1K words. The cache uses direct mapping with a block size
    of four words.
    I. How many bits are there in the tag, index, block, and word
    fields of the address format?
    II. How many bits are there in each word of cache, and how
    they are divided into functions? Include a valid bit.
    III. How many blocks can the cache accommodate?
    (e) Explain with neat diagram, the address selection for control memory. CO3
    Printed Page: 2 of 2 
    Subject Code: KCS302
    0Roll No: 0 0 0 0 0 0 0 0 0 0 0 0 0

    BTECH
    (SEM III) THEORY EXAMINATION 2021-22
    COMPUTER ORGANIZATION AND ARCHITECTURE
     
    SECTION C
    3. Attempt any one part of the following: 10x1 = 10
    Qno Questions CO
    (a) A binary floating-point number has seven bits for a biased exponent. CO2
    The constant used for the bias is 64.
    I. List the biased representation of all exponents from -64 to +63.
    II. Show that after addition of two biased exponents, it is necessary
    to subtract 64 in order to have a biased exponent’s sum.
    III. Show that after subtraction of two biased exponents, it is
    necessary to add 64 in order to have a biased exponent’s
    difference.
    (b) Show the multiplication process using Booth algorithm, when the CO2
    following binary numbers, (+13) x (-15) are multiplied.

    4. Attempt any one part of the following: 10x1 = 10


    Qno Questions CO
    (a) Draw a diagram of a Bus system in which it uses 3 state buffers and a CO1
    decoder instead of the multiplexers.
    (b) Explain in detail multiple bus organization with the help of a diagram. CO1

    5. Attempt any one part of the following: 10x1 = 10


    Qno Questions CO
    (a) The logical address space in a computer system consists of 128 CO4
    segments. Each segment can have up to 32 pages of 4K words each.
    Physical memory consists of 4K blocks of 4K words each. Formulate
    the logical and physical address formats.
    (b) How is the Virtual address mapped into physical address? What are the CO4
    different methods of writing into cache?

    6. Attempt any one part of the following: 10x1 = 10


    Qno Questions CO
    (a) Explain how the computer buses can be used to communicate with CO5
    memory and I/O. Also draw the block diagram for CPU-IOP
    communication.
    (b) What are the different methods of asynchronous data transfer? Explain CO5
    in detail.

    7. Attempt any one part of the following: 10x1 = 10


    Qno Questions CO
    (a) Write a program to evaluate arithmetic expression using stack CO3
    organized computer with 0-address instructions.
    X = (A-B) * (((C - D * E) / F) / G)
    (b) List the differences between hardwired and micro programmed control CO3
    in tabular format. Write the sequence of control steps for the following
    instruction for single bus architecture.
    R1  R2 * (R3)

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