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60 views10 pagesChapter 7. Subsystem Design PDF
Uploaded by
Naimur EshanCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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/ 10
Subsystem Design Processes
(One ofthe pleasontest hing inthe world is going on 2 journey
= Sie Jone Hatnncron
The longest ouney stars wih a single step,
= Mao Zeoene
OBJECTIVES
This chapter andthe following two cary though the design ofa. digital system wsing & 109-
down approach. The complete rysem environment is that ofa 4t microprocessor which
is readily envisaged as an interconnection of four major architectural blocks ALU, Contol
‘Unit, VO Unit and Memory:
‘The design developed in this text that of the ALU or dat path, which itself divides
readily into four subsystems. This chapter concentrates ou attention onthe design of one of
the ALU subsystems the Shifter
The whole design proces clearly illstrates the step-by-step nature of structured design
and the inherently regular nature of properly conceived subsysiem architecture. A general
design process is developed and set out ia this chapter
7.1 SOME GENERAL CONSIDERATIONS
‘The frst question to ask about any design methodology isthe time-honored “Whats in it for
ime? Is it going to be worwile investing the time to learn. To answer the second part
fis, remarkably litle tie is needed to learn the rudiments of VLSI design, This is largely
thanks tothe Mead and Conway methodology which orginally brought VLSI design within
the scope of the ordinary electronics engineer. Infact, the average undergraduate student of
electrical or eletronic engineering can acquire a basic level of competence in VLSI design
for an investment of aboot 40 hours of lectures spread over one or mare academic Lenn Or
semesters. Sinlaly,« 10-day fulltime continuing education course can quite readily bing
Practicing professional enginets or computer scientists up to a simile standard. A base
level of competence is taken asthe ability to apply the design methodology and make use
‘of design tools and procedures othe point where a chip design of several husdred tansistors
(or higher fr regular structures) can be tacked
“The first part ofthe quesion—"Whats init for me?”—may be quite simply answered
as: Providing better ways of tackling some problems, providing @ way of designing and
‘realizing systems that are too lrg, to complex, or just nt sited to ofFhe-shel components
and providing an appreciation and understanding of IC technology
"ener" may include
1. Lower unt cost compared with other approaches tothe same requirement. Quantity
plays a part here but even small quantities, if realized through cooperative ventures
Such asthe mutproject chip (MPC) or multiproduct wafer (MPW), canbe fabricated
fora lite as $200 (MPC) or $800 (MPW) per square millimee of silicon, including
the bonding and packaging of five or six chips per customer.
2, Higher reliability High levels of system integration usvally greatly reduce
interconnections—a weak spot in any system.
3. Lower power disipaian, lower weigh, and ower volume compared with most eter
approaches to a gen sytem
4. Beier performance—pariculary in tems of speed power product.
5. Enhanced repetabiiy. Thete ate fewer processes 1 contol ifthe whole sytem or
ery linge part of it is realized on a single chip.
6. The posiiliy of reuced designidevelopment periods (particularly fr more complex
systems) if suitable desig procedures and design aids are avaiable
7.1.1 Some Problems ‘very large pat of i realized on a single chip
6. The post ofrtuced desgn/development periods (paula fr more complex
systems) if suitable design procedures and desig aids are avaiable
7.1.1 Some Problems
Some ofthe problems associated with VLSI design at:
1. How to design large complex systems in a reasonable time and with reasonable
cffort. This is problem shared with other approaches to sytem design
2, Thernatueof architectures best suited to take fl advantage of VLSI and the technolo.
53, The testability of largelcomplex systems once implemented in silicon,
Problems 1 and 3 are greatly reduced if two aspect of standard practice ae scepted:
“Approach the desig i a top-down manner snd with adequate computer aided tools
todo the jb. Panton the system sesily, aiming for sinple interconnection between
subsystems and high regularity within subsystems. Generate and then verify each
section of the design
‘+ Design testability into the system from ie outset and be prepared to devote a significant
proportion (eg. up t9 30%) of the total chip area to test and diagnose facilities
These problems are the subject of considerable resetrch and development setivity at
his time
eg
In taeking the design of a sytem, we must bear in mind tha topological properties are
generally far more significa than the logis operations being performed It may be sai that
‘tis better to duplicate (or tpliate, ete.) rather than communicate, This i indeed the case,
tnd it an approach which seems wrong 1o more traditional designers. In fet, even
relatively stightorvard designs, x much as 40-S0% of the chip may be taken up
fmterconpectons, and i 6 wue to say that interconnections generally pose the most ecute
problems inthe design of large sytem. Communications mist therefore be given the highest
Ponty carly inthe design process and a communication sraegy should be evolved and
here to throughout that process.
‘Accordingly, the architecture shouldbe carefully chosen to allow the design objectives
to be realized ond tallow high regularity in realization.
7.2. AN ILLUSTRATION OF DESIGN PROCESSES
Structured desig begins with the concept of hierarchy
Wis possible o divide any comple function into less complex subfunctons. These
may be subdivided furher into even simpler subfunctions and s0 on—the botom
level being commonly refered to a5 “eal
+ Tis proces is known as top-down design
+ As a'system's complexity increases, it organization changes as different factors
become relevant toils eration.
+ Coupling canbe used as measure of how much submodules interact. Clever systems
Partioning aims at reducing implicit complexity by minimizing the amount of
fateraction between subparts; thus independence of design becomes a realiy.
+ Its eral hat components interacting with high frequency be hysialy proximate,
since one may pay severe penalties for long, highbandwidth interconnet
+ Concurrency shouldbe exploited is desirable that ll gates onthe ehip do usefo
work most ofthe time,
+ Because technology changes s0 fst, the adaptation toa new process must occur in
8 short time, Thus technology-independentdeserition becomes important.
In representing a desig, several approaches: may be used at different stages of the
design proces; for example
+ conventional cireuit symbols;
* opie symbols,
stick diagrams;
any mixture of logic symbols and sick diagrams tht is convenient at particular
stage
+ mack layouts;
+ architectral block diagrams;
* floor plans.
‘We will sustate various representations during the course of the following design
ceveriset illustrate design proeses,
OoOTCTwVTl- re Fema
7.2.1. The General'Arrangement of a 4-bit Arithmetic Processor (sito asin Facsies =
7.2.1 The General Arrangement of a 4-bit Arithmetic Processor
‘The 4:it microprocessor has been chosen as a design example because itis particularly
suitable for iustrting the design and interconnection ef commen architectural Blocks
Figure 71 sets out te basic architecture of mest if not all, microprocessors. At this
stage we will consider the design ofthe datapath only, but matters relevant to other blocks
‘vill follow in ater chapters
BE] | come | |
FIGURE 7.1. Basic digital processor structure
The datapath hasbeen separated ou in Figure 7.2 and it will be seen that the structure
comprises anit which pocestes data plied tone port and present soup aa second
port Altematvely, the two data port may be combined as a single Bidirectional poet if
"orage facilities exist in the datapath. Conzl over the fonctions to be perarmed is effected
by contol signals as indicated
FIGURE 7.2. Communieatons strategy for data path
[At this early stage i is essential to evolve an interconnections strategy (as shown) to
‘which we vil then ars
[Now we will decompose the datapath nto a bloc diagram showing the main subunits
In doing tis it i useful to anticipate possible floor plan to show the planned relative
Aisposiion of the subunits onthe chip an thus on the mask layouts. A Block diagram is
presented in Figure 73.
_
wogatet Tae) itty fm] RE Lo dine
i
FIGURE 7.3. Subunits and basle Interconnections for data path
‘A further decision must then be made about the nature of the bus architecture linking
the subunits The choices in this ease range from one-bus,two-bus or thee-busareitectre
Some ofthe posites are shown in Figure 7.8
In pursuing this particular design exercise, it was decided to implement the strocure
with a two-bus architecture. In our planning we can now extend on our iferonnections
Strategy by planning for power ris and nationally making some basic allocation of layers
fn which the varius signal paths will be predominantly run. These additonal features ae FIGURE 7.2 Communications strategy for datapath
A his erty stage it essen
which we will then adhere
"Now we will decompose the datapath at a block diagram showing the main subunits
In doing this it i useful to anticipate a possible loor plan to show the planed relative
disposition of the subunits on the chip and thus on the mask layouts. A Block diagram is
presented in Figure 73.
tO __— tt
1 0 evolve an interconnections strategy (8 shown) to
veges feo) te Fe] Lo nike
ole cde te
FIGURE 7.2. Subunits and basic Interconnections for date path,
{A further decision must then be made abou the nature of the bus architecture inking
the subunits. The choices in thi ease range from one: bus, two bus or three-busarchiectre
Some ofthe possibilities are shown in Figure 7.4
In pursuing this particular design exercise, it was decided to implement the sirvture
with a two-bus architecture, In our planning we ean now extend on our interconnections
steategy by planning for power rails and ntinally making some basic allocation of layers
fn which the varius signal paths wll be predominantly run. These additional features are
illrtated in Figre 7.5, together with «tentative floorplan ofthe proposed desien which
includes some form of interface (VO) to the parent system data bus (see Figure 7-1)
‘The proposed processor willbe sen to omprie a register array in whch 4bit numbers
an be stored either from an inptoutpat porto fem the output ofthe ALU via shits
Numbers ffom the register aray canbe fd in pats to the ALU tobe added (or subtracted,
ce) and the result can be shied or not, before being feared to the register array of
possibly out tough the LO por. Obvieusy, data connections between the UO port, ALU.
nd shifter must be inthe form of 4-bit bose, Simultaneously, we must recognize that cach
ofthe blocks must be autably connected to contr lines 30 that function maybe defined
for any ofa range of posible epertions.
The required arrangement hat been tamed into @ very tentative flor plan, 26 sa
Figure 75, which indiates a possible relative disposition ofthe blocks and als sdicates an
sceepable and sensible interconnection satey indicated bythe lines showing the prefered
‘ietion of dataflow and contol signal datrbution, At this stge of leaning, Moor plans
wll every tentative since we will no as ye beable o accurately aes he area tequtemets,
Sy for afi register of it adder
Overall interconnection strategy having een determined, stick diagrams forthe etcults
comprising sections of the various blocks may be developed, conforming to the required
"rategy. An interactive process of modifiation may well then ake place between he various
stages asthe design progresses, During the design process, and in particular when defining
urs en ai Pa
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FIGURE 7.4 Basic bus architectures.
Tianaawe een
t oan
FIGURE 7.5 Tentative Moor plan for 4 datapath
te interconnection strategy and designing the stick diagrams, care must be taken in allocating
te Layers tothe various data or control paths. We must remember that
1, Metal can cross polysilicon or diffsion without any significant effect (with some
reservations to be discussed late)
2. Wherever polysilicon ersses diffusion a wansstr willbe formed. This includes the
second polysilicon layer for processes that have 0
3, Wherever lines touch on the same lvel an interconnection is formed.
Simple contacts can be used to join difsion or polysilicon to metal.
5. To join diffusion and polysilicon we must use either a buried contactor «butting
coniat (in which ease all thee layers are joined togetber atthe contact) or O40
ontets,difusion to metal then meal to polysilicon,
6. In some processes, a second metal layer is avalable. This ean cross over any other
layers and is conveniently employed for power ral
Fest and second meal layers may be joined using a ve
eh layer has particlar electrical properties which mast be taken into count
For CMOS layouts, p- and a-iffsion wives must not diet join each other, ot
may they cross either a powell or an novell boundary.
With these factors in mind, we may now adopt suitable tactics to meet the strategic
requirements when we approach the design of each subunit in tum,
7.2.2 The Design of a 4-bit Shifter
Any general purpose mit shir shouldbe ale to shift incoming data by upto ®— 1 places Qe ae —,
the imerconnetion strategy and designing the stick diagrams, care must be taken in allocating
the layers to the various data oe control paths. We must rember that:
1. Meal can cross polysilicon or effsion without any significant effect (with come
reservations to be dieussed Ine)
2, Wherever polysilicon crosses difsion a transistor willbe formed, This incldes the
second polyilicon layer for processes that have 6.
3, Wherever lines touch on the same level an interconnection is formed
4 Simple contacts can he used 10 join difusion of polysilicon to meta
5. To join diffusion and polysilicon we must use either a buried contactor a buting
contact (in which case all three layers are joined together atthe contact) oF two
contacts, difision to metal ten metal to polysilicon.
6, In some proceste, 2 second metal layer x avaiable. This ean eross over any other
layers and is conveniently employed for power rails
7, First and second metal layers may be joined using a via.
ach layer has particular cleeical properties which must be taken into account
9. For CMOS layouts, p- and s-difusion wires must not dzely join each other, nor
‘may they cross either a powell or an n-vell Boundary.
‘With these factors in mind, we may now adopt suitable tactics to meet the strategic
requirement when we approach the design of each tubunit in um,
7.2.2 The Design of a 4-bit Shifter
‘Any general purpose #-hit shir shouldbe able to shift incoming data by wp to = 1 places
fina mphtsbift or left-shiRt direction. If we now farther specify that all sis should be on
tan 'endaround” basis, so tha any bit shifted out at one end of data word wil be shied
fin a the other end ofthe wor, then the problem of right shit olf shi is greally eased
Infact, a moments consideration will reveal, fora 4-bit word, that a Lit sift iht is
cquivalent oa 3-bit shift ef and a 2-bit shi right is equivalemt wo a2-bit shift ef, ete. Thus
‘ve ean achieve capability to shift let or tight by ze, one, wo, or thee places by
‘designing a cieut which wil shift right only (ay) by 2eo, one, two, or tree places
The nature of the shifer having been decided on, its implementation must then be
considered. Obviously, the fist circuit which comes 10 mind is that ofthe si ester in
Figures 638, 6.39 and 6.40, Data could be loaded from the output ofthe ALU and shifting
effected; then the curputs ofeach stage of the shift register would provide the required
parallel outpt tbe returned tothe register amay (or elsewhere inthe general eae)
However there is danger in accepting the obvious without question. Many designers,
‘ned tothe constraints of TTL, MSI, and SSI ogi, would be conditioned to think in tems
of such standard arrangements, When designing VLSI systems, it pas to set out exactly what
{is rquired to assess the best approach, In this eas, the shifter must have
* input from a foursine parallel data bus:
* four ouput lines forthe shied dats;
{+ means of transfering inpot dat output lines with any shift rom zero to three bits
inclusive.
Soe Daign Pacers 7
In looking fora way of meting these requirements, we should also atempt to take best
sdvamage of the technology; for example, the availabilty of the swith-like MOS pass
transistor and transmission gate
‘We must also observ the suategy decided on earlier for the direction of data and
contol signal low, ad the approach adopted should make this feasible. Remember thatthe
‘overall sategy inthis cae i fr data to flow horizontally and cont signal vertically
‘A olution which mecte these requirements emerges fom the days of switch and relay
conuct based switching networks—the crossbor switch. Consider @ direct MOS switch
implementation of a 4% 4 crossbar switch, asin Figure 7.6
te tt tte ”
ae
aL I. T ‘Sayles Dai Peer
In looking for a way of meeting these requirements, we should also atempt to take best
advantage of the technology: for example, the availabilty ofthe switehike MOS pass
‘wansistor and transmission git
‘We must also cbserve the strategy decided on earlier forthe direction of data and
‘contol signal fos, andthe approach adopted should make this feasible, Remember tha the
‘overall strategy in this ense is for data (flow horizontally and conte signal vertically
‘A solution which mets thee requirements emerges from the days of switch and relay
contact based switching networks—the crossbar switch. Cousder a dicet MOS switch
Implementation of « 4% 4 crosbar switch asin Figure 7.6.
“
‘The arrangement i quite general and may be realy expanded to accommodate n-bit
inputsoutputs. Infact, this arrangement isan overal in thot any input ine canbe eomneted
to any of all output lines i all switches are closed, then all input are connected to all
‘outputs in one glorious shor cnc. Furthermore, 16 contol signals (eM sw3) one fr
‘ach transistor switch, must be provided to drive the crossbar switch, and such complenty
is highly undesirable” An adaptation ofthis arangement recognizes the fact that We ca
couple the switch gates together in groups of four (i this case) and also form four separate
‘roups corresponding to shifts of zero, one, two and thre bits. The arrangement is realy
‘apted so that the in-lines also run horizontally (lo conform to the requted strategy).
The resulting arengement is known as a barrel shifter and a 4 bit barel shiRer
