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May 1997

ML4810*, ML4811**
High Frequency Power Supply Controller
GENERAL DESCRIPTION FEATURES
The ML4810 and ML4811 High Frequency PWM ■ Integrating Soft Start Reset
Controllers are optimized for use in Switch Mode Power ■ High current (2A peak) dual totem pole outputs
Supply designs running at frequencies to 1MHz. The
ML4810/11 contain a unique overload protection circuit ■ Practical operation to 1MHz (fOSC)
which helps to limit stress on the output devices and ■ 5.1V ±2% trimmed bandgap reference
reliably performs a soft-start reset. These controllers are ■ Under voltage lockout with 7V hysteresis
designed to work in either voltage or current mode and
provide for input voltage feed forward. ■ Soft Start Reset Delay (ML4811)
■ Oscillator synchronization function (ML4811)
A 1.1V threshold current limit comparator provides a ■ Soft Start latch ensures full soft start cycle
cycle-by-cycle current limit. An integrating circuit
“counts” the number of times the 1.1V limit was reached. ■ Outputs pull low for undervoltage lockout
A soft-start cycle is initiated if the cycle-by-cycle current ■ Accurately controlled oscillator ramp discharge current
limit is repeatedly activated. A reset delay function is
■ All timing currents “slaved” to RT for precise control
provided on the ML4811.

These controllers are similar to the UC1825 controller, * This part is End of Life as of August 1, 2000
however these controllers include many features not ** This part is Obsolete
found on the 1825. These features are set in Italics.

BLOCK DIAGRAM (Pin numbers shown are for ML4811)


RT
6
CT OSC CLOCK
7 5
SYNC +
10 2.2V
O.V.P./SHUTDOWN –
11
1.25V R
RAMP COMP
8 + I(1)
S Q
E/A OUT –
3
ERROR V+ PWR VC
NI AMP 16
2 +
OUT A
INV – I(1) 14
1 C Q
POWER GND
SOFT START TF.F.
9
P Q POWER VC
OUT B
17

POWER GND
1.1V – 15

+ V+ + 4V

ILIM/SD +
12
ENABLE
– VREF
1.5V 1.5V VREF
19
VREF GEN
2.45V – S Q
+ 9V
S
3× I(1) R INTERNAL
VCC
RC (RESET) – BIAS 18
4 Q 5.1V +
R UNDER
1.1V + + 1.1V GND
CLOCK VOLTAGE 13
RESET DELAY – – LOCKOUT
20 3V
I(1) = 16 x R
T

1
ML4810, ML4811
PIN CONFIGURATION

ML4811
20-Pin DIP (P20)
ML4810 20-Pin SOIC (S20)
16-Pin DIP (P16)
16-Pin SOIC (S16W) INV 1 20 RESET DELAY

INV 1 16 5.1V REF NI 2 19 5.1V REF


NI 2 15 VCC
E/A OUT 3 18 VCC
E/A OUT 3 14 OUTB
RCRESET 4 13 POWER VC RCRESET 4 17 OUTB
RT 5 12 PWR GND
CLOCK 5 16 POWER VC
CT 6 11 OUTA
RAMP 7 10 GND RT 6 15 PWR GND
SOFT START 8 9 ILIM/S.D.
CT 7 14 OUTA
TOP VIEW
RAMP 8 13 GND

SOFT START 9 12 ILIM/S.D.

SYNC 10 11 OVP
TOP VIEW

PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION

1 INV Inverting input to error amp. 11 OVP Exceeding 2.5V terminates the PWM
cycle and inhibits the outputs.
2 NI Non-inverting input to error amp.
12 ILIM/S.D. Current limit sense pin. Normally
3 E/A OUT Output of error amplifier and input to connected to current sense resistor.
main comparator.
13 GND Analog signal ground.
4 RCRESET Timing elements for Integrating Soft
Start reset. 14 OUTA High current totem pole output. This
output is the first one energized after
5 CLOCK Oscillator output. power on reset.

6 RT Timing resistor for oscillator — sets 15 PWR GND Return for the high current totem
charging current for oscillator timing pole outputs.
capacitor (pin 6).
16 VC Positive supply for the high current
7 CT Timing capacitor for oscillator. totem pole outputs.

8 RAMP Non-inverting input to main 17 OUTB High current totem pole output.
comparator. Connected to CT for
voltage mode operation or to current 18 VCC Positive supply for the IC.
sense resistor for current mode.
19 5.1V REF Buffered output for the 5.1V voltage
9 SOFT START Normally connected to Soft Start reference.
capacitor.
20 RESET DELAY Timing capacitor to determine the
10 SYNC A high going pulse terminates the amount of delay between fault.
PWM cycle and discharges CT.

2
ML4810, ML4811
ABSOLUTE MAXIMUM RATINGS Clock Output Current (Pins 5) ................................. –5mA
Error Amplifier Output Current (Pin 3) ...................... 5mA
Absolute maximum ratings are those values beyond which Junction Temperature ............................................. 150°C
the device could be permanently damaged. Absolute Storage Temperature Range ..................... –65°C to 150°C
maximum ratings are stress ratings only and functional Lead Temperature (Soldering 10 sec.) ..................... 260°C
device operation is not implied. Thermal Resistance (θJA)
Plastic DIP ....................................................... 65°C/W
Supply Voltage (Pins 18, 16) ...................................... 25V Plastic SOIC .................................................... 65°C/W
Output Current, Source or Sink (Pins 14, 17)
DC ....................................................................... 0.5A
Pulse (0.5µs) ......................................................... 2.0A OPERATING CONDITIONS
Analog Inputs
(Pins INV, NI, SOFT START) ....................... –0.3V to 7V Temperature Range
(Pins 9, 10, 11, 12, 20) .............................. –0.3V to 6V ML4810, ML4811 ...................................... 0°C to 70°C

ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 15V, RT = 3.65kΩ, CT = 1000pF, TA = Operating Temperature Range. (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
OSCILLATOR
Initial Accuracy TJ = 25°C 360 400 440 kHz
Voltage Stability 10V < VCC < 25V 0.2 4 %
Temperature Stability 5 %
Total Variation line, temperature 340 460 kHz
Clock Out High 3.9 4.5 V
Clock Out Low 2.3 2.9 V
Ramp Peak 2.8 V
Ramp Valley 1.0 V
Ramp Valley to Peak 1.6 2.3 V
Sync Input Threshold 0.8 1.0 1.4 V
Sync Input Current SYNC = 4V µA
REFERENCE
Output Voltage TJ = 25°C, IO = 1mA 5.00 5.10 5.20 V
Line Regulation 10V < VCC < 25V 2 20 mV
Load Regulation 1mA < IO < 10mA 5 20 mV
Temperature Stability 0°C < TJ < 150°C 0.2 0.4 %
Total Variation line, load, temperature 4.95 5.25 V
Output Noise Voltage 10Hz to 10kHz 50 µV
Long Term Stability TJ = 125°C, 1000 hrs 5 25 mV
Short Circuit Current VREF = 0V –15 –50 –100 mA
UNDERVOLTAGE LOCKOUT
Start Threshold 15 16 17 V
UVLO Hysteresis 6.5 7 7.5 V
ERROR AMPLIFIER
Input Offset Voltage ±20 mV
Input Bias Current 0.6 3 µA
Input Offset Current 0.1 1 µA
Open Loop Gain 1 < VO < 4V 60 96 dB

3
ML4810, ML4811
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER (Continued)
CMRR 1.5 < VCM < 5.5V 65 95 dB
PSRR 10 < VCC < 30V 75 90 dB
Output Sink Current VPIN 3 = 1V 1 2.5 mA
Output Source Current VPIN 3 = 4V –0.5 –1.3 mA
Output High Voltage IPIN 3 = –0.5mA 4.0 4.7 5.0 V
Output Low Voltage IPIN 3 = 1mA 0 0.5 1.0 V
Unity Gain Bandwidth 3 5.5 MHz
Slew Rate 6 12 V/µs
PWM COMPARATOR
Pin 8 Bias Current VPIN 8 = 0V –1 –5 µA
Duty Cycle Range 0 75 %
Pin 3 Zero DC Threshold 1.1 1.25 V
Delay to Output 50 80 ns
SOFT-START
Charge Current (Pin 9) ML4811 VPIN 9 = 1V, VPIN 4, 12 = 0 –35 –55 –75 µA
Discharge Current (Pin 9) VPIN 9 = 3V, VPIN 4 > 2.5 1 5 mA
VPIN 9 = 3V, VPIN 12 > 1.65, VPIN 4 < 2 1 5 mA
Charge Current (Pin 20) VPIN 20 = 1V 1 5 mA
Discharge Current (Pin 20) Requires external discharge resistor 0 µA
CURRENT LIMIT/SHUTDOWN
Pin 12 Bias Current 0V < VPIN 12 < 4V +15 µA
Current Limit Threshold ML4810 1.2 1.3 1.4 V
ML4811 0.95 1.1 1.3 V
Reset Threshold (Pin 12) ML4810 VPIN 4 < 2V 1.60 1.75 1.90 V
ML4811 VPIN 4 < 2V 1.4 1.50 1.8 V
Delay to Output 40 70 ns
Pin 4 Charging Current VPIN 12 = 2V 120 150 180 µA
Restart Threshold (Pin 4) 2 2.45 3 V
OVP Shutdown Threshold (Pin 11) 2.4 2.7 2.8 V
OVP Input Current VPIN 11 = 3V 40 50 60 µA
Charge Current (Pin 8) ML4810 VPIN 8 = 1V, VPIN 4, 9 = 0 –40 –50 –60 µA
OUTPUT
Output Low Level IOUT = 20mA 0.25 0.4 V
IOUT = 200mA 1.2 2.2 V
Output High Level IOUT = –20mA 13.0 13.5 V
IOUT = –200mA 12.0 13.0 V
Collector Leakage VC = 30V 100 500 µA
Rise/Fall Time CL = 1000pF 30 60 ns
SUPPLY
Start Up Current ML4810 VCC = 8V 2.0 3.5 mA
ML4811 VCC = 8V 2.5 4.0 mA
ICC ML4810 VPIN 1, 7, 9 = 0V, VPIN 2 = 1V, TA = 25°C 32 46 mA
ML4811 VPIN 1, 7, 9 = 0V, VPIN 2 = 1V, TA = 25°C 38 55 mA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

4
ML4810, ML4811
FUNCTIONAL DESCRIPTION A method of circumventing this problem involves
“counting” the number of times the controller terminates
the PWM cycle due to the cycle by cycle current limit.
SOFT START AND CURRENT LIMIT
The ML4810/11 offers a unique system of fault detection When the switch current crosses the 1.1V threshold A1
and reset. Most PWM controllers use a two threshold signals the F1 to terminate the cycle and sets F3, which is
method which relies on the buildup of current in the reset at the beginning of the PWM cycle. The output of F3
output inductor during a fault. This buildup occurs turns on a current source to charge C2. When, after
because: several cycles, C2 has charged to 2.45V, A5 turns on F2 to
discharge soft start capacitor C1. Charge is short lived (for
1. Inductor di/dt is a small number when the switch is off instance a disk drive start-up or a board being plugged
under load fault (short circuit) conditions, since VL is into a live rack) the control can “ride out” the surge with
small. the switch protected by the cycle by cycle limit. R1 and
C1 can be selected to track diode heating, or to ride out
2. Some energy is delivered to the inductor since the IC various system surge requirements as required.
must first detect the over-current because there is a
finite delay before the output switch can turn off. If the high current demand is caused by a short circuit, the
duty cycle will be short and the output diodes will carry
the current for the majority of PWM cycle. C2 charges
TPD TPD TPD fastest for low duty cycles (since F3 will be on for a longer
VTH2
VTH1 time) providing for quicker shutdown during short-circuit
when the output diodes are being maximally stressed.
SWITCH CURRENT
DIODE CURRENT
V+ ERROR
RESET DELAY
Figure 1. Current Waveforms for Slow Turn-Off System 20 QI
AMP
+
FROM OSC.

with Load Fault A3


I(1) I(1)
This scheme was adequate for controllers with longer
comparator propagation delays and turn-off delays than is
R Q G2
desirable in a high frequency system. For systems with
SOFT START
low propagation delays, very little energy will be Q2 F1
9 S
delivered to the inductor and the current “ratcheting” –
described above will not occur. This results in the C1 FROM PWM
– A4
COMPARATOR
controller never detecting the load fault and continuing to 1.1V +
pump full current to the load indefinitely, causing heating R
2.45V – F2
in the output rectifiers and inductor. RCRESET A5
QI
Q G1
4 +

TPD TPD TPD S


VTH2
VTH1 C2
I(2) 4UL0

Q R FROM OSC.
SWITCH CURRENT R1
F3
DIODE CURRENT – S
1.5V
A2
+
Figure 2. Current Waveforms for High Speed System
ILIM/SD
with Load Fault 12 +
A1
1.1V –

Figure 3. Integrating Soft Start Reset

5
ML4810, ML4811
OSCILLATOR
The ML4811 oscillator charges the external capacitor (CT) The oscillator period can be described by the following
with a current (ISET) equal to 3/RT. When the capacitor relationship:
voltage reaches the upper threshold (Ramp Peak), the
comparator changes state and the capacitor discharges to tOSC = tRAMP + tDEADTIME
the lower threshold (Ramp Valley) through Q1. While the
capacitor is discharging, Q2 provides a high pulse. A where:
discharge of the oscillator con be initiated by applying a C (Ramp Valley to Peak)
high level to the Sync pin. A short pulse of a frequency tRAMP =
ISET
higher than the oscillator’s free running frequency can be
used to synchronize the ML4811 to an external clock. The and:
pulse can be equal to the desired deadtime (TD) or the C (Ramp Valley to Peak)
tDEADTIME =
deadtime can be determined by IDIS and CT, whichever is IQ1
greater.

I(1) SYNC 10

ISET 3V 5V

6
ISET
RT Q2

V(1) CLOCK
7 + OUT
CT IDIS 5

Figure 4. Switching Current and Pin 4 Voltage — Normal Q1

I(1)

CLOCK

tD

RAMP PEAK
V(1) CT

RAMP VALLEY

Figure 5. Switching Current and Pin 4 Voltage — Load Fault Figure 6. Simplified Oscilator Block Diagram and Timing

100k 160

100nF

47nF 1.0nF
140
22nF
TD (ns)

0nF
RT (Ω)

10k 120
4.7nF

2.2nF
100
1nF
470pF 470pF
1k 80
100 1k 10k 100k 1M 10k 100k 1M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 7. Oscillator Timing Resistance vs Frequency Figure 8. Oscillator Deadtime vs Frequency

6
ML4810, ML4811
ERROR AMPLIFIER OUTPUT DRIVER STAGE
The ML4811 error amplifier is a 5.5MHz bandwidth The ML4811 Output Driver is a 2A peak output high
12V/µsec slew rate op-amp with provision for limiting the speed totem pole circuit designed to quickly switch the
positive output voltage swing (Output Inhibit line) for ease gates of capacitive loads, such as power MOSFET
in implementing the soft start function. transistors.

4.70

4
2.20
VIN

1.00
TD (µs)

(V)
0.47
VOUT

0.22
2

0.10

0.047 1
0.47 1.0 2.2 4.7 10.0 22 47 100 0 0.2 0.4 0.6 0.8 1.0
CT (nF) TIME (µs)

Figure 9. Oscillator Deadtime vs CT (3kΩ ≤ RT ≤ 100kΩ) Figure 10. Unity Gain Slew Rate

100
VCC

80 POWER VC
13

60
AV

40 Q2
AV (dB)

OUT A
11
20
OUT B
14
0 0
0 0
–20 –90
Q1
POWER
–180 GND
12
100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)

Figure 11. Open Loop Frequency Response


Figure 12. Simplified Schematic

7
ML4810, ML4811
3 0.2
IL (A)

2
SOURCE 15 –0.2

VOUT (V)
VSAT (V)

10
1

SINK 5

0 0
0 0.5 1.0 1.5 0 40 80 120 160 200
IOUT (A) TIME (ns)

Figure 13. Saturation Curves Figure 14. Rise/Fall Time (CL = 1000pF)

2 40
IL (A)
35
0
30
ICC — SUPPLY CURRENT

15 –2 25
VOUT (V)

20
10
15

10
5

0 0
0 100 200 300 400 500 –60 –40 –20 0 20 40 60 80 100 120 140
TIME (ns) TEMPERATURE (°C)

Figure 15. Rise/Fall Time (CL = 10,000pF) Figure16. Supply Current vs. Temperature

8
ML4810, ML4811

9
ML4810, ML4811
PHYSICAL DIMENSIONS inches (millimeters)

Package: P16
16-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)

16

0.240 - 0.260 0.295 - 0.325


PIN 1 ID
(6.09 - 6.61) (7.49 - 8.26)

1
0.02 MIN
(0.50 MIN) 0.055 - 0.065 0.100 BSC
(4 PLACES) (1.40 - 1.65) (2.54 BSC)

0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)

0.016 - 0.022 SEATING PLANE 0.008 - 0.012


0.125 MIN (0.40 - 0.56) 0º - 15º (0.20 - 0.31)
(3.18 MIN)

Package: S16W
16-Pin Wide SOIC
0.400 - 0.414
(10.16 - 10.52)
16

0.291 - 0.301 0.398 - 0.412


(7.39 - 7.65) (10.11 - 10.47)

PIN 1 ID

1
0.024 - 0.034 0.050 BSC
(0.61 - 0.86) (1.27 BSC)
(4 PLACES) 0.095 - 0.107
(2.41 - 2.72)

0º - 8º

0.012 - 0.020 0.022 - 0.042


0.090 - 0.094 0.005 - 0.013 0.009 - 0.013
(0.30 - 0.51) SEATING PLANE (0.56 - 1.07)
(2.28 - 2.39) (0.13 - 0.33) (0.22 - 0.33)

10
ML4810, ML4811
PHYSICAL DIMENSIONS inches (millimeters) (Continued)

Package: P20
20-Pin PDIP
1.010 - 1.035
(25.65 - 26.29)

20

0.240 - 0.260 0.295 - 0.325


PIN 1 ID
(6.09 - 6.61) (7.49 - 8.26)

1
0.060 MIN
(1.52 MIN) 0.055 - 0.065 0.100 BSC
(4 PLACES) (1.40 - 1.65) (2.54 BSC)

0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)

0.016 - 0.022 SEATING PLANE 0.008 - 0.012


0.125 MIN (0.40 - 0.56) 0º - 15º (0.20 - 0.31)
(3.18 MIN)

Package: S20
20-Pin SOIC
0.498 - 0.512
(12.65 - 13.00)
20

0.291 - 0.301 0.398 - 0.412


(7.39 - 7.65) (10.11 - 10.47)

PIN 1 ID

1
0.024 - 0.034 0.050 BSC
(0.61 - 0.86) (1.27 BSC)
(4 PLACES) 0.095 - 0.107
(2.41 - 2.72)

0º - 8º

0.012 - 0.020 0.022 - 0.042


0.090 - 0.094 0.005 - 0.013 0.007 - 0.015
(0.30 - 0.51) SEATING PLANE (0.56 - 1.07)
(2.28 - 2.39) (0.13 - 0.33) (0.18 - 0.38)

11
ML4810, ML4811

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4810CP 0°C to 70°C 16-Pin PDIP (P16) (End Of Life)


ML4810CS 0°C to 70°C 16-Pin Wide SOIC (S16W) (Obsolete)
ML4811CP 0°C to 70°C 20-Pin PDIP (P20) (Obsolete)
ML4811CS 0°C to 70°C 20-Pin SOIC (S20)(Obsolete)

© Micro Linear 1997 is a registered trademark of Micro Linear Corporation


Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein, 2092 Concourse Drive
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
San Jose, CA 95131
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility Tel: 408/433-5200
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel Fax: 408/432-0295
before deciding on a particular application.

DS4810-01
12

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