l3 - Part1 - Analog Front End Sampling - v22
l3 - Part1 - Analog Front End Sampling - v22
l3 - Part1 - Analog Front End Sampling - v22
Bekkeng, 27.12.2021
Learning outcome
• This is fundamental electronics and signal processing that we
need to know.
10 mV
+ 10V
_ 1000 ADC
Lead Wires
Sampled Signal
Aliasing
Adequately
Sampled
Signal
Signal
Aliased
Signal
A system that has a sampling frequency fs (a) will digitize signals with
frequencies below fs/2 as well as above. Input signals below fs/2 will be
reliably digitized while signals above fs/2 will be folded back (b) and appear
as lower frequencies in the digital output according to faliased = |fin – N*fs |
In post-processing (non-real
time) a zero-phase digital
filter can be used, by
processing the input data in
both the forward and reverse
directions
Analog filters
• Some common filter characteristics
– Butterworth (no rippel)
– Chebyshev
– Bessel (constant group delay = linear
phase in pass band)
– Elliptic
WEBENCH
LP HP
Extra
Switched-Capacitor Filter
• Can be suitable as an ADC anti-aliasing filter if you build your
own electronics
• Be aware of possible clock noise (add RC-filters before and after)
• The corner frequency (cut-off) fc is “programmable” using an
external clock
• Example:
– MAX7400 8th-order,lowpass, elliptic filter
– MAX7400 has a transition ratio (fs/fc) of 1.5 and a typical stop band
rejection of 82dB
ADC architectures
• Multiplexed sampling
– Gives a time delay
between channel sampling
• Simultaneous
sampling
– One ADC, multiple
Sample-and-Hold registers
– Multiple ADCs
– Important for phase
measurements
ADC resolution
• The number of bits used to represent an analog signal determines the
resolution of the ADC
• Larger resolution = more precise representation of your signal
• The resolution determine the smallest detectable change in the input
signal, referred to as code width or LSB (least significant bit)
Examples:
DIFF ADC
+ +
G=1
- -
Gain of 0.1 SPI
VOCM
(attenuation) to 1,
or > 1
Extra
27
Extra
FDA ADC
Buffer (G = 1)
LP-filter
24V input
Optimized Analog Front-End DAQ System Ref Design for 18-Bit SAR Data Converters (Rev. A)
Extra
Isolated DAQ
Extra
Isolated DAQ
18-Bit, 2-MSPS Isolated Data Acquisition Reference Design for Maximum SNR and Sampling Rate (Rev. A)
Extra