Publication date: July 2009

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Part No.
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Package Code No.

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SDB00169AEB
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AN5891K
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SDIP024-P-0300B
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DATA SHEET

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1
AN5891K

Contents
„ Features …………………………………………………………………………………………………………… 3
„ Applications ……………………………………….……………………………………………………………….. 3
„ Package ………………………………………….………………………………………………………………… 3
„ Type ……………………………………………….……………………………………………………………….. 3
„ Application Circuit Example …………………………………….……………………………………………….. 4
„ Block Diagram …………………………….………………………………………………………………………. 5

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„ Pin Descriptions ………………………….……………………………………………………………………….. 6
„ Absolute Maximum Ratings ………….…………………………………………………………………………… 7
„ Operating Supply Voltage Range ……….………………………………………………………………………. 7

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„ Electrical Characteristics …………….…………………………………………………………………………… 8

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„ Electrical Characteristics (Reference values for design) ……………………………………………………… 11

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„ Electrical Characteristics Test Procedures …………………………………………………………………….. 14

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„ Electrical Characteristics (Reference values for design) Test Procedures …………………………………. 16

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„ Technical Data …………………………………………………………………………………………………….. 17
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y I/O block circuit diagrams and pin function descriptions ……………………………………………………... 17
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y I2C bus ……………………………………………………………………………………………………………. 22

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y Adjust method of AGC control ………………………………………………………………………………….. 25

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„ Usage Notes ………………………………………………………………………………………………………. 26

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SDB00169AEB 2
AN5891K

AN5891K
TV and audio sound processor
„ Features
y Sound Processor using I2C bus
y This IC has Mute, AGC, super bass, tone, volume balance control, and 3-D surround.

„ Applications
y TV, Audio

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„ Package
y 24 pin Plastic Shrink Dual Inline Package (SDIP Type)

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„ Type

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y Silicon monolithic bipolar IC

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SDB00169AEB 3
AN5891K

„ Application Circuit Example

VCC Rin Rout SDA SCL

10 μF 10 μF 0.68 μF 0.1 μF 10 μF 10 μF
10 μF 10 nF 10 μF

MODE VCC RIN VREF BB RB RT BLD TD ROUT SDA SCL

24 23 22 21 20 19 18 17 16 15 14 13

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Volume Balance
Tone 2.2 kΩ /MUTE
AGC SURR Control
Control

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1 2 3 4 5 6 7 8 9 10 11 12

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PF1 AGC LIN PF2 PF3 PF4 GND LT LB BD VD LOUT

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33 nF 10 μF 33 nF 0.1 μF 10 μF 10 μF 10 μF
10 μF 39 nF 10 nF

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15 nF
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220 kΩ
on rod
Lin Lout
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Application circuit to get L+R output instead of Super Bass Boost

pla wi
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VCC Rin L+R Out Rout SDA SCL

typ s f
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10 μF 0.1 μF 10 μF 10 μF
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10 μF 10 μF 10 μF 10 nF 10 μF
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MODE VCC RIN VREF BB RB RT BLD TD ROUT SDA SCL

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24 23 22 21 20 19 18 17 16 15 14 13
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Volume Balance
int ten

Tone 2.2 kΩ /MUTE

AGC SURR Control
Control
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1 2 3 4 5 6 7 8 9 10 11 12
PF1 AGC LIN PF2 PF3 PF4 GND LT LB BD VD LOUT
33 nF 10 μF 33 nF 0.1 μF 10 μF 10 μF 10 μF
10 μF 39 nF 10 nF
15 nF
220 kΩ
Lin Lout

Note) This application circuit is shown as an example but does not guarantee the design for mass production set.

SDB00169AEB 4
AN5891K

„ Block Diagram

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MODE VCC RIN VREF BB RB RT BLD TD ROUT SDA SCL
24 23 22 21 20 19 18 17 16 15 14 13

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TONE VOL BAL

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AGC
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SUPER
VCA

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SURR BASS

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AGC TONE VOL BAL

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LEVEL SENSE
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CONTROL
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1 2 3 4 5 6 7 8 9 10 11 12
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typ s f

PF1 AGC LIN PF2 PF3 PF4 GND LT LB BD VD LOUT

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Note) This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified.
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SDB00169AEB 5
AN5891K

„ Pin Descriptions
Pin No. Pin name Description
1 PF1 Phase filter 1
2 AGC AGC level sensor
3 LIN L-ch. input
4 PF2 Phase filter 2
5 PF3 Phase filter 3
6 PF4 Phase filter 4

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7 GND Ground
8 LT L-ch. treble Fc adjustment

9
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LB L-ch. bass Fc adjustment

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10 BD BASS DAC output

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11 VD Volume DAC output

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12 LOUT L-ch. output

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13 SCL SCL

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14 SDA SDA
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15 ROUT R-ch. output
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16 TD Treble DAC output

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17 BLD Balance DAC output

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18 RT R-ch. treble Fc adjustment

typ s f

19 RB R-ch. bass Fc adjustment

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20 BB Bass mixer gain adjustment

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21 VREF 1/2VCC
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22 RIN R-ch. input

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23 VCC Power supply pin (VCC)

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24 MODE Mode control

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SDB00169AEB 6
AN5891K

„ Absolute Maximum Ratings

Note) Absolute maximum ratings are limit values which are not destructed, and are not the values to which operation is guaranteed.

A No. Parameter Symbol Rating Unit Notes

1 Supply voltage VCC 11.0 V *1

2 Supply current ICC 50 mA ⎯
3 Power dissipation PD 550 mW —
4 Operating ambient temperature Topr –25 to +75 °C *2
5 Storage temperature Tstg –55 to +150 °C *2

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Notes) *1 : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2 : Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C.

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„ Operating Supply Voltage Range

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Parameter Symbol Range Unit Notes

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Supply voltage range VCC 6.0 to 10.0 V *

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Note) * : The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
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SDB00169AEB 7
AN5891K

„ Electrical Characteristics at VCC = 9.0 V

Note) Ta = 25°C±2°C unless otherwise specified.

B Limits
Parameter Symbol Conditions Unit Notes
No. Min Typ Max

1 Quiescent Current ICCT No input — 45 60 mA —

VIN = 1 V[rms]
2 Volume (Max Level) VVmax –1 0 1 dB *1
f = 1 kHz
VIN = 1 V[rms]
3 Volume (Mid Level) VVmid –14.5 –12.5 –10.5 dB *1

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f = 1 kHz
VIN = 1 V[rms]
4 Volume (Min Level) VVmin — –100 –90 dB *1
f = 1 kHz

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VIN = 1 V[rms]

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5 THD (1 kHz) THDmax — 0.1 0.3 % *1
f = 1 kHz

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THD = 1%

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6 Max input level VImax 2.0 2.2 — V[rms] *1

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f = 1 kHz
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VIN = 0 V[rms]

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7 Output noise at volume min VNmin — 3 10 μV *2

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Rg = 4.7 kΩ

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VIN = 0 V[rms]
8 Output noise at volume max VNmax — 65 100 μV *2
sc te

on rod
Rg = 4.7 kΩ
isc r P

VIN = 1 V[rms]
d d fou

9 Mute Level VMUTE — –100 –90 dB *1

f = 1 kHz
Di ain

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VIN = 1 V[rms]
pla wi

10 Balance (Max Level) VBmax –1 0 1 dB *1

e, ollo

f = 1 kHz
typ s f

VIN = 1 V[rms]
ce de

11 Balance (Min Level) VBmin — –82 –80 dB *1

f = 1 kHz
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VIN = 400 mV[rms]

12 Bass (Max Level) VBBmax 10 12.5 15 dB —
int ed

f = 50 Hz
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VIN = 400 mV[rms]

13 Bass (Min Level) VBBmin –13.5 –11.0 –8.5 dB —
f = 50 Hz
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VIN = 400 mV[rms]

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14 Treble (Max Level) VTBmax 10 12.5 15 dB —

f = 20 kHz
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VIN = 400 mV[rms]

15 Treble (Min Level) VTBmin –13.5 –11.0 –8.5 dB —
ma ain

f = 20 kHz
M

VIN = 400 mV[rms]

16 Super bass (Max Level) VXBmax 3 5 7 dB *1
f = 50 Hz
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VIN = 400 mV[rms]

17 Super bass (Min Level) VXBmin 0 2 4 dB *1
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f = 50 Hz

Notes) *1 : DIN AUDIO filter used.

*2 : A-weighted noise filter used.

SDB00169AEB 8
AN5891K

„ Electrical Characteristics (continued) at VCC = 9.0 V

Note) Ta = 25°C±2°C unless otherwise specified.

B Limits
Parameter Symbol Conditions Unit Notes
No. Min Typ Max

VIN = 50 mV[rms]
18 AGC gain 1 VAGC1 77 110 150 mV[rms] *1
f = 1 kHz
VIN = 1 V[rms]
19 AGC gain 2 VAGC2 230 345 470 mV[rms] *1
f = 1 kHz
VIN = 50 mV[rms]
20 Surround level 1 VSU1 200 240 280 mV[rms] *1

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f = 50 Hz
VIN = 50 mV[rms]
21 Surround level 2 VSU2 130 170 210 mV[rms] *1
f = 10 kHz

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VIN = 0 mV

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22 Surround noise Level VSN — 110 150 μV[rms] *2
Rg = 4.7 kΩ

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VIN = 400 mV[rms]

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23 THD (Surround) THDSU — 0.1 0.3 % *1

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f = 1 kHz

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VIN = 1 V[rms]

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24 Cross talk CT — –78 –66 dB *2

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f = 1 kHz

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tin uc
VIN = 1 V[rms]
25 Channel balance (Max) CBmax –1 0 1 dB *1
sc te

on rod
f = 1 kHz
isc r P

VIN = 1 V[rms]
d d fou

26 Channel balance (1/4) CB1/4 –2 0 2 dB *1

f = 1 kHz
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Notes) *1 : DIN AUDIO filter used.

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*2 : A-weighted noise filter used.

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SDB00169AEB 9
AN5891K

„ Electrical Characteristics (continued) at VCC = 9.0 V

Note) Ta = 25°C±2°C unless otherwise specified.

Limits
B
Parameter Symbol Conditions Unit Notes
No. Min Typ Max

I2C Interface
Max. suction current value of Pin
27 Suction current during ACK IACK 3.0 10 — mA —
14 at 0 4 V
28 SCL, SDA signal input High level VIHI — 3.0 — 5.0 V —

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29 SCL, SDA signal input Low level VILO — 0 — 1.5 V —
30 Max frequency allowable to input fimax — — — 100 kbit/s —

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SDB00169AEB 10
AN5891K

„ Electrical Characteristics (Reference values for design) at VCC = 9.0 V

Note) Ta = 25°C±2°C unless otherwise specified.
The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection.
If a problem does occur related to these characteristics, we will respond in good faith to user concerns.

Reference values
B No. Parameter Symbol Conditions Unit Notes
Min Typ Max
I2C interface
1 Bus free before start tBUF — 4.0 — — μs —
2 Set-up time of START condition tSU,STA — 4.0 — — μs —

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3 Hold time of START condition tHD,STA — 4.0 — — μs —
4 Low period of SCL, SDA tLO — 4.0 — — μs —
5
tin nc
High period of SCL tHI — 4.0 — — μs —

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6 SCL, SDA rise time tR — — — 1.0 μs —

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7 SCL, SDA fall time tF — — — 0.35 μs —

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8 Data set-up time (Write) tSU,DAT — 0.25 — — μs —

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9 Data hold time (Write) tHD,DAT — 0 — — μs —

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10 Acknowledge set-up time tSU,ACK — — — 3.5 μs —
tin uc
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on rod
11 Acknowledge hold time tHD,ACK — 0 — — μs —
isc r P

μs
d d fou

12 [STOP] condition set-up time tSU,STO — 4.0 — — —

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DAC
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1LSB = LSB/
13 6 bit DAC DNLE L6 0.1 1.0 1.9 —
[Data (max) – Data (00)]/63 STEP
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SDB00169AEB 11
AN5891K

„ Electrical Characteristics (Reference values for design) (continued) at VCC = 9 V

Note) Ta = 25°C±2°C unless otherwise specified.
The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection.
If a problem does occur related to these characteristics, we will respond in good faith to user concerns.

START Slave Acknowledge Subaddress Acknowledge Data Acknowledge STOP

condition address bit bit byte bit condition

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SDA

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tBUF tSU,DAT tHD,DAT

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tSU,STO

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SCL

tin
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tSU,STA
tHD,STA tR tF tHI tLO

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SDB00169AEB 12
AN5891K

„ Electrical Characteristics (Reference values for design) (continued) at VCC = 9.0 V

Note) Ta = 25°C±2°C unless otherwise specified.
The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection.
If a problem does occur related to these characteristics, we will respond in good faith to user concerns.

Reference values
B No. Parameter Symbol Conditions Unit Notes
Min Typ Max
AGC gain 3 VIN = 100 mV[rms]
14 VAGC3 — 150 — mV[rms] *1
(Sub address 04H : 05H) f = 1 kHz
AGC gain 4 VIN = 140 mV[rms]
15 VAGC4 — 200 — mV[rms] *1
(Sub address 04H : 03H) f = 1 kHz

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AGC gain 5 VIN = 200 mV[rms]
16 VAGC5 — 250 — mV[rms] *1
(Sub address 04H : 01H) f = 1 kHz

tin nc
AGC gain 6 VIN = 280 mV[rms]

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17 VAGC6 — 350 — mV[rms] *1

d
(Sub address 04H : 07H) f = 1 kHz

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dt
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AGC gain 7 VIN = 500 mV[rms]

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18 VAGC7 180 290 430 mV[rms] *1

isc ag
(Sub address 04H : 03H) f = 1 kHz

tin
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on na

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Note) *1 : DIN AUDIO filter used.

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SDB00169AEB 13
AN5891K

„ Electrical Characteristics Test Procedures

C SW Sub address
Parameter Symbol Input conditions
No. 1 2 3 4 5 6 00H 01H 02H 03H 04H

1 Quiescent Current ICCT — — — — ON OFF VIN = 0 mV FC 80 77 00 00

VIN = 1 V[rms]
2 Volume (Max Level) VVmax b, a a, b b, a a ON OFF FC 80 77 00 00
f = 1 kHz
VIN = 1 V[rms]
3 Volume (Mid Level) VVmid b, a a, b b, a a ON OFF 80 80 77 00 00
f = 1 kHz

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VIN = 1 V[rms]
4 Volume (Min Level) VVmin b, a a, b b, a a ON OFF 00 80 77 00 00
f = 1 kHz
VIN = 1 V[rms]
5 THD (1 kHz) THDmax b, a a, b b, a a ON OFF FC 80 77 00 00

tin nc f = 1 kHz

e)
d
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THD = 1%

dt
6 Max input level VImax b, a a, b b, a a ON OFF FC 80 77 00 00
f = 1 kHz

on e.
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isc ag
tin
, d st
VIN = 0 mV
on na
7 Output noise at volume min VNmin c c b, a b ON OFF 00 80 77 00 00

ed cle
Rg = 4.7 kΩ

yp cy
d t ife
VIN = 0 mV
8 Output noise at volume max VNmax c c b, a b ON OFF FC 80 77 00 00

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Rg = 4.7 kΩ
tin uc
sc te

on rod
VIN = 1 V[rms]
9 Mute Level VMUTE b, a a, b b, a a ON OFF FE 80 77 00 00
isc r P
f = 1 kHz
d d fou

VIN = 1 V[rms] FC,

10 Balance (Max Level) VBmax b, a a, b b, a a ON OFF FC 77 00 00
Di ain

ne ng

f = 1 kHz 00
pla wi
e, ollo

VIN = 1 V[rms] FC,

11 Balance (Min Level) VBmin b, a a, b b, a a ON OFF FC 77 00 00
typ s f

f = 1 kHz 00
ce de

VIN = 400 mV[rms]

an clu

12 Bass (Max Level) VBBmax b, a a, b b, a c ON OFF FC 80 7F 00 00

f = 50 Hz
en in
M

int ed

VIN = 400 mV[rms]

ma inu

13 Bass (Min Level) VBBmin b, a a, b b, a c ON OFF FC 80 70 00 00

f = 50 Hz
e, ont
typ isc

VIN = 400 mV[rms]

14 Treble (Max Level) VTBmax b, a a, b b, a c ON OFF FC 80 F7 00 00
ce /D

f = 20 kHz
an ce
en an

VIN = 400 mV[rms]

15 Treble (Min Level) VTBmin b, a a, b b, a c ON OFF FC 80 07 00 00
int ten

f = 20 kHz
ma ain

VIN = 400 mV[rms]

M

16 Super bass (Max Level) VXBmax b, a a, b b, a c ON OFF FD 80 77 00 00

f = 50 Hz
VIN = 400 mV[rms]
ed

17 Super bass (Min Level) VXBmin b, a a, b b, a c ON OFF FD 83 77 00 00

f = 50 Hz
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SDB00169AEB 14
AN5891K

„ Electrical Characteristics Test Procedures (continued)

C SW Sub address
Parameter Symbol Input conditions
No. 1 2 3 4 5 6 00H 01H 02H 03H 04H
VIN = 50 mV[rms]
18 AGC gain 1 VAGC1 b, a a, b a, b a ON OFF FC 80 77 00 03
f = 1 kHz
VIN = 1 V[rms]
19 AGC gain 2 VAGC2 b, a a, b a, b a ON OFF FC 80 77 00 03
f = 1 kHz
VIN = 50 mV[rms]
20 Surround level 1 VSU1 b, a a, b b, a a ON OFF FC 80 77 80 00
f = 50 Hz

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VIN = 50 mV[rms]
21 Surround level 2 VSU2 b, a a, b b, a a ON OFF FC 80 77 80 00
f = 10 kHz
VIN = 0 mV[rms]
22

tin nc
Surround noise Level VSN c c b, a b ON OFF
Rg = 4.7 kΩ
FC 80 77 80 00

e)
d
yp
VIN = 400 mV[rms]

dt
23 THD (Surround) THDSU b, a a, b a a ON OFF FC 80 77 80 00

on e.
ue
f = 1 kHz

isc ag
tin
, d st
on na
VIN = 1 V[rms]
24 Cross talk CT b, a a, b a, b b ON OFF FC 80 77 00 00

ed cle
f = 1 kHz

yp cy
d t ife
VIN = 1 V[rms]
25 Channel balance (Max) CBmax — — — — ON OFF FC 80 77 00 00

ue t l
f = 1 kHz
tin uc
sc te

on rod
VIN = 1 V[rms]
26 Channel balance (1/4) CB1/4 — — — — ON OFF 40 80 77 00 00
isc r P

f = 1 kHz
d d fou
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SDB00169AEB 15
AN5891K

„ Electrical Characteristics (Reference values for design) Test Procedures

C SW Sub address
Parameter Symbol Input conditions
No. 1 2 3 4 5 6 00H 01H 02H 03H 04H
VIN = 100 mV[rms]
14 AGC gain 3 VAGC3 b, a a, b b, a a ON OFF FC 80 77 00 05
f = 1 kHz
VIN = 140 mV[rms]
15 AGC gain 4 VAGC4 b, a a, b b, a a ON OFF FC 80 77 00 03
f = 1 kHz
VIN = 200 mV[rms]
16 AGC gain 5 VAGC5 b, a a, b b, a a ON OFF FC 80 77 00 01
f = 1 kHz

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VIN = 280 mV[rms]
17 AGC gain 6 VAGC6 b, a a, b b, a a ON OFF FC 80 77 00 07
f = 1 kHz
VIN = 500 mV[rms]
18

tin nc
AGC gain 7 VAGC7 b, a a, b b, a a ON OFF
f = 1 kHz
FC 80 77 00 03

e)
d
yp
dt
on e.
ue
isc ag
tin
, d st
on na

ed cle
yp cy
d t ife
ue t l
tin uc
sc te

on rod
isc r P
d d fou
Di ain

ne ng
pla wi
e, ollo
typ s f
ce de
an clu
en in
M

int ed
ma inu
e, ont
typ isc
ce /D
an ce
en an
int ten
ma ain
ed M
lan
(p

SDB00169AEB 16
AN5891K

„ Technical Data
y I/O block circuit diagrams and pin function descriptions
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Pin Waveform and

Internal circuit Description
No. voltage

1 4.5 V 1 5k 2k Phase filter 1

ue e/
tin nc

e)
Level 2 Level 1

d
yp
dt
on e.
ue
isc ag
Depend on input

tin
, d st
on na
2 level AGC level sensor

ed cle
0.5 V to 2.0 V 1k 50k 2k

yp cy
d t ife
ue t l
2

tin uc
sc te

on rod
isc r P
d d fou
Di ain

ne ng
pla wi
e, ollo

3
3 4.5 V 1.5k L-ch. input
typ s f
ce de

82k
an clu
en in
M

1/2 VCC
int ed
ma inu
e, ont
typ isc
ce /D
an ce

2.5k
en an

4 4.5 V Phase filter 2

int ten

4
ma ain
ed M
lan
(p

5
5 4.5 V 2k Phase filter 3

2.5k

SDB00169AEB 17
AN5891K

„ Technical Data (continued)

y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Pin Waveform and

Internal circuit Description
No. voltage

6 5k 2k
6 4.5 V Phase filter 4

ue e/
tin nc

e)
7 0V — GND

d
yp
dt
on e.
ue
isc ag
tin
, d st
on na

ed cle
6.3k

yp cy
d t ife
8 4.5 V 900 L-ch. Treble Fc adjustment
8

ue t l
tin uc
sc te

on rod
isc r P
d d fou
Di ain

ne ng
pla wi
e, ollo
typ s f
ce de

8.64k
an clu

9 L-ch. Bass Fc adjustment

9 4.5 V 1.36k
en in
M

int ed
ma inu
e, ont
typ isc
ce /D
an ce
en an
int ten
ma ain

10 250
M

Depend on I2C
10 data 9.4k Bass DAC output
250
ed

1.6 V to 2.5 V
lan

2.0 V
(p

SDB00169AEB 18
AN5891K

„ Technical Data (continued)

y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Pin Waveform and

Internal circuit Description
No. voltage

3.5 V 5k
11
2C
Depend on I 11k
11 data 600 Volume DAC output

ue e/
2.0 V to 4.0 V

tin nc

e)
d
yp
dt
on e.
ue
isc ag
250

tin
, d st
on na
12 4.5 V L-ch. output

ed cle
12

yp cy
d t ife
500

ue t l
tin uc
sc te

on rod
isc r P
d d fou

2k
Di ain

ne ng

13
pla wi

13 — I2C bus clock input

e, ollo

15p
typ s f
ce de
an clu
en in
M

int ed
ma inu
e, ont

2k
14
typ isc

14 — I2C bus data input

ce /D

15p
an ce
en an
int ten
ma ain
ed M

250
lan

15 4.5 V R-ch. output

(p

15

500

SDB00169AEB 19
AN5891K

„ Technical Data (continued)

y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Pin Waveform and

Internal circuit Description
No. voltage

16 250
Depend on I2C
16 data 9.4k Treble DAC output
250

ue e/
1.6 V to 2.5 V
2.0 V

tin nc

e)
d
yp
dt
on e.
ue
isc ag
3.5 V 5k 17

tin
, d st
on na

ed cle
Depend on I2C

yp cy
17 data 250 Balance DAC output

d t ife
2.5 V to 3.5 V 250

ue t l
tin uc
sc te

on rod
isc r P
d d fou
Di ain

ne ng
pla wi
e, ollo

6.3k
typ s f

18 4.5 V 900 R-ch. Treble Fc adjustment

ce de

18
an clu
en in
M

int ed
ma inu
e, ont
typ isc
ce /D
an ce

8.64k
en an

19
int ten

19 4.5 V 1.36k R-ch. Bass Fc adjustment

ma ain
ed M
lan
(p

20

20 4.5 V 2.2k Bass mix gain adjustment

2k

SDB00169AEB 20
AN5891K

„ Technical Data (continued)

y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed.

Pin Waveform and

Internal circuit Description
No. voltage

70k
21
500
21 4.5 V Reference voltage stabilizing

ue e/
70k

tin nc

e)
d
yp
dt
on e.
ue
isc ag
tin
, d st
on na
22

ed cle
1.5k

yp cy
22 4.5 V R-ch. input

d t ife
ue t l
82k

tin uc
sc te

on rod
isc r P
1/2VCC
d d fou
Di ain

ne ng

23 9.0 V — VCC
pla wi
e, ollo
typ s f
ce de
an clu
en in
M

Depend on I2C 30.8k

int ed

24 data 24 Mode control

ma inu

1k
0.6 V to 2.6 V
e, ont
typ isc
ce /D
an ce
en an
int ten
ma ain
ed M
lan
(p

SDB00169AEB 21
AN5891K

„ Technical Data (continued)

y I2C-bus

2. Transmission Message

SDA

SCL

ue e/
START condition Slave address ACK Sub address ACK Data ACK STOP
condition
1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0

tin nc 8 2 0 2 1 2

e)
d
yp
Fig.1 Example of transmission message

dt
on e.
ue
isc ag
tin
, d st
on na

ed cle
For transmission messages, both SCL and SDA are transferred in the form of synchronized serial transmission.

yp cy
SCL is a clock of a specific frequency, and SDA indicates address data for controlling the receiving side and is transferred in

d t ife
parallel, being synchronized with SCL.

ue t l
Data is transferred in principle in 3 octets (bytes), and each one octet (one octet = 8 bits) includes one acknowledge bit.
tin uc
sc te

on rod
Frame structure is described below.
isc r P
d d fou

(a) START condition

Di ain

ne ng

The receiver becomes possible to receive data when SDA changes from High to Low while SCL is High.
pla wi
e, ollo

(b) STOP condition

typ s f

The receiver halts receiving when SDA changes from Low to High while SCL is High.
ce de
an clu

(c) Slave address

en in
M

This is an address which is determined for each device. If other device address is sent, receiving will be halted.
int ed
ma inu

(d) Sub address

e, ont

This is an address which is determined for each function.

typ isc
ce /D
an ce

(e) Data
en an

This is control data.

int ten
ma ain

(f) Acknowledge bit

M

This is a bit by which the master acknowledges that data was successfully received in each octet. Master sends the High
signal and the receiver sends back the Low signal as shown in Figure 1 with dotted line, causing the master to
acknowledge the reception by the receiver. If the Low signal is not returned, communication will be halted.
ed

Except START and STOP conditions, SDA does not change while SCL is High.
lan
(p

SDB00169AEB 22
AN5891K

„ Technical Data (continued)

y I2C-bus (continued)
3. I2C Bus Addressing
(1) This contains 7 DAC controls and 4 SWs.
(2) オートインクリメント機能は以下のとおりです。
y Sub address 0xxxxxxx : Auto-increment mode
(When the data is sent in consecutive order, the Sub address will be changed in consecutive order, as data is input.)
y Sub address 1xxxxxxx : Data update mode
(When the data is sent consecutively, it is sent to the same Sub address.)
(3) I2C bus protocol
y Slave address : 10000010 (82H)

ue e/
y Format (Usual)

tin nc

e)
d
yp
dt
on e.
ue
isc ag
tin
, d st
S Slave address A Sub address A Data byte A P
on na

ed cle
yp cy
d t ife
Ack

ue t l
START STOP

tin uc
condition condition
sc te

on rod
isc r P
d d fou
Di ain

ne ng

y Auto increment mode/Data update mode

pla wi
e, ollo

S Slave address A Sub address A Data 1 A Data 2 A Data n A P

typ s f
ce de
an clu

START Ack
en in
M

STOP
condition
int ed

condition
ma inu
e, ont
typ isc
ce /D
an ce

(4) Since the DAC initial status is not guaranteed, the standard data input is certainly necessary when power is turned ON.
en an
int ten
ma ain
ed M
lan
(p

SDB00169AEB 23
AN5891K

„ Technical Data (continued)

y I2C-bus (continued)
3. I2C Bus Addressing (continued)

(5) Sub address byte and data byte format

Sub Upper MSB Data byte

address
D7 D6 D5 D4 D3 D2 D1 D0
Mute Super Bass
00 Volume
ON/OFF ON/OFF

ue e/
BASS Mix
01 Balance
Effect

tin nc02 L/R Treble L/R Bass

e)
d
yp
dt
× ×

on e.
03 MODE Surround Effect

ue
isc ag
tin
, d st
on na
Not defined AGC
04 AGC ADJ

ed cle
ON/OFF

yp cy
d t ife
ue t l
tin uc
1) MODE 6) Bass Mix ON/OFF
sc te

on rod
"00" = Bypass DATA = "0" : OFF
isc r P

"01" = Simulated Stereo DATA = "1" : ON

d d fou

"10" = Stereo Surround

Di ain

ne ng
pla wi

"11" = Mono surround 7) Bass Mix Effect

e, ollo

DATA = "11" : min

typ s f

2) Volume DATA = "00" : max

ce de
an clu

DATA = "000000" : min

en in
M

DATA = "111111" : max 8) AGC ON/OFF

int ed

DATA = "0" : OFF

ma inu
e, ont

3) Balance DATA = "1" : ON

typ isc

DATA = "000000" : Lout : min, Rout : max

ce /D

DATA = "100000" : CENTER 9) AGC ADJ (0 dB Adjustment) *

an ce
en an

DATA = "111111" : Lout : max, Rout : min DATA = "00" : 200 mV[rms]
int ten

DATA = "01" : 140 mV[rms]

ma ain

4) L/R Treble, Bass DATA = "10" : 100 mV[rms]

M

DATA = "0000" : min DATA = "11" : 280 mV[rms]

DATA = "0111" : CENTER
ed

DATA = "1111" : max 10) Surround Effect

lan

DATA = "1111" : min

(p

5) Mute ON/OFF DATA = "0000" : max

DATA = "0" : OFF
DATA = "1" : ON

Note) * : 0 dB Adjustment level of AGC is reference value, and not guaranteed by shipping inspection.

SDB00169AEB 24
 AN5891K

Output level VO (mV[rms])

M y Adjust method of AGC control
„ Technical Data (continued)

(p
lan
ed M
ma ain
int ten
en an
Di ain
an ce
ce /D
typ isc
sc te
e, ont
ma inu
int ed
en in

SDB00169AEB
on na
an clu
AGC Characteristic

ce de
typ s f

Input level VIN (mV[rms])

e, ollo
pla wi
します。また，AGCの入出力特性は下記のとおりI2Cによって制御できます。

tin nc
ne ng
d d fou
isc r P
on rod
tin uc
ue e/
ue t l
d t ife
yp cy
d ed cle
, d st
isc ag
on e.
tin
ue
dt
yp
e)
AGCがONの場合，入出力ゲインは小信号レベルにおいては0 dB，標準信号レベルでは上昇し，大信号レベルでは減少

25
AN5891K

„ Usage Notes
y Special attention and precaution in using
1. This IC is intended to be used for general electronic equipment [Television].
Consult our sales staff in advance for information on the following applications:
x Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may
directly jeopardize life or harm the human body.
x Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automobile, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant

ue e/
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might

tin nc

e)
smoke or ignite.

d
yp
3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In

dt
on e.
addition, refer to the Pin Description for the pin configuration.

ue
isc ag
tin
4. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solder-

, d st
on na

ed cle
bridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because

yp cy
the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during

d t ife
transportation.

ue t l
tin uc
5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin-
sc te

on rod
VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load short) .
isc r P

And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and
d d fou

smoke emission will depend on the current capability of the power supply.
Di ain

ne ng

6. When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
pla wi

(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
e, ollo

maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
typ s f

defect which may arise later in your equipment.

ce de
an clu

Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
en in
M

mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
int ed

or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
ma inu

7. When using the LSI for new models, verify the safety including the long-term reliability for each product.
e, ont

8. When the application system is designed by using this LSI, be sure to confirm notes in this book.
typ isc

Be sure to read the notes to descriptions and the usage notes in the book.
ce /D
an ce
en an
int ten
ma ain
ed M
lan
(p

SDB00169AEB 26
 Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.

(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.

(3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office
equipment, communications equipment, measuring instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support
systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod-
ucts may directly jeopardize life or harm the human body.
– Any applications other than the standard applications intended.

(4) The products and product specifications described in this book are subject to change without notice for modification and/or im-
provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product

ue e/
Standards in advance to make sure that the latest specifications satisfy your requirements.

(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute

tin nc

e)
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any

d
yp
defect which may arise later in your equipment.

dt
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure

on e.
ue
isc ag
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire

tin
, d st
on na
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.

ed cle
yp cy
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,

d t ife
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which

ue t l
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
tin uc
sc te

on rod
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
isc r P
d d fou

20080805
Di ain

ne ng
pla wi
e, ollo
typ s f
ce de
an clu
e n in
M

int ed
ma inu
e, ont
typ isc
ce /D
an ce
en an
int ten
ma ain
ed M
lan
(p