Other types of concurrent VHDL signal assignments

 The “<=“ operator is not the only means by which we can perform combinational
assignments in VHDL.

 There are other concurrent signal assignment operators that make writing VHDL a bit
easier.

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Concurrent signal assignments (1)

 We have the concurrent signal assignment statement “<=“ for representing logic
equations in VHDL.
 Example (this is a 4-to-1 multiplexer):

-- implementation of a 4-to-1 multiplexer

-- version using concurrent signal assignment.

library ieee;
use ieee.std_logic_1164.all;

entity mux4to1_version1 is
port (x1, x2, x3, x4 : in std_logic; -- inputs
s : in std_logic_vector(1 downto 0); -- controls
f : out std_logic); -- output
end entity;

architecture prototype of mux4to1_version1 is

begin
f <= (not s(0) and not s(1) and x1) or
(not s(0) and s(1) and x2) or
( s(0) and not s(1) and x3) or
( s(0) and s(1) and x4);
end prototype;

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Conditional signal assignments (1)

 A conditional signal assignment is another construct for assigning the value to a

function.

 It offers a higher level of abstraction that the concurrent signal assignment (which is
at the gate level; e.g., AND, OR and NOT gates).

 Basic syntax is:

signal <= other_signal1 when (condition1) else

other_signal2 when (condition2) else
other_signal3 when (condition3) else
…
other_signaln when (conditionn) else
default_signal ;

 Notice that we always have a default assignment in case none of the conditions are
true.

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Conditional signal assignments (2)

 Example (this is a 4-to-1 multiplexer):

-- implementation of a 4-to-1 multiplexer

-- version using conditional signal assignment.

library ieee;
use ieee.std_logic_1164.all;

entity mux4to1_version2 is
port (x1, x2, x3, x4 : in std_logic; -- inputs
s : in std_logic_vector(1 downto 0); -- controls
f : out std_logic); -- output
end entity;

architecture prototype of mux4to1_version2 is

begin
f <= x1 when (s = "00") else
x2 when (s = "10") else
x3 when (s = "01") else
x4;
end prototype;

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Conditional signal assignments (3)

 The ordering of the “when-else” is important – they are evaluated in order.

 There is a priority implied.

 Several conditions may be true, but the first true condition encountered will
determine the resulting signal assignment.

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Priority encoder (1)

 Illustration of priority via a 8-to-3 priority encoder…

library ieee;
use ieee.std_logic_1164.all;

entity priority8 is
port (x : in std_logic_vector(7 downto 0); -- input lines
valid : out std_logic; -- output valid?
y : out std_logic_vector(2 downto 0)); -- encoded output.
end priority8;

architecture prototype of priority8 is

begin
y <= "111" when (x(7) = '1') else -- value of lower inputs not important
"110" when (x(6) = '1') else
"101" when (x(5) = '1') else
"100" when (x(4) = '1') else
"011" when (x(3) = '1') else
"010" when (x(2) = '1') else
"001" when (x(1) = '1') else
"000" when (x(0) = '1') else
"000";

valid <= '0' when x = "00000000" else '1';

end prototype;

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Priority encoder (2)

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Selected signal assignment (1)

 Selected signal assignment is very similar to the conditional signal assignment.

 It also offers a higher level than abstraction compared to a concurrent assignment.

 The value to be assigned to a signal is determined by the value of a select expression,

much like a case statement in a conventional programming language.

 It has the syntax:

with (some_signal) select

other_signal <= value1 when (condition1) ,
value2 when (condition2) ,
…,
default_value when others ;

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Selected signal assignment (2)

 We can write VHDL for a 4-to-1 multiplexer using selected signal assignment which is
more abstract, representing the operation of a multiplexer:

-- version using selected signal assignment.

library ieee;
use ieee.std_logic_1164.all;

entity mux4to1_version3 is
port (x1, x2, x3, x4 : in std_logic;
s : in std_logic_vector(1 downto 0);
f : out std_logic);
end entity;

architecture prototype of mux4to1_version3 is

begin
with s select
f <= x1 when "00" ,
x2 when "10" ,
x3 when "01" ,
x4 when others;
end prototype;

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Selected vs. conditional signal assignment

 The selected signal assignment is different that the conditional signal assignment in
that (1) there is no priority and (2) all choices are evaluated at once (and therefore
only one choice can be true at any time).

 All possible choices need to be specified, but we can capture values that we are not
interested in using the others keyword.

 The “others” keyword conveniently captures all the other possible values of the
select signal.

 Note: we should always include the “when others;” in the selected signal
assignment.

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Constants

 In the explanation of our new conditional and selected signal assignment statements,
we saw the assignment of constants to signals and to vectors of signals.

 To assign a constant to a signal, or to a single bit of a vector of signals, we enclose the

constant inside of single tick marks:

E.g., f <= ‘1’; -- f is std_logic

E.g., y(4) <= ‘0’; -- y is std_logic_vector and y(4) is 4-th bit.

 To assign a vector of signals all at once, we assign each bit, but enclose the bits inside
of double quotation marks:

E.g., z <= “10011”; -- z is a 5-bit std_logic_vector

E.g., z(3 downto 0) <= “1110”;
-- z is std_logic_vector and this assigns lowest 4-bits.

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Signal declarations inside of the architecture

 In all the examples so far, we have only seen how to declare signals in the port section
of the entity declaration.

 Sometimes, we will have signals internal to our implementation. These signals get
declared in the declarative section of the architecture:
 (We will see more on this later)…

-- notice entity declaration skipped…

architecture prototype of something is
-- declarative section

signal temp_signal : std_logic ; -- signal can be used below in the

-- implementation section.
signal temp_bus : std_logic_vector(12 down 0);

begin prototype
-- implementation section

end prototype;

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