09 VHDL Component Instantiations

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Component instantiations

 Often we will have a VHDL Description of part of a circuit that we would like to use inside of
another circuit.
 As an example, consider building an n-bit ripple adder from 1-bit full adders.

 We can use VHDL descriptions inside of other VHDL descriptions by:

 Declaring components we wish to use.


 Creating or instantiating copies of the components.
 Connecting together the components.

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VHDL description of a 1-bit adder

-- VHDL for 1-bit full adder.

library ieee;
use ieee.std_logic_1164.all;

entity fulladder1 is
port( a,b,c : in std_logic;
s,z : out std_logic);
end fulladder1;

architecture prototype of fulladder1 is


begin
s <= a xor b xor c; -- sum
z <= (a and b) or (a and c) or (b and c); -- cout
end prototype;

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VHDL description of a 4-bit adder (built from 1-bit adders)
(1)
 Before we can use the 1-bit adder, we need to declare it inside of the declarative section of
architecture of the 4-bit adder:

-- VHDL for a 4-bit adder built from 1-bit adders.

library ieee;
use ieee.std_logic_1164.all;

entity fulladder4 is
port (x,y : in std_logic_vector(3 downto 0);
cin : in std_logic;
sum : out std_logic_vector(3 downto 0);
cout : out std_logic);
end fulladder4;

architecture prototype of fulladder4 is


-- need to declare the components (other VHDL descriptions) we will use.

component
-- like the entity of the circuit we want to use, but notice the “component” keyword
component fulladder1
port (a,b,c
s,z
: in std_logic;
: out std_logic);
declaration
end component;

signal c1, c2, c3 : std_logic; -- temporary signals needed in the architecture.

begin
temporary
-- description will go here. signals
end prototype;

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VHDL description of a 4-bit adder (built from 1-bit adders)
(2)
 Once we have declared components, we can instantiate copies in the architecture body and
connect them together:

-- VHDL for a 4-bit adder built from 1-bit adders.

-- continued from previous page (architecture body only).

component

architecture prototype of fulladder4 is
component fulladder1
port (a,b,c : in std_logic;
declaration
s,z : out std_logic);
end component;

signal c1, c2, c3 : std_logic; -- temporary signals needed in the architecture.


temporary
begin signals
bit0: fulladder1
port map (a=>x(0),b=>y(0),c=> cin,s=> sum(0),z=> c1);
bit1: fulladder1
port map (a=>x(1),b=>y(1),c=> c1,s=> sum(1),z=>
bit2: fulladder1
c2); component
port map (a=>x(2),b=>y(2),c=> c2,s=> sum(2),z=> c3); instantiations
bit3: fulladder1
port map (a=>x(3),b=>y(3),c=> c3,s=> sum(3),z=> cout); and wiring
end prototype;

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Summary

 Once we declare a component (another VHDL Description), we can create a copy of it using the
syntax:

instance_name : component_name
port map ( signal_in_component => signal_in_current_circuit,
signal_in_component => signal_in_current_circuit,

signal_in_component => signal_in_current_circuit
);

 The notation “=>” inside of the “port map” is like connecting or wiring the signal in the current
circuit to an input or output pin of the sub-circuit (the component).

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Simulation

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Comments

 Note that we needed temporary signals in order to connect the 1-bit full adders
together inside of the architecture body of the 4-bit full adder:

architecture prototype of fulladder4 is


-- component declarations…

signal c1, c2, c3 : std_logic; -- temporary signals needed in the architecture.

begin
-- cicuit description…
end prototype;

 The syntax for this is:

signal signal_name : type ;

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