09 VHDL Component Instantiations
09 VHDL Component Instantiations
09 VHDL Component Instantiations
Often we will have a VHDL Description of part of a circuit that we would like to use inside of
another circuit.
As an example, consider building an n-bit ripple adder from 1-bit full adders.
library ieee;
use ieee.std_logic_1164.all;
entity fulladder1 is
port( a,b,c : in std_logic;
s,z : out std_logic);
end fulladder1;
library ieee;
use ieee.std_logic_1164.all;
entity fulladder4 is
port (x,y : in std_logic_vector(3 downto 0);
cin : in std_logic;
sum : out std_logic_vector(3 downto 0);
cout : out std_logic);
end fulladder4;
component
-- like the entity of the circuit we want to use, but notice the “component” keyword
component fulladder1
port (a,b,c
s,z
: in std_logic;
: out std_logic);
declaration
end component;
begin
temporary
-- description will go here. signals
end prototype;
component
…
architecture prototype of fulladder4 is
component fulladder1
port (a,b,c : in std_logic;
declaration
s,z : out std_logic);
end component;
Once we declare a component (another VHDL Description), we can create a copy of it using the
syntax:
instance_name : component_name
port map ( signal_in_component => signal_in_current_circuit,
signal_in_component => signal_in_current_circuit,
…
signal_in_component => signal_in_current_circuit
);
The notation “=>” inside of the “port map” is like connecting or wiring the signal in the current
circuit to an input or output pin of the sub-circuit (the component).
Note that we needed temporary signals in order to connect the 1-bit full adders
together inside of the architecture body of the 4-bit full adder:
begin
-- cicuit description…
end prototype;