08 VHDL Introduction
08 VHDL Introduction
The acronym VHSIC in turn stands for Very-High Speed Integrated Circuit program.
The language became the IEEE Standard 1076-1987. New features added later and
forms the IEEE Standard 1076-1993.
So, VHDL is somewhat generic in that although we are using it for digital systems, it
does not specifically rely on any underlying implementation technology.
Simulation using a VHDL Simulator takes a VHDL description and executes the
description to mimic the behavior of the circuit in terms of events and waveforms.
We can get an idea of how we can use VHDL to describe digital systems if we try to draw an analogy
between VHDL and a schematic.
Consider the following circuit (schematic) implementing a two simple logic functions:
a
b s
c
entity FullAdder is
port( a,b,c : in std_logic; z
s,z : out std_logic);
end FullAdder;
We can simulate the design using a VHDL Simulator to test correct functionality or we can
synthesis the design to get a circuit (in some technology).
library ieee;
use ieee.std_logic_1164.all;
entity FullAdder is
port( a,b,c : in std_logic;
s,z : out std_logic);
end FullAdder;
Entity declaration.
Architecture definition.
The entity declaration describes the interface to the rest of the world; i.e., the inputs
and outputs of the circuit.
Signal names can contain any alpha-numeric characters and the underscore.
Data objects have types (we will consider this later, but in our example all signals are type
std_logic).
In our example, our 5 signals are declared inside of the Port of the Entity
Declaration.
ENTITY entity_name IS
PORT(
SIGNAL signal_name : mode type ;
SIGNAL signal_name : mode type ;
…
SIGNAL signal_name : mode type ) ;
END entity_name;
Entity Declarations have a name and a port. The port basically is where the inputs
and outputs of the circuit are listed.
We will worry about the different sections and possibilities as we need them.
Boolean Operators
AND, OR, NOT, XOR, NAND, NOR, etc...
Relational Operators
= (equality), /= (not equality), < (less than), > (greater than), etc…
Arithmetic Operators
+, -, &, etc.
E.g., all concurrent signal assignments operate in parallel, and all left-hand sides (new
values at time t+ t) get undated from the right-hand sides using the values at time t.
The mode can be 1 of 4 values and basically tells us the direction of the signal.
IN --
Data flows along the signal into the circuit.
OUT --
Data flows along the signal out of the circuit.
BUFFER --
Data flows along the signal out of the circuit, but is used internally inside of the
circuit.
INOUT --
Data flows along the signal both into and out of the circuit.
IN OUT
IN BUFFER
IN INOUT
IN
OUT
Consider real wires in a digital circuit. The logical values 0 and 1 are represented by
voltages, and are not sufficient:
What if a signal is not driven to a certain value because a wire is disconnected or
temporarily disconnected?
What if accidentally a signal is concurrently driven to both 0 and 1… What is its
correct value?
What if the initial value of a signal is not defined?
Since signals are implemented physically with wires, how can we represent the
strength of a signal?
In the early days of VHDL, different tool vendors had their own ways to represent the
above situations.
This (again) made it hard to share VHDL descriptions.
Note: from the perspective of synthesis, the 9-valued system is slightly different
than for simulation. E.g., when circuits are synthesized unknown or un-initialized
values do not have any meaning – no physical representation for such situations.
type std_ulogic is (
‘U’, -- Uninitialized
‘X’, -- Forcing Unknown
‘1’, -- Forcing 1
‘0’, -- Forcing 0
‘Z’, -- High impedance
‘W’, -- Weak Unknown
‘L’, -- Weak 0
‘H’, -- Weak 1
‘-’ -- Don’t care
);
This type is defined in the IEEE library in the 1164 package (more in a minute).
The IEEE 1164 Standard also defines the signal type std_logic. It has the same values
as std_ulogic, determined according to the following table (if multiple drivers).
The VHDL library IEEE; in our VHDL Descriptions simply identifies a library that we
wish to access.
The library name is a logical name and in practice usually just maps to a directory on
the computer in which various design units have been precompiled and stored.
The VHDL use ieee.std_logic_1164.all; means that we want to use the std_logic_1164
package which is stored inside the IEEE library.
The “.all” simply means that we want access to everything stored inside of the
package.
So, we always place the following VHDL prior to every entity declaration.
entity FullAdder is
port( a,b,c : in std_logic; z
s,z : out std_logic);
end FullAdder;
Ignoring the library and use statements (just put them at the top of the VHDL
description), we should be able to layout the entire VHDL Description.
library ieee;
use ieee.std_logic_1164.all;
entity SomeFunction is
port( a,b,c : in std_logic;
f : out std_logic);
end SomeFunction;