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20 Asynchronous State Minimization

The document discusses state minimization techniques for asynchronous circuits. It describes how states can be minimized by identifying don't care outputs and next state values. States are considered compatible if they produce the same outputs and have compatible next states for all input combinations. An implication chart is used to identify compatible states, which are then merged in a merger diagram to minimize the number of states. Care must be taken to ensure any implied compatibilities are valid when performing mergers.

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0% found this document useful (0 votes)
53 views14 pages

20 Asynchronous State Minimization

The document discusses state minimization techniques for asynchronous circuits. It describes how states can be minimized by identifying don't care outputs and next state values. States are considered compatible if they produce the same outputs and have compatible next states for all input combinations. An implication chart is used to identify compatible states, which are then merged in a merger diagram to minimize the number of states. Care must be taken to ensure any implied compatibilities are valid when performing mergers.

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Omnipotent yay
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We take content rights seriously. If you suspect this is your content, claim it here.
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State minimization in asynchronous circuits

 Similar to the minimization we did with synchronous sequential circuits.

 Lot’s of opportunity for state minimization in asynchronous flow tables:


 Lots of don’t care outputs for unstable states (since we won’t stay in this
situation too long).
 Don’t care next state information if we assume fundamental mode operation
(some transitions will not occur).

ECE124 Digital Circuits and Systems Page 1


Compatible states

 With don’t cares, equivalency is replaced with compatibility.

 Two states A and B are compatible if, for every input combination we find:

 A and B produce the same outputs where specified, AND

 A and B have compatible next states where specified.

 Don’t cares match with anything…

ECE124 Digital Circuits and Systems Page 2


Implication chart using compatible states (1)

 Consider the following flow table with some unspecified next states and outputs (two
inputs, one output, 6 states):

curr
inputs (DG) output
state
00 01 11 10 00 01 11 10
a c a b - - 0 - -
b - a b e - - 1 -
c c a - d 0 - - -
d c - b d - - - 0
e f - b e - - - 1
f f - - e 1 - - -

ECE124 Digital Circuits and Systems Page 3


Implication chart using compatible states (2)

 Build the implication chart (list states along left and bottom side – like lower triangle
of a matrix):

curr
state
inputs (DG) output b
00 01 11 10 00 01 11 10
c
a c a b - - 0 - -
b - a b e - - 1 - d
c c a - d 0 - - - e
d c - b d - - - 0
f
e f - b e - - - 1
f f - - e 1 - - - a b c d e

ECE124 Digital Circuits and Systems Page 4


Implication chart using compatible states (3)

 Mark states incompatible due to different outputs with “x”.

 Marking definitely compatible states with “v”.

 Marking possibly compatible states with implied decisions.

curr
state
inputs (DG) output b
00 01 11 10 00 01 11 10
c (d,e)
a c a b - - 0 - -
b - a b e - - 1 - d (d,e)

(c,f)
c c a - d 0 - - - e (c,f)
(d,e)
d c - b d - - - 0 (c,f)
f (c,f)
(d,e)
e f - b e - - - 1
f f - - e 1 - - - a b c d e

ECE124 Digital Circuits and Systems Page 5


Implication chart using compatible states (4)

 Scan columns again and again, checking implied decisions to remove compatibilities…

curr
state
inputs (DG) output b
00 01 11 10 00 01 11 10
c (d,e)
a c a b - - 0 - -
b - a b e - - 1 - d (d,e)

c c a - d 0 - - - (c,f)
e (c,f)
(d,e)
d c - b d - - - 0 (c,f)
f (c,f)
(d,e)
e f - b e - - - 1
f f - - e 1 - - - a b c d e

ECE124 Digital Circuits and Systems Page 6


Merger diagram with compatible states (1)

 Squares with any “x” are not compatible; those with all “v” are compatible (possibly
under implications).

 Draw the Merger Diagram:


a

f b

e c

ECE124 Digital Circuits and Systems Page 7


Merger diagram with compatible states (2)

 We now look for large cliques in the graph (clique is part of the graph in which every
node is connected to every other node)…

a
a

f b
f b

e c
e c

d
d

 We can now merge states (a,c,d) and (b,e,f). We have reduced 6 states down to 2
states by merging.

ECE124 Digital Circuits and Systems Page 8


Important!!!

 Reminders:
 We need to check that each state is included at least once.
 We need to make sure that any implied compatibilities are true…

 For our solution…


 (a,c,d) and (b,e,f) all states are included.
 Implied compatibilities are true. In particular, (a,c,d) and (b,e,f) requires no
implied compatibilities.

ECE124 Digital Circuits and Systems Page 9


Final result

 Our final result is:


curr curr
inputs (DG) output inputs (DG) output
state state
00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10
a c a b - - 0 - - a c a b b 0 0 - 0
b - a b e - - 1 - b b a b b 1 - 1 1
c c a - d 0 - - -
d c - b d - - - 0
e f - b e - - - 1
f f - - e 1 - - -

 Note that we still have some unspecified values in the flow table (which is no longer a
primitive flow table).

ECE124 Digital Circuits and Systems Page 10


Revisiting the merger diagram (1)

 Useful to illustrate an example where we need to be careful about mergings in the


Merger Diagram.

 Consider the following implication chart and its merger diagram:

b (b,c)

c (d,e)
b
d (b,c) (a,d) e
e (b,c)

a b c d

d c

ECE124 Digital Circuits and Systems Page 11


Revisiting the merger diagram (2)

 Say we consider the merging (a,b) and (c,d,e)…

 For (a,b), (d,e) we require that (b,c) get merged.


 For (c,d) we require that (a,d) get merged.

 The implied compatibilities do not hold given our selected merging, so our merging is
BAD (i.e., wrong). a

b (b,c)

c (d,e)
b
d (b,c) (a,d) e
e (b,c)

a b c d

d c

ECE124 Digital Circuits and Systems Page 12


Revisiting the merger diagram (3)

 Say we consider (a,d), (b,c), (c,d,e)…

 The implied compatibilities do hold given our selected merging, so our merging is
GOOD (i.e., right).

b (b,c)

c (d,e)
b
d (b,c) (a,d) e
e (b,c)

a b c d

d c

ECE124 Digital Circuits and Systems Page 13


Summary

 Given a flow table (or state table), we can always try to reduce the number of states
using an implication chart and a merger diagram.

 Both tables (the original table and the reduced table) will perform the same function.

 The idea is that having a smaller table will result in a simpler circuit.

ECE124 Digital Circuits and Systems Page 14

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