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Spread-Spectrum Clocking in Switching Regulators for EMI Reduction

Article  in  IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · February 2003

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IEICE TRANS. FUNDAMENTALS, VOL.E86–A, NO.2 FEBRUARY 2003
381

PAPER Special Section on Analog Circuit Techniques and Related Topics

Spread-Spectrum Clocking in Switching Regulators for

EMI Reduction
Takayuki DAIMON† , Hiroshi SADAMURA† , Takayuki SHINDOU† , Nonmembers,
Haruo KOBAYASHI†a) , Regular Member, Masashi KONO† , Nonmember,
Takao MYONO†† , Regular Member, Tatsuya SUZUKI†† , Shuhei KAWAI†† ,
and Takashi IIJIMA†† , Nonmembers

SUMMARY This paper describes a simple, inexpensive tech-

nique for intentionally broadening and flattening the spectrum
of a DC-DC converter (switching regulator) to reduce Electro-
Magnetic Interference (EMI). This noise spectrum broaden-
ing technique involves intentionally introducing pseudo-random
dithering of control clock timing, which can be achieved by
adding simple digital circuitry. This technique can significantly
reduce noise power spectrum peaks at the DC-DC converter out-
put. For our test case circuit, measurements showed that noise
power was reduced by 5.7 dBm at the main peak, by 15.6 dBm at
the second peak and by 12.8 dBm at the third peak. This sim-
Fig. 1 A switching regulator (buck converter) with a PWM
ple, inexpensive technique can be applied to most conventional
controller which sets the output voltage Vout to (1 + R2 /R1 )Vb .
switching regulators by adding simple digital circuitry, and with-
The minus input of the comparator is a ramp signal of a frequency
out any modification of the design of other parts.
fdata .
key words: switching regulator, DC-DC converter, spread spec-
trum, EMI, switching noise

1. Introduction

Switching regulators are widely used—particularly in

mobile equipment—as highly efficient DC-DC convert-
ers [1]. They consist of an input power supply Vdd ,
a power MOS switch, a choke coil (L), a capacitor
(C), a diode (D) and PWM control circuitry (Fig. 1).
To reduce the switching noise [2] that they generate,
however, requires complex noise filtering and shield-
ing which makes the switching power supply more Fig. 2 A buck converter core circuit. Vdd is an input voltage,
costly and larger in size. This paper presents a tech- M1 is an MOS switch, clk is a control clock and L, C consist of
nique for broadening and flattening their switching a low pass filter. The value of the output voltage Vout is lower
noise power spectrum to reduce Electro-Magnetic In- than the input voltage Vdd and is controlled by the duty of clk.
terference (EMI) and to satisfy EMI regulations [3].
This technique involves pseudo-random dithering of the
switching regulator control clock timing, and such clock
2. Switching Regulator
jitter can be introduced by adding simple digital cir-
cuitry. This technique can significantly reduce noise
Figure 2 shows a voltage buck converter which consists
power spectrum peaks at the DC-DC converter output.
of an input power supply Vdd , a power MOS switch,
a diode (D), and a LC low-pass filter consisting of a
choke coil (L) and capacitor (C) to smooth the output
voltage Vout . Then we have
Manuscript received June 20, 2002. Ton
Manuscript revised August 28, 2002. Vout ≈ Vdd , (1)
Final manuscript received October 23, 2002. Ton + Toff
†
The authors are with the Department of Electronic where Ton is the switch ON time interval, and Toff is
Engineering, Faculty of Engineering, Gunma University,
Kiryu-shi, 376-8515 Japan. the switch OFF time interval. Since the output volt-
††
The authors are with Semiconductor Company, Sanyo age is controlled by quickly turning the MOS switch
Electric Co., Ltd., Gunma-ken, 370-0596 Japan. on and off, high efficiency can be achieved. However,
a) E-mail: k [email protected] the choke coil L of the switching regulator generates
 IEICE TRANS. FUNDAMENTALS, VOL.E86–A, NO.2 FEBRUARY 2003
382

Fig. 5 Clock waveforms of conventional and proposed switch-

ing regulators. In the conventional one, the clock rising timing
interval is constant, while in the proposed one it fluctuates in a
pseudo random manner.

Fig. 3 Clock and output voltage waveforms (Vclk and Vout re-
spectively ) of a conventional switching regulator. We see that
the output voltage Vout suffers from the switching noise at the
rising and falling timings of Vclk .

Fig. 6 Output voltage power spectrum of conventional and

proposed switching regulators. The output power spectrum of
the conventional one has peaks which may violate EMI regula-
tions while the one of our proposed method spreads the noise
peak power spectrum which helps to satisfy EMI regulations.

Fig. 4 Measured output power spectrum of a conventional

switching regulator. We see that it has peaks at the multiples of
the fundamental frequency.

V = L(dI/dt) voltage transients (Fig. 3) when the

switch turns on and off, so the switching noise power
spectrum peaks are at multiples of the switching clock
frequency (Fig. 4). As the switching frequency is in- Fig. 7 Circuit implementation of the PRM when the number
creased (to reduce the size of choke coil and capacitor) N of the M-sequence flip-flops is 3. The signal indicated by fdata
and the size of portable equipment is reduced, this tran- is from the PWM controller output and the one indicated by
sient noise becomes more troublesome, and it becomes “fclk ” is clock signal to produce the delayed signals of the “PRM
Input” signal. The signal “PRM Output” goes to the switching
more difficult to satisfy EMI regulations [3] without
regulator MOS gate, and the signal “reset” initializes the M-
costly and bulky shielding. sequence circuit.

3. Proposed EMI Reduction Technique

(However note that this technique does not reduce the
3.1 Principle total power of the switching noise.) This technique in-
volves adding simple digital circuitry (Fig. 7), without
We propose a digital Pseudo Random Modulation any design modification of other parts. Usually clock
(PRM) technique to alleviate the above-described jitter gives negative impacts to analog circuits [4], [5],
switching noise problem. This technique involves phase but this technique utilizes it positively.
modulation (dithering) of the switching regulator con- This proposed technique can be considered as the
trol clock (Fig. 5) and spreads the noise power spec- application of “Spread Spectrum Clocking (SSC)” (for
trum in the frequency domain to reduce EMI (Fig. 6). synchronous digital circuits) [6]–[8] to switching reg-
DAIMON et al.: SPREAD-SPECTRUM CLOCKING IN SWITCHING REGULATORS FOR EMI REDUCTION
383

ulators. However—because the switching clock fre- fdata (which is the same clock as the one used in the
quency is just a few Megahertz—our PRM technique PWM controller) to produce a pseudo-random signal
can use digital modulation, whereas the SSC technique SEL1, SEL2, ..., SEL(N ). The shift-register is driven
has to use analog modulation because the clock fre- by the clock fclk to delay the PWM controller output by
quency is very high (more than several hundred Mega- n/fclk , where n = 1, 2, 3, ..., 2N − 1; the delay Ti of the
hertz). Note that it is easy to implement digital modu- i-th flip-flop output IN (i) is i/fclk . The data inputs
lation circuitry that is little affected by CMOS process of the multiplexer are IN 1, IN 2, IN 3, ..., IN (2N − 1),
variations, operating temperature variations, and ag- and its selector inputs are SEL1, SEL2, ..., SEL(N ).
ing. The multiplexer output drives the gate of the MOS-
We note that the following merits are expected by FET switch. For example, when IN 2 is selected as the
spreading the noise spectrum in the switching regulator multiplexer output, the switch is driven by the PWM
using the proposed method: output with 2/fclk delay. Since the selection is done
in a pseudo-random order, the multiplexer output is a
• The EMI level in the low frequency range (be-
PWM signal with pseudo-random phase modulation.
low several-hundred-kilo-hertz) measured espe-
If fclk is much lower than 2N fdata , the output rip-
cially with a “quasi-peak detection method ” as well
ple of the switching regulator becomes very large. On
as with an “average detection method ” [3], [9] can
the other hand, if fclk is much higher than 2N fdata ,
be reduced.
then switching noise is not sufficiently spread in the fre-
• Filter requirements for smoothing out the switch-
quency domain. From simulations and measurements,
ing noise spectrum below a certain level can be re-
we have found that the following value of the shift reg-
laxed because the noise peak spectrum is reduced
ister clock frequency fclk is the best compromise:
by the proposed method.
• The proposed method can provide several positive fclk ≈ 2N fdata . (2)
effects in electromagnetic environments, e.g., the
interference of the switching noise to AM radios Equation (2) can be also interpreted as follows: when
the maximum delay of the multiplexer output from the
can be reduced.
PWM output equals the clock period (1/fdata ) of the
PWM controller, the noise spectrum is spread widely
3.2 Circuit Implementation and output ripple is small.
In order to determine the number N of the M-
Figures 7 and 8 show circuit implementation and tim- sequence flip-flops, we have changed it and measured
ing chart for the PRM (Pseudo Random Modulation) the maximum noise peak reduction. Then we have
technique; it consists of an N -bit M-sequence genera- found that the best choice is N =5; this is because as N
tor, a 2N -bit shift-register and a (2N − 1)-to-1 multi- increases from 1 to 5 (one by one), the maximum noise
plexer. The M-sequence generator is driven by the clock power reduces significantly, but the reduction is almost
the same between the cases for N = 5 and N = 6. On
the other hand, as N increases, the PRM hardware as
well as the shift register clock frequency fclk have to
increase.
The shift register control clock fclk and the PWM
clock fdata may be generated by a single oscillator and
dividers.

4. Experimental Results

We have implemented the PRM circuit with an FPGA

(ALTERA FLEX10K30EQC208-3), and applied it to
a voltage buck converter (Fig. 9) and its experiment
conditions are shown in Table 1.
Then we have compared the cases with and without
the PRM circuit. Figure 10 shows the measured output
power spectrum of a switching regulator without the
PRM circuit, while Fig. 11 shows the spectrum with the
Fig. 8 Timing chart of the PRM circuit in Fig. 7. “Shift Reg- PRM circuit. We see that the fundamental-frequency
ister Control Clock” at the top corresponds to “fclk ” signal in
Fig. 7 while “PRM input” signal corresponds to “fdata ” signal
noise peak is reduced by 5.7 dBm, the second harmonic
in Fig. 7. Also “SEL” signal corresponds to SEL1, SEL2, SEL3 noise peak is reduced by 15.6 dBm, the third harmonic
signals in Fig. 7 and “PRM output” corresponds to “OUTPUT” peak by 12.8 dBm, and as a whole, the maximum noise
signal in Fig. 7. peak is reduced by 12.3 dBm. We see that the noise
 IEICE TRANS. FUNDAMENTALS, VOL.E86–A, NO.2 FEBRUARY 2003
384

Fig. 9 Measurement setup of a buck converter system with the

Fig. 11 Measured output power spectrum of the switching reg-
PRM circuit. A 5-bit M-sequence generator and a 32-bit shift
ulator with the PRM. We see that the noise power peaks are
register are used in the PRM circuit. A PC controls an Altera
reduced compared to the ones in Fig. 10.
FPGA board and a spectrum analyzer measures the switching
regulator output.

Table 1 Experiment conditions of the PRM circuit.

Shift register clock frequency fclk 6 MHz
PWM clock frequency fdata 187 kHz
Number N of M-sequence flip-flops 5
Supply voltage 3.3 V

Fig. 12 Measured output voltages of a buck converter with and

without the PRM with respect to the clock duty. The line of
“Normal” indicates the output voltage without the PRM while
the line of “PRM (Proposed)” indicates the one with the PRM.
We see that in both cases the output voltages are almost the
same and hence adding the PRM circuitry does not affect the
output voltage. Note that the line of “IDEAL” shows the output
voltage calculated using Eq. (1).

Fig. 10 Measured output power spectrum of the switching

regulator without the PRM.

power spectrum peaks are significantly reduced. Fig-

ure 12 show the measured output voltage the switch-
ing regulator with and without the PRM, while Fig. 13
shows the measured output efficiency of the switch-
ing regulator with and without the PRM. (The power
consumption of the PRM circuit as well as the PWM
controller is not taken into account here because it is
small CMOS digital hardware and its power consump-
tion is negligible when implemented as a fraction of
digital VLSI chip.) We see that the addition of the Fig. 13 Measured efficiencies of a buck converter with and
PRM does not significantly affect the output voltage without the PRM. The power consumption of the PRM circuit
and efficiency. We note that additional measurement as well as the PWM controller is not taken into account here.
DAIMON et al.: SPREAD-SPECTRUM CLOCKING IN SWITCHING REGULATORS FOR EMI REDUCTION
385

results using a standard EMI measurement system in Takahashi, K. Enomoto, and H. Kogure, “Sampling jitter
an electro-magnetic shield room (anechoic chamber) are and finite aperture time effects in wideband data acquisi-
reported in [10]. tion systems,” IEICE Trans. Fundamentals, vol.E85-A, no.2,
pp.335–346, Feb. 2002.
[5] N. Kurosawa, H. Kobayashi, H. Kogure, T. Komuro, and H.
5. Concluding Remarks Sakayori, “Sampling clock jitter effects in digital-to-analog
converters,” Measurement, vol.31, no.3, pp.187–199, March
We have proposed a spread-spectrum clocking tech- 2002.
[6] C.D. Hoekstra, “Frequency modulation of system clocks
nique for switching regulators involving digital pseudo-
for EMI reduction,” Hewlett-Packard Journal, Article 13,
random modulation of the switch control clock. Its ef- pp.101–107, Aug. 1997.
fectiveness has been demonstrated by prototype imple- [7] H.-S. Li, Y.-C. Cheng, and D. Puar, “Dual-loop spread
mentation and its measurements, and it has the follow- spectrum clock generator,” ISSCC Digest of Tech. Papers,
ing advantages: pp.184–185, Feb. 1999.
(i) Small hardware requirement, low cost, low [8] Y. Moon, D.-K. Jeong, and G. Kim, “Clock dithering for elec-
tromagnetic compliance using spread spectrum phase mod-
power: The proposed technique can be imple- ulation,” ISSCC Digest of Tech. Papers, pp.186–187, Feb.
mented simply by adding a small low-cost, low-power- 1999.
consumption digital circuit. [9] C.R. Paul, Introduction to Electromagnetic Compatibility,
(ii) Universality: This technique can be applied to Mimatsu Data System, 1996.
almost all types of switching regulator (e.g. not only [10] H. Sadamura, M. Namekata, M. Kono, H. Kobayashi, and
N. Ishikawa, “EMI reduction and measurement techniques of
voltage buck converters but also voltage boost convert-
switching regulators,” IEEJ Technical Meetings of Electronic
ers). Circuits, ECT-02-117, Tokyo, Dec. 2002.
(iii) Compatibility: There is no need to modify con-
ventional switching regulator circuit design; simply add
a small digital circuit. Also the proposed technique can
be employed together with other conventional noise re-
duction techniques.
(iv) Stability: Since digital modulation is used, this
is virtually unaffected by temperature variations, aging Takayuki Daimon received the
or CMOS process variations. B.S. degree in electronic engineering from
Shibaura Institute of Technology in 1999
(v) Flexibility: Since digital modulation is used, not
and the M.S. degree in electronic engi-
only pseudo-random phase modulation but also other neering from Gunma University in 2002,
types of modulation (such as frequency modulation) where he was involved in research for
can readily be implemented. design, analysis and measurements of
switching regulator circuits as well as vari-
ous analog CMOS and Bipolar circuits. In
Acknowledgement
2002, he joined Asahi Kasei Microsystem
Co. Ltd., where he is engaged in analog
We would like to thank T. Arai, M. Kawakami and K. integrated circuit design.
Tanaka for their kind support of this project. Thanks
are also due to M. Namekata, Y. Yuminaka, Y. Hosaka
and K. Wilkinson for valuable discussions. A part of Hiroshi Sadamura received the
this work was performed at Gunma University Satellite B.S. degree in electronic engineering from
Venture Business Laboratory. Gunma University in 2001, and he is cur-
rently a graduate student in M.S. course
there. He has been involved in design,
References
analysis and measurements of switching
regulator circuits including their EMI
[1] A.J. Stratakos, C.R. Sullivan, S.R. Sanders, and R.W. measurements.
Broderson, “High-efficiency low-voltage DC-DC conversion
for portable applications,” in Low-Voltage/Low-Power Inte-
grated Circuits and Systems, Chapter 12, IEEE Press, 1999.
[2] S. Sakiyama, J. Kajiwara, M. Kinoshita, K. Satomi, K.
Ohtani, and A. Matsuzawa, “An on-chip high-efficiency and
Takayuki Shindou received the
low-noise DC/DC converter using divided switches with
B.S. degree in electronic engineering from
current control technique,” ISSCC Digest of Tech. Papers,
Gunma University in 2002, where he was
pp.156–157, Feb. 1999.
involved in research for design, analysis
[3] International Special Committee on Radio Interference,
and measurements of switching regulator
CISPR16-I: Specification for Radio Disturbance and Immu-
circuits. In 2002, he joined Sanyo LSI De-
nity Measuring Apparatus and Methods, Part 1, Interna-
sign System Soft Co. Ltd., where he is en-
tional Electro-technical Commission, First edition, Geneva,
gaged in analog integrated circuit design.
Switzerland, 1993.
[4] H. Kobayashi, K. Kobayashi, M. Morimura, Y. Onaya, Y.
 IEICE TRANS. FUNDAMENTALS, VOL.E86–A, NO.2 FEBRUARY 2003
386

Shuhei Kawai received the B.S. de-

Haruo Kobayashi received the B.S.
gree in electrical engineering from Sci-
and M.S. degrees in information physics
ence University of Tokyo, Tokyo, Japan
from University of Tokyo in 1980 and 1982
in 1998. In 1998, he joined Sanyo Elec-
respectively, the M.S. degree in electri-
tric Corporation, Semiconductor Com-
cal engineering from University of Califor-
pany, Gunma, Japan. Since 1998, he
nia at Los Angeles (UCLA) in 1989, and
has been working on the development of
the Dr. Eng. degree in electrical engineer-
power resources circuit.
ing from Waseda University in 1995. He
joined Yokogawa Electric Corp. Tokyo,
Japan in 1982, where he was engaged in
the research and development related to
measuring instruments and mini-supercomputers. From 1994 to
1997, he was involved in research and development of ultra-high- Takashi Iijima graduated from Tokyo
speed ADCs/DACs at Teratec Corp. In 1997 he joined Gunma Industry technical junior college in 1992.
University and presently is a Professor in Electronic Engineering In 1992 he joined Sanyo Electric Corpo-
Department there. He was also an adjunct lecturer at Waseda ration, Semiconductor Company, Gunma,
University from 1994 to 1997. His research interests include ana- Japan. He is now working on the analog
log & digital integrated circuits design and signal processing al- circuit design.
gorithms. He is a recipient of the 1994 Best Paper Award from
the Japanese Neural Network Society.

Masashi Kono is an undergradu-

ate student in electronic engineering de-
partment at Gunma University, and is ex-
pected to receive the B.S. degree in March
2003. He has been involved in design,
analysis and measurements of switching
regulator circuits including their EMI
measurements for his B.S. thesis.

Takao Myono graduated from Ku-

magaya Technical High School in 1964,
In 1964 he joined Sanyo Electric Corpo-
ration, Semiconductor Company, Gunma,
Japan. From 1965 to 1968 he studied
at Ibaraki University, Japan, and ob-
tained Ph.D. degree in electronic engi-
neering from Gunma University in 2002.
From 1968 to 1976 he was engaged in the
design of PMOS and CMOS logic LSIs,
and from1976 to 1995 he was involved in
the development of CAD systems. Currently he is Senior Man-
ager of Semiconductor Division, Sanyo Electric Co., Ltd. His
research interests include analog circuits design and device mod-
eling.

Tatsuya Suzuki received the B.S. de-

gree in electronics from Nihon University
College of Science and Technology, To-
kyo, Japan in 1986. In 1986, he joined
Fuji Heavy Industries Ltd. (SUBARU),
Automobile Division, Gunma, Japan. In
1991, he joined Sanyo Electric Corpora-
tion, Semiconductor Company, Gunma,
Japan. Since 1991, he has been working
on the development of analog MOS cir-
cuits.

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