TESTING OF VLSI CIRCUITS

Sequential Circuit Test Generation

Vinay Reddy
Department of Electronics & Communication Engineering
TESTING OF VLSI CIRCUITS

Unit 3 : Sequential Circuit Test

Generation

Vinay Reddy
Department of Electronics and Communication Engineering
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Syllabus
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Unit 3 - Part 1
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Sequential circuits contain combinational logic and flip-flops.

Their testing is more complex than that of the

combinational logic, for two reasons:
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Internal memory states:

The circuit contains internal memory whose state is not known at the beginning
of the test.

The test must, therefore, initialize the circuit to a known state.

Long test sequences:

A test for a fault in sequential logic essentially contains three parts:

(a) initialization of the internal memory,

(b) a combinational test to activate the fault and bring its effects to the boundary of the
combinational logic, and
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Model of a Synchronous Sequential Circuit

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Assumptions
We consider synchronous sequential circuits

- All memory elements are under the control of a clock signal

- Vectors at the PI are synchronized with the clock.

A new vector is applied just after the active edge of the clock
Outputs reach their steady state values just before the before the
next active edge of the clock

- Signal propagation time through the combinational logic does not exceed the clock period
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

A Simplified Model
The combinational part is modeled at the gate level
- All single stuck-at-faults are considered in it.

Flip-flops are treated as ideal memory elements.

- Clock signal is not explicitly represented and no faults in the clock signals are modeled.
- Internal faults in the flip-flops are not modeled.
- Input/output faults on flip-flops are modeled as faults on output and input signals of the
combinational logic.
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Sequential Circuit Testing Numerical 1

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Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
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Sequential Circuit Test Generation
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Sequential Circuit Test Generation
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Sequential Circuit Test Generation

Sequential Circuit Testing Numerical 2

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Sequential Circuit Test Generation
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Sequential Circuit Test Generation
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Sequential Circuit Test Generation
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Sequential Circuit Test Generation

Sequential Circuit Testing Numerical 3

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Unit 3 - Part 2
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

A Simplified Model
Test Generation Methods

• Can be classified into two categories:

1. Time frame expansion

• A model of the circuit is created such that tests can be generated by a

combinational ATPG tool.
• Efficient for circuits described at the gate level.
• Efficiency degrades significantly with cyclic structure, multiple-clocks, or
asynchronous logic.
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

A Simplified Model

2. Simulation-based methods

• A fault simulator and a test vector generator are used to derive tests.

• Circuits modeled at other levels (RTL, transistor, etc.) can be treated.

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Numerical to prove Nine Valued Algebra

is necessary for Sequential Circuit Testing

Numerical 4
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Figure 8.5(b) is a two time-frame construction of the

Time-Frame Expansion Method test generation process with the five-valued logic,
showing that the fault cannot be detected.

Figure 8.5(c) repeats the process with the nine-value

system and finds that an input A = 0 after the
application of one clock detects the fault at B as 0/1.

Most implementations of sequential

circuit test generators use the nine-
valued system.
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Unit 3 - Part 3
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Numerical on Time Frame Expansion

Method

Numerical 5

A serial Adder Circuit

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

To apply the combinational

ATPG procedures we can thus
“unroll” the sequential circuit
into a larger combinational
circuit. This unrolling is called
“timeframe expansion.”
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

To apply the combinational

ATPG procedures we can thus
“unroll” the sequential circuit
into a larger combinational
circuit. This unrolling is called
“timeframe expansion.”
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

To apply the combinational

ATPG procedures we can thus
“unroll” the sequential circuit
into a larger combinational
circuit. This unrolling is called
“timeframe expansion.”
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

The sequential circuit test is an initialization vector 11 followed by another

11 vector that produces a D at the output.

Notice that the fault is activated in both time-frames, although that is not
always necessary.

For example, another test 00 followed by 11 (had we used the alternative

choice of Cn) activates the fault only in time-frame 0.
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

1. Replace all the flip – flops by nets.

2. Perform D algorithm on the virtual combinational circuit and find the

values of primary and secondary inputs.

3. Using multiple steps apply the required signals.

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Numerical on Time Frame Expansion

Method

Numerical 6
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

The sequence is a = 0,1,1 to test the stuck at 1 fault in the circuit

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Time-Frame Expansion Method

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Unit 3 - Part 4
 The state of a flip-flop Fi is considered dependent on another
TESTING OF VLSI CIRCUITS flip-flop Fj if there exists a combinational path from Fj to Fi.
Such dependence can be expressed by a directed graph, usually
Sequential Circuit Test Generation
called the s-graph
Time-Frame Expansion Method

This is a cycle-free circuit since there is no feedback among flip-flops.

 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method
We define the sequential
depth, of the circuit as the
maximum level number.

In the s-graph, the node with 0 in-degree corresponds to a flip-flop whose state depends exclusively on primary
inputs.

There can be more than one such vertices.

We will levelize the s-graph by assigning a level number 1 to all 0 in-degree vertices.

The rest of the graph is then levelized such that the level number of a vertex is one greater than the maximum
level feeding into it.
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

An example of a Cyclic Circuit

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

Reference: Pg 226 from the text book

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

Reference: Pg 227 from the text book

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Numerical on Time Frame Expansion

Method

Numerical 7
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

For the sequential circuit given below –

a. Identify if it is a cyclic or a cycle free circuit
b. Give the test vectors for input A of C stuck-at-0
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

A=1
Time frame 1

B=0
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

A=1
After Time frame 1

B=0

Was sensitizing the fault necessary in time frame 1 ?

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

A=X
After Time frame 1

Was sensitizing the fault necessary in time frame 1 ?

B=0
Even if we don’t sensitize the fault its fine
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

A=X
Time frame 1

B=0
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

1
A=1
Time frame 2
1/0
1/0 0
1
0 1

B=0

0 1
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

1
A=1
Time frame 2
1/0
1/0 0
1
0 1

B=0

0 1 Is this sufficient in TF2 ?

TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

1
A=1
Time frame 2
1/0
1/0 0
1
0 1

B=1
Is this sufficient in TF2 ?
0 1
We have to make B = 1
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

1
A=1
Time frame 3
1/0
1 0
1
1 1/0 0/1

B=1
1
1 0/1
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

1
A=1
After Time frame 3
1/0
1 0
1
1 1 0

B=1
0/1
1 0
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method

1
A=1
Time frame 4
1/0
1 0
0/1
1 1 0

B=X
0/1 Fault is propagated successfully
1 0
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Time-Frame Expansion Method
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Cyclic Circuit
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Cyclic Circuit

When CNT = 1, it
increments its state
(FF2,FF1), every time the
flip-flops are clocked.

For CNT = 0, the circuit holds

its state.
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Cyclic Circuit

When CNT = 1, it
increments its state
(FF2,FF1), every time the
flip-flops are clocked.
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Cyclic Circuit
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Cyclic Circuit
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Cyclic Circuit
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
Cyclic Circuit it can be detected prior to initialization if the circuit powers-up
in the 11 state Notice that this is not a valid state in this
implementation of the modulo-3 counter.
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Cyclic Circuit - Summary

Even though a cyclic circuit can be made initializable by adding hardware, some
faults in the added circuitry can only be potentially tested. Those are the faults that
interfere with the initialization process.

Not all cyclic circuits are uninitializable.

 THANK YOU

Vinay Reddy
Department of Electronics & Communication Engineering
[email protected]
+91 9945730244
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Vinay Reddy
Department of Electronics & Communication Engineering
TESTING OF VLSI CIRCUITS

Unit 3 : Sequential Circuit Test

Generation

Vinay Reddy
Department of Electronics and Communication Engineering
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Syllabus
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

Simulation Based Sequential ATPG Algorithms:

1. CONTEST Algorithm

2. Genetic Algorithm
 TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation

CONTEST Algorithm

Phase 1 : Initialization Phase

Phase 2 : Concurrent Fault Detection Phase
Phase 3 : Single Fault Detection Phase
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
TESTING OF VLSI CIRCUITS
Sequential Circuit Test Generation
 THANK YOU

Vinay Reddy
Department of Electronics & Communication Engineering
[email protected]
+91 9945730244