Block Diagram

6. Block Diagram

SPGPe

CPU DATA BUS

Sys Addr BUS

Sys Data BUS

Sys Cntl BUS

CPU Addr BUS
OSC. (KS32C61100) FONT ROM DATA ROM SIMM Post Script 3
PROGRAM ROM
20M Hz PLL
(MASK ROM) (DRAM) (Up to 64MB) (Flash : 2MB
(FLASHMEMORY)
ARM 7TDM I 512K*16b*2EA 1M*16b*2EA (Option) Font : 2MB)
Cache 8 KB 512K*16b*2EA
POWER (Option)
Reset & W D T
ON RESET Generation

/CS,/RD ,/W R
CPU DATA BUS
CPU ADDR. BUS
A/D Bu s
ROM/SRAM/
RCS
FLASH ROM
RD Control SYSTEM DATA BUS
WR (4 Bank)
SYSTEM ADDR. BUS

MA
IOCS I/O CPU B u s EDO / FPM
MD
Control In te rf ace DRAM
(5 Bank) Control RAS
Blo ck (4Bank) CAS

G PIO
GEU NETWORK
INTERFACE PANEL INTERCACE
(Option)
Interrupt MOTOR CONTROL
Control
(4 External) PVC
S yste rm Bu s NV RAM INTERCACE
I nt erfa ce
B loc k
Timer [A rbite r] I /O SENSORS INPUT
(3 CH) INTERFACE
PPI
SOLENOID CONTROL
Tone
Generator 74HC245*2EA FAN/PTL CONTROL
PARALLEL
UA RT 74LS273*3EA LSU INTERFACE
( 3 CH) DMAC INTERFACE
OSC.(Video) (2 CH)
VIS
53.0109277MHz HVPS CONTROL
USB
OSC. USB
INTERFACE IC FUSER CONTROL
48 MHz INTERFACE
Engine JB IG HCT (USBN9602)
Comm. I/F
SCF INTERFACE

LR AM :1296B
RAM : 512B C XRAM :256B

HPVC
Laser Diode Vcc
AD C
on LSU
RAM
[ LASER DIODE ON/OFF SWITCH ]
512B + 512B

SUPPLY 24V to
SUPPLY 5V to each ICS Motor/HVPS/FAN/LSUA
THERM STOR
ADC INPUT

THV READ 5V
ADC INPUT
SMPS 24V 24VS
[ COVER OPEN SWITCH ]

6-1