Handout #17

EE362A
Fall 2015

EE362A Semiconductor Devices

Lecture 16 - MOSFET

Hyunjoo Jenny Lee

Assistant Professor
School of Electrical Engineering
Korea Advanced Institute of Science and Technology (KAIST)

*Figures that are not annotated with reference are from the education package distributed by the distributor of Neamen textbook.
 Current-Voltage Relationship – Concepts (1)

§  What happens with large VDS?

§  (a)

H. J. Lee | EE | KAIST EE362A | Fall 2015 2

 Current-Voltage Relationship – Concepts (2)

§  What happens with large VDS?

§  (b) Getting narrower as VDS increases
(VGS-VDS decreases near drain)

H. J. Lee | EE | KAIST EE362A | Fall 2015 3

 Current-Voltage Relationship – Concepts (3)

§  What happens with large VDS?

§  (c)
slope = 0, gd=0

“pinch-off”

VGS-VDS(sat) = VT
(just the inversion point at the drain
à the induced inversion charge density is zero at the drain)

H. J. Lee | EE | KAIST EE362A | Fall 2015 4

 Current-Voltage Relationship – Concepts (4)

§  What happens with large VDS?

If ΔL << L, ID is constant in the
§  (d) saturation region (VDS > VDS(sat))

Electron enter at the source à travel through

the channel toward the drain à being injected
into the space charge region à swept by the
E-field to the drain

H. J. Lee | EE | KAIST EE362A | Fall 2015 5

 Current-Voltage Relationship – Concepts (5)

§  n-channel enhancement-mode MOSFET (NMOS)

I D ∝ (VGS −VT )2

increase VGS

H. J. Lee | EE | KAIST EE362A | Fall 2015 6

 Current-Voltage Relationship – Concepts (6)

§  Quick look at the equation before derivation:

Non-saturation Saturation

W µ nCox
ID = [2(VGS −VT )VDS −V 2DS ] VDS = V GS −VT
2L

k 'n W k 'n W
ID = [2(VGS −VT )VDS −V 2DS ] ID = (VGS −VT )2
2 L 2 L

k 'n = µ nCox W/L design parameter

Process conduction parameter

(For a given technology, constant)

H. J. Lee | EE | KAIST EE362A | Fall 2015 7

 Today’s Lecture

§  Objective:
–  Mathematical derivation of I-V characteristics
–  Frequency responses
–  CMOS technology

§  Readings:
–  Chapter 10.3 – 10.5

H. J. Lee | EE | KAIST EE362A | Fall 2015 8

 Mathematical Derivation (1)

§  MOSFET structure:

H. J. Lee | EE | KAIST EE362A | Fall 2015 9

 Mathematical Derivation (2)

§  Assumptions:

1. The current in the channel is due to drift rather than diffusion.

2. No current through the gate oxide

3. “gradual channel approximation” ! !

∂E y ∂E x
>>
(Ex is essentially a constant) ∂y ∂x

µ Ex is created by VDS
4. Mobility, , is constant in the channel.

H. J. Lee | EE | KAIST EE362A | Fall 2015 10

 Mathematical Derivation (3)

§  (1) Start with Ohm’s Law:

By Ohm’s law: J x = σ ⋅ Ε x σ = qµ n n(y)

Electron concentration in the
Channel Conductivity inversion layer

§  The total channel current at x is

Channel width
Ix = ∫ ∫J x dy dz
y z
I x = −W µ nQn ' E x
Qn ' = − ∫ qn(y)dy
Actually independent of x under
our assumptions
Qinv Inversion charge per unit area

§  (2) Need to find Q’n

H. J. Lee | EE | KAIST EE362A | Fall 2015 11

 Mathematical Derivation (4)

§  Two concepts are used to compute total charge:

–  charge neutrality & Gauss’s law
§  1. Charge neutrality:

VGS > VT

Q'm + Q'ss + Q'n + Q'sd (max) = 0

negative

H. J. Lee | EE | KAIST EE362A | Fall 2015 12

 Mathematical Derivation (5)

§  In order to find out Q’n, we use 2. Gauss’s law

!
"∫ ε En dS = QT
S

Outward directed normal total charge enclosed by

component to the S the surface, S

Fixed oxide charges Q’ss

Inversion layer charge Q’n

Depletion layer charge Q’SD(max)

Since there is no Ez, the two x, y,

planes do not contribute to the integral

H. J. Lee | EE | KAIST EE362A | Fall 2015 13

 Mathematical Derivation (6)

§  Surface 1 & 2:

1 2 Ex is a constant through x
Ex E x+Δx

!
§  Surface 3: neutral region = E = 0 E-field

§  Surface 4: the only surface contributes to the integral

! !
"∫ ε En dS = −εox Ε oxWdx = QT
S !
Inward direction of Eox −εox Ε ox = Q'ss + Q'n + Q'SD(max)

QT = [Q'ss + Q'n + Q'SD(max) ]Wdx

Now, we need to find this

H. J. Lee | EE | KAIST EE362A | Fall 2015 14

 Mathematical Derivation (7)

§  (3) Find Eox

(A) VGS −Vx ≠ Vox ! V
(B) Eox = ox
= Vox + 2φ fp + φ ms tox

VG in the previous
discussion (Eq. 10.21)

!
(C) ∴−ε E = − ε ox [(V −V ) − (φ + 2φ )]
ox ox GS x fp
Vx: potential across the
ms
tox
channel due to VDS
= Q'ss + Q'n + Q'SD(max)
§  (4) Thus, going back to current equation ….

I x = −W µ nQ'n E x Q'n = −Cox [(VGS −Vx ) −VT ]

dVx inversion charge
= −W µ nCox [(VGS −Vx ) −VT ]
dx

H. J. Lee | EE | KAIST EE362A | Fall 2015 15

 Mathematical Derivation (8)

§  Derive current at drain:

L Vx(L )

∫I x = −W µ nCox ∫ [(VGS −Vx ) −VT ]dVx

0 Vx(0)

§  Letting I D = −I x (Actually, independent of x)

VGS ≥ VT ,
W µ nCox 2
Valid when
IDL = [2(VGS −VT )VDS −VDS]
2 0 ≤ VDS ≤ VDS(SAT )

kn ' W 2 2
ID = [2(VGS −VT )VDS −VDS] = kn [2(VGS −VT )VDS −VDS]
2 L

kn' : the process conduction parameter

kn : the conduction parameter

H. J. Lee | EE | KAIST EE362A | Fall 2015 16

 Mathematical Derivation (10)

§  Complete the I-V curve for larger VDS

kn ' W 2
§  Plotting I D = [2(VGS −VT )VDS −VDS]
2 L
Saturates (why?)

H. J. Lee | EE | KAIST EE362A | Fall 2015 17

 Mathematical Derivation (11)

∂I D
§  Find the peak current by solving =0
∂VDS

§  Maximum when VDS = VGS −VT

Name this VDS(SAT )

§  Current at maximum (or at saturation) is ….

W µ nCox
I D(SAT ) = (VGS −VT )2
2L
kn' W pmos ßà nmos
= (VGS −VT )2
2 L 3µ p ≅ µ n
Design parameter
PMOS has 3x W then NMOS

H. J. Lee | EE | KAIST EE362A | Fall 2015 18

 Mathematical Derivation (12)

L Vx(L )
kn ' W
§  Exercise 1: Solve ∫ I x = −W µnCox ∫ [(VGS −Vx ) −VT ]dVx to derive I D = 2 L
2
[2(VGS −VT )VDS −VDS]
0 Vx(0)

§  Exercise 2: Derive VDS(SAT) and IDS(SAT)

H. J. Lee | EE | KAIST EE362A | Fall 2015 19

 Mathematical Derivation (13)

§  Use I-V relation to experimentally determine mobility and threshold voltage

§  If VDS is very small (~0.1V), V2DS can be ignored. Then,

W µ nCox
ID = (VGS −VT )VDS
L
§  For a fixed VDS,

µ is a function of VGS
(next chapter)

1. mobility:
Subthreshold µCoxWVDS
conduction Slope = ⇒ µ can be derived
L
(next chapter)

H. J. Lee | EE | KAIST EE362A | Fall 2015 20

 Mathematical Derivation (11)

§  If the device is in the saturation region,

W µ nCox
I D(sat ) = (VGS −VT )
2L

2. Threshold voltage

H. J. Lee | EE | KAIST EE362A | Fall 2015 21

 Transconductance (1)

§  Transconductance: change of ID with respect to change in VGS

∂I D
gm = “transistor gain”
∂VGS

W µ nCox (ideally independent of VG

§  (1) non-saturation region: g = VDS
mL
L à actually not)

VDS: small
gm

gm(max) gm ↓ as µ ↓
subthreshold

VGS
VT
H. J. Lee | EE | KAIST EE362A | Fall 2015 22
 Transconductance (2)

§  (2) saturation region:

∂I D(SAT ) W µ nCox
gms = = (VGS −VT ) Independent of VDS and
∂VGS L linear to VGS

§  Overall, size of transistor (W and L) important in MOSFET circuits

1
gmL & gms ∝W, Cox ,
L
engineering design
parameter

H. J. Lee | EE | KAIST EE362A | Fall 2015 23

 Substrate Bias Effect (1)

§  What happens if we apply a bias voltage at the body?

VSB ≥ 0
S to B pn junction must be 0 or
reverse biased
Increase in depletion region
width

H. J. Lee | EE | KAIST EE362A | Fall 2015 24

 Substrate Bias Effect (3)

§  Effects of substrate voltage on threshold voltage:

2ε s (2φ fp +VSB )
xdT =
qN a

Q'SD(max) = −qN a xdT

= − 2qε s N a (2φ fp +VSB )
à increase in negative space charge

ΔQ'SD = − 2qε s N a [ 2φ fp −VSB − 2φ fp ]

Increase in negative
charge is reflected as
ΔQ'SD 2qε s N a
ΔVT = − = [ 2φ fp +VSB − 2φ fp ]
change in positive charge Cox Cox

VT increases for nMOS γ : body effect coefficient

H. J. Lee | EE | KAIST EE362A | Fall 2015 25
 Substrate Bias Effect (2)

§  What happens to threshold voltage?

H. J. Lee | EE | KAIST EE362A | Fall 2015 26

 Frequency Limitations (1)

§  Device and parasitic components:

Cgs , Cgd : gate-to-channel cap.

Cgsp , Cgdp : parasitic overlap cap.

(due to the fab. process)
important due to Miller effect
=> Lower the freq. response of the
device

Cds : drain-to-substrate pn junction cap

rs , rd : series resistance
V 'gs : internal gate-to-source voltage

No Css: source and substrate are grounded

H. J. Lee | EE | KAIST EE362A | Fall 2015 27

 Frequency Limitations (2)

§  Small-signal equivalent circuits:

CgsT , CgdT : total gate-to-s/d capacitance.

rds : channel length modulation

(like Early Voltage)

H. J. Lee | EE | KAIST EE362A | Fall 2015 28

 Frequency Limitations (3)

§  At low frequency, caps are open

gate impedance = ∞

rs , rd : neglected

H. J. Lee | EE | KAIST EE362A | Fall 2015 29

 Frequency Limitations (4)

§  Including rs,

Vgs = V 'gs + (gmV 'gs )⋅ rs

= (1+ gm rs )V 'gs

! gm $
I D = gmV 'gs = # &Vgs = g'm Vgs
" 1+ gm rs %

As rs é => g’m ê

The source resistance reduces

the effective transconductance
or transistor gain

H. J. Lee | EE | KAIST EE362A | Fall 2015 30

 Frequency Limitations (5)

§  Two basic frequency limitation factors:

–  Channel transit time vs. gate charging time

§  1) The channel transit time:

–  Assume carriers are traveling at their saturation drift velocity

vsat ≈ 10 7 cm / s

–  Transit time channel length

L
τt =
vsat
–  Example:

if L = 1µ m ⇒ τ t = 10 ps ⇒100GHz

Thus, usually not a limiting factor

H. J. Lee | EE | KAIST EE362A | Fall 2015 31

 Frequency Limitations (6)

§  2) Gate charging time (the capacitance charging time)

(rs , rd , rds , Cds , neglected) Load resistance

<High-frequency small-signal
equivalent circuits>

input gate impedance ≠ ∞

–  Currents at input and output nodes:

I i = jwCgsT Vgs + jwCgdT (Vgs −Vd )

Vd
+ gmVgs + jwCgdT (Vd −Vgs ) = 0
RL

H. J. Lee | EE | KAIST EE362A | Fall 2015 32

 Frequency Limitations (7)

§  Miller capacitance:

' ! 1+ g R $*
I i = jw )CgsT + CgdT ## m L
&&,Vgs I i ( jwCgdT << 1) = jw !"CgsT + CgdT (1+ gm RL )#$Vgs
)( " 1+ jwRL
C gdT %,+

CM = CgdT (1+ gm RL )
Miller capacitance

Especially, Cgdp (Cgd essentially zero)

(drain overlap capacitance) No inversion charge

near drain

§  Overlap parasitic cap. is multiplied by the gain!

H. J. Lee | EE | KAIST EE362A | Fall 2015 33

 Frequency Limitations (8)

§  The cutoff frequency, fT:

–  Frequency at which |the current gain| = 1 or I i = I d

I i = jw(CgsT + CM )Vgs

I d = gmVgs

Id gm
= =1
I i 2π f (CgsT + CM )

gm gm
∴ fT = =
2π (CgsT + CM ) 2π CG
Equivalent input gate capacitance

H. J. Lee | EE | KAIST EE362A | Fall 2015 34

 Frequency Limitations (9)

§  In the ideal MOSFET,

Cgsp & Cgdp = 0

§  In saturation region, Cgd à 0 (no channel charge near the drain)

Cgs ≈ CoxWL

W
gms = µ nCox (VGS −VT )
L

µ n (VGS −VT ) L is very important in the device speed!

⇒ fT =
2π L2 ∴ L ⇒ sub µ m in the modern technology

H. J. Lee | EE | KAIST EE362A | Fall 2015 35

 CMOS Technology (1)

§  Complementary MOS (= NMOS + PMOS on the same wafer)

§  P-well technology

H. J. Lee | EE | KAIST EE362A | Fall 2015 36

 CMOS Technology (2)

§  How to isolate devices:

(1)  Thick oxide:

VTFOXé à circuit voltage

(2) Substrate doping é

à VTFOXé

H. J. Lee | EE | KAIST EE362A | Fall 2015 37

 CMOS Technology (3)

§  “Latch-up”
–  A major problem in CMOS circuits

pnpn direct current flow

à  Can cause permanent damage
à  burnout of the circuit

H. J. Lee | EE | KAIST EE362A | Fall 2015 38

Any Questions?