UNIT 4

Sequential circuit design and analysis

Sequential Circuit Design

 Steps in the design process for sequential circuits

 State Diagrams and State Tables
 Examples

 Steps in Design of a Sequential Circuit

1. Specification – A description of the sequential circuit. Should include a detailing of the
inputs, the outputs, and the operation. Possibly assumes that you have knowledge of digital
system basics.
2. Formulation: Generate a state diagram and/or a state table from the statement of the problem.
3. State Assignment: From a state table assign binary codes to the states.
4. Flip-flop Input Equation Generation: Select the type of flip-flop for the circuit and generate
the needed input for the required state transitions
5. Output Equation Generation: Derive output logic equations for generation of the output from
the inputs and current state.
6. Optimization: Optimize the input and output equations. Today, CAD systems are typically
used for this in real systems.
7. Technology Mapping: Generate a logic diagram of the circuit using ANDs, ORs, Inverters,
and F/Fs.
8. Verification: Use a HDL to verify the design.
Mealy and Moore
 Sequential machines are typically classified as either a Mealy machine or a Moore
machine implementation.
 Moore machine: The outputs of the circuit depend only upon the current state of the
circuit.
 Mealy machine: The outputs of the circuit depend upon both the current state of the
circuit and the inputs.

An example to go through the steps

The specification: The circuit will have one input, X, and one output, Z. The output Z will be 0
except when the input sequence 1101 are the last 4 inputs received on X. In that case it will be a
1
Generation of a state diagram
 Create states and meaning for them.
State A – the last input was a 0 and previous inputs unknown. Can also be the reset state.
State B – the last input was a 1 and the previous input was a 0. The start of a new sequence
possibly.
 Capture this in a state diagram
 Capture this in a state diagram

Circles represent the states

Lines and arcs represent the transition between states.
The notation Input/output on the line or arc specifies the input that causes this transition
and the output for this change of state.
 Add a state C – Have detected the input sequence 11 which is the start of the sequence

Add a state D
State D – have detected the 3rd input in the start of a sequence, a 0, now having
110. From State D, if the next input is a 1 the sequence has been detected and a 1
is output.

The previous diagram was incomplete.

In each state the next input could be a 0 or a 1. This must be included
  The state table

 This can be done directly from the state diagram

 Now need to do a state assignment

Select a state assignment

 Will select a gray encoding

 For this state A will be encoded 00, state B 01, state C 11 and state D 10

Flip-flop input equations

 Generate the equations for the flip-flop inputs

 Generate the D0 equation

 Generate the D1 equation

The output equation
 The next step is to generate the equation for the output Z and what is needed to generate
it.
 Create a K-map from the truth table.

Now map to a circuit

 The circuit has 2 D type F/Fs

Shift registers:
In digital circuits, a shift register is a cascade of flip-flops sharing the same clock, in
which the output of each flip-flop is connected to the "data" input of the next flip-flop in the
chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the
data present at its input and shifting out the last bit in the array, at each transition of the clock
input. More generally, a shift register may be multidimensional, such that its "data in" and stage
outputs are themselves bit arrays: this is implemented simply by running several shift registers of
the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured
as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that
have both serial and parallel input and types with serial and parallel output. There are also bi-
directional shift registers which allow shifting in both directions: L→R or R→L. The serial
input and last output of a shift register can also be connected to create a circular shift register
Shift registers are a type of logic circuits closely related to counters. They are basically for the
storage and transfer of digital data.
Buffer register:
The buffer register is the simple set of registers. It is simply stores the binary word. The buffer
may be controlled buffer. Most of the buffer registers used D Flip-flops.

Figure: logic diagram of 4-bit buffer register

The figure shows a 4-bit buffer register. The binary word to be stored is applied to the data
terminals. On the application of clock pulse, the output word becomes the same as the word
applied at the terminals. i.e., the input word is loaded into the register by the application of clock
pulse.
When the positive clock edge arrives, the stored word becomes:
Q4Q3Q2Q1=X4X3X2X1
Q=X
Controlled buffer register:
If goes LOW, all the FFs are RESET and the output becomes, Q=0000.
When is HIGH, the register is ready for action. LOAD is the control input. When
LOAD is HIGH, the data bits X can reach the D inputs of FF‘s.
Q4Q3Q2Q1=X4X3X2X1
Q=X
When load is low, the X bits cannot reach the FF‘s.
Data transmission in shift registers:

A number of ff‘s connected together such that data may be shifted into and shifted out of them is
called shift register. data may be shifted into or out of the register in serial form or in parallel
form. There are four basic types of shift registers.
1. Serial in, serial out, shift right, shift registers
2. Serial in, serial out, shift left, shift registers
3. Parallel in, serial out shift registers
4. Parallel in, parallel out shift registers
Serial IN, serial OUT, shift right, shift left register:

The logic diagram of 4-bit serial in serial out, right shift register with four stages. The register
can store four bits of data. Serial data is applied at the input D of the first FF. the Q output of the
first FF is connected to the D input of another FF. the data is outputted from the Q terminal of
the last FF.

When serial data is transferred into a register, each new bit is clocked into the first FF at the
positive going edge of each clock pulse. The bit that was previously stored by the first FF is
transferred to the second FF. the bit that was stored by the Second FF is transferred to the third
FF.

Serial-in, parallel-out, shift register:

In this type of register, the data bits are entered into the register serially, but the data stored in
the register is shifted out in parallel form.

Once the data bits are stored, each bit appears on its respective output line and all bits are
available simultaneously, rather than on a bit-by-bit basis with the serial output. The serial-in,
parallel out, shift register can be used as serial-in, serial out, shift register if the output is taken
from the Q terminal of the last FF.
Parallel-in, serial-out, shift register:

For a parallel-in, serial out, shift register, the data bits are entered simultaneously into their
respective stages on parallel lines, rather than on a bit-by-bit basis on one line as with serial data
bits are transferred out of the register serially. On a bit-by-bit basis over a single line.
There are four data lines A,B,C,D through which the data is entered into the register in
parallel form. The signal shift/ load allows the data to be entered in parallel form into the register
and the data is shifted out serially from terminalQ4

Parallel-in, parallel-out, shift register

In a parallel-in, parallel-out shift register, the data is entered into the register in parallel form,
and also the data is taken out of the register in parallel form. Data is applied to the D input
terminals of the FF‘s. When a clock pulse is applied, at the positive going edge of the pulse, the
D inputs are shifted into the Q outputs of the FFs. The register now stores the data. The stored
data is available instantaneously for shifting out in parallel form.
Bidirectional shift register:

A bidirectional shift register is one which the data bits can be shifted from left to right
or from right to left. A fig shows the logic diagram of a 4-bit serial-in, serial out, bidirectional
shift register. Right/left is the mode signal, when right /left is a 1, the logic circuit works as a
shift-register.the bidirectional operation is achieved by using the mode signal and two NAND
gates and one OR gate for each stage.

A HIGH on the right/left control input enables the AND gates G1, G2, G3 and G4 and
disables the AND gates G5,G6,G7 and G8, and the state of Q output of each FF is passed
through the gate to the D input of the following FF. when a clock pulse occurs, the data bits are
then effectively shifted one place to the right. A LOW on the right/left control inputs enables the
AND gates G5, G6, G7 and G8 and disables the And gates G1, G2, G3 and G4 and the Q output
of each FF is passed to the D input of the preceding FF. when a clock pulse occurs, the data bits
are then effectively shifted one place to the left. Hence, the circuit works as a bidirectional shift
register

Figure: logic diagram of a 4-bit bidirectional shift register

Universal shift register:

A register is capable of shifting in one direction only is a unidirectional shift register. One that
can shift both directions is a bidirectional shift register. If the register has both shifts and parallel
load capabilities, it is referred to as a universal shift registers. Universal shift register is a
bidirectional register, whose input can be either in serial form or in parallel form and whose
output also can be in serial form or I parallel form.
The most general shift register has the following capabilities.

1. A clear control to clear the register to 0

2. A clock input to synchronize the operations
3. A shift-right control to enable the shift-right operation and serial input and output lines
associated with the shift-right
 4. A shift-left control to enable the shift-left operation and serial input and output lines
associated with the shift-left
5. A parallel loads control to enable a parallel transfer and the n input lines associated with
the parallel transfer
6. N parallel output lines
7. A control state that leaves the information in the register unchanged in the presence of
the clock.

A universal shift register can be realized using multiplexers. The below fig shows the logic
diagram of a 4-bit universal shift register that has all capabilities. It consists of 4 D flip-flops and
four multiplexers. The four multiplexers have two common selection inputs s1 and s0. Input 0 in
each multiplexer is selected when S1S0=00, input 1 is selected when S1S0=01 and input 2 is
selected when S1S0=10 and input 4 is selected when S1S0=11. The selection inputs control the
mode of operation of the register according to the functions entries. When S1S0=0, the present
value of the register is applied to the D inputs of flip-flops. The condition forms a path from the
output of each flip-flop into the input of the same flip-flop. The next clock edge transfers into
each flip-flop the binary value it held previously, and no change of state occurs. When S1S0=01,
terminal 1 of the multiplexer inputs have a path to the D inputs of the flip-flop. This causes a
shift-right operation, with serial input transferred into flip-flopA4. When S1S0=10, a shift left
operation results with the other serial input going into flip-flop A1. Finally when S1S0=11, the
binary information on the parallel input lines is transferred into the register simultaneously
during the next clock cycle

Figure: logic diagram 4-bit universal shift register

Function table for theregister

mode control
S0 S1 register operation

0 0 No change
0 1 Shift Right
1 0 Shift left
1 1 Parallel load

Counters:

Counter is a device which stores (and sometimes displays) the number of times
particular event or process has occurred, often in relationship to a clock signal. A Digital counter
is a set of flip flops whose state change in response to pulses applied at the input to the counter.
Counters may be asynchronous counters or synchronous counters. Asynchronous counters are
also called ripple counters
In electronics counters can be implemented quite easily using register-type circuits such as
the flip-flops and a wide variety of classifications exist:

 Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state
flip-flops
 Synchronous counter – all state bits change under control of a single clock
 Decade counter – counts through ten states per stage
 Up/down counter – counts both up and down, under command of a control input
 Ring counter – formed by a shift register with feedback connection in a ring
 Johnson counter – a twisted ring counter
Cascaded counter
Modulus counter.

Each is useful for different applications. Usually, counter circuits are digital in nature, and count
in natural binary Many types of counter circuits are available as digital building blocks, for
example a number of chips in the 4000 series implement different counters.
Occasionally there are advantages to using a counting sequence other than the natural binary
sequence such as the binary coded decimal counter, a linear feed-back shift register counter, or
a gray-code counter.
Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.
Asynchronous counters:

An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input fed
from its own inverted output. This circuit can store one bit, and hence can count from zero to one
before it overflows (starts over from 0). This counter will increment once for every clock cycle
and takes two clock cycles to overflow, so every cycle it will alternate between a transition from
0 to 1 and a transition from 1 to 0. Notice that this creates a new clock with a 50% duty cycle at
exactly half the frequency of the input clock. If this output is then used as the clock signal for a
similarly arranged D flip-flop (remembering to invert the output to the input), one will get
another 1 bit counter that counts half as fast. Putting them together yields a two-bit counter:

Two-bit ripple up-counter using negative edge triggered flip flop:

Two bit ripple counter used two flip-flops. There are four possible states from 2 – bit up-
counting I.e. 00, 01, 10 and 11.

· The counter is initially assumed to be at a state 00 where the outputs of the tow flip-flops
are noted as Q1Q0. Where Q1 forms the MSB and Q0 forms the LSB.

· For the negative edge of the first clock pulse, output of the first flip-flop FF1 toggles its
state. Thus Q1 remains at 0 and Q0 toggles to 1 and the counter state are now read as 01.

· During the next negative edge of the input clock pulse FF1 toggles and Q0 = 0. The output
Q0 being a clock signal for the second flip-flop FF2 and the present transition acts as a negative
edge for FF2 thus toggles its state Q1 = 1. The counter state is now read as 10.

· For the next negative edge of the input clock to FF1 output Q0 toggles to 1. But this
transition from 0 to 1 being a positive edge for FF2 output Q1 remains at 1. The counter state is
now read as 11.

· For the next negative edge of the input clock, Q0 toggles to 0. This transition from 1 to 0
acts as a negative edge clock for FF2 and its output Q1 toggles to 0. Thus the starting state 00 is
attained. Figure shown below
Two-bit ripple down-counter using negative edge triggered flip flop:

A 2-bit down-counter counts in the order 0,3,2,1,0,1…….,i.e, 00,11,10,01,00,11 …..,etc. the

above fig. shows ripple down counter, using negative edge triggered J-K FFs and its timing
diagram.
 For down counting, Q1‘ of FF1 is connected to the clock of Ff2. Let initially all the FF1
toggles, so, Q1 goes from a 0 to a 1 and Q1‘ goes from a 1 to a 0.
  The negative-going signal at Q1‘ is applied to the clock input of FF2, toggles Ff2 and,
therefore, Q2 goes from a 0 to a 1.so, after one clock pulse Q2=1 and Q1=1, I.e., the state
of the counter is 11.
 At the negative-going edge of the second clock pulse, Q1 changes from a 1 to a 0 and
Q1‘ from a 0 to a 1.
 This positive-going signal at Q1‘ does not affect FF2 and, therefore, Q2 remains at a 1.
Hence , the state of the counter after second clock pulse is 10
 At the negative going edge of the third clock pulse, FF1 toggles. So Q1, goes from a 0 to
a 1 and Q1‘ from 1 to 0. This negative going signal at Q1‘ toggles FF2 and, so, Q2
changes from 1 to 0, hence, the state of the counter after the third clock pulse is 01.
 At the negative going edge of the fourth clock pulse, FF1 toggles. So Q1, goes from a 1
to a 0 and Q1‘ from 0 to 1. . This positive going signal at Q1‘ does not affect FF2 and, so,
Q2 remains at 0, hence, the state of the counter after the fourth clock pulse is 00.

Two-bit ripple up-down counter using negative edge triggered flip flop:

Figure: asynchronous 2-bit ripple up-down counter using negative edge triggered flip flop:

 As the name indicates an up-down counter is a counter which can count both in upward
and downward directions. An up-down counter is also called a forward/backward counter
or a bidirectional counter. So, a control signal or a mode signal M is required to choose
the direction of count. When M=1 for up counting, Q1 is transmitted to clock of FF2 and
when M=0 for down counting, Q1‘ is transmitted to clock of FF2. This is achieved by
using two AND gates and one OR gates. The external clock signal is applied to FF1.
 Clock signal to FF2= (Q1.Up)+(Q1‘. Down)= Q1m+Q1‘M‘

Design of Asynchronous counters:

To design a asynchronous counter, first we write the sequence , then tabulate the values of
reset signal R for various states of the counter and obtain the minimal expression for R and R‘
using K-Map or any other method. Provide a feedback such that R and R‘ resets all the FF‘s after
the desired count
 Design of a Mod-6 asynchronous counter using T FFs:
A mod-6 counter has six stable states 000, 001, 010, 011, 100, and 101. When the sixth
clock pulse is applied, the counter temporarily goes to 110 state, but immediately resets to 000
because of the feedback provided. it is ―divide by-6-counter‖, in the sense that it divides the
input clock frequency by 6.it requires three FFs, because the smallest value of n satisfying the
conditionN≤2n is n=3; three FFs can have 8 possible states, out of which only six are utilized and
the remaining two states 110and 111, are invalid. If initially the counter is in 000 state, then after
the sixth clock pulse, it goes to 001, after the second clock pulse, it goes to 010, and so on.

After sixth clock pulse it goes to 000. For the design, write the truth table with present state
outputs Q3, Q2 and Q1 as the variables, and reset R as the output and obtain an expression for R
in terms of Q3, Q2, and Q1that decides the feedback into be provided. From the truth table,
R=Q3Q2. For active-low Reset, R‘ is used. The reset pulse is of very short duration, of the order
of nanoseconds and it is equal to the propagation delay time of the NAND gate used. The
expression for R can also be determined as follows.

R=0 for 000 to 101, R=1 for 110, and R=X=for111

Therefore,
R=Q3Q2Q1‘+Q3Q2Q1=Q3Q2

The logic diagram and timing diagram of Mod-6 counter is shown in the above fig.

The truth table is as shown in below.

 After States
pulses Q3 Q2 Q1 R

0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 0
4 1 0 0 0
5 1 0 1 0
6 1 1 0 1

0 0 0 0
7 0 0 0 0

Design of a mod-10 asynchronous counter using T-flip-flops:

A mod-10 counter is a decade counter. It also called a BCD counter or a divide-by-10
counter. It requires four flip-flops (condition 10 ≤2n is n=4). So, there are 16 possible states, out
of which ten are valid and remaining six are invalid. The counter has ten stable state, 0000
through 1001, i.e., it counts from 0 to 9. The initial state is 0000 and after nine clock pulses it
goes to 1001. When the tenth clock pulse is applied, the counter goes to state 1010 temporarily,
but because of the feedback provided, it resets to initial state 0000. So, there will be a glitch in
the waveform of Q2. The state 1010 is a temporary state for which the reset signal R=1, R=0 for
0000 to 1001, and R=C for 1011 to 1111.

The count table and the K-Map for reset are shown in fig. from the K-Map R=Q4Q2. So,
feedback is provided from second and fourth FFs. For active –HIGH reset, Q4Q2 is applied to
the clear terminal. For active-LOW reset 4 2 is connected isof all Flip=flops.
 After Count
pulses Q4 Q3 Q2 Q1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 0 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 0 1 0 1
10 0 0 0 0
Synchronous counters:

Asynchronous counters are serial counters. They are slow because each FF can change state
only if all the preceding FFs have changed their state. if the clock frequency is very high, the
asynchronous counter may skip some of the states. This problem is overcome in synchronous
counters or parallel counters. Synchronous counters are counters in which all the flip flops are
triggered simultaneously by the clock pulses Synchronous counters have a common clock pulse
applied simultaneously to all flip- -Bit Synchronous Binary Counter

Design of synchronous counters:

For a systematic design of synchronous counters. The following procedure is used.

Step 1:State Diagram: draw the state diagram showing all the possible states state diagram which
also be called nth transition diagrams, is a graphical means of depicting the sequence of states
through which the counter progresses.

Step2: number of flip-flops: based on the description of the problem, determine the required
number n of the flip-flops- the smallest value of n is such that the number of states N≤2n--- and
the desired counting sequence.

Step3: choice of flip-flops excitation table: select the type of flip-flop to be used and write the
excitation table. An excitation table is a table that lists the present state (ps) , the next state(ns)
and required excitations.
Step4: minimal expressions for excitations: obtain the minimal expressions for the excitations of
the FF using K-maps drawn for the excitation of the flip-flops in terms of the present states and
inputs.

Step5: logic diagram: draw a logic diagram based on the minimal expressions

Design of a synchronous 3-bit up-down counter using JK flip-flops:

Step1: determine the number of flip-flops required. A 3-bit counter requires three FFs. It has 8
states (000,001,010,011,101,110,111) and all the states are valid. Hence no don‘t cares. For
selecting up and down modes, a control or mode signal M is required. When the mode signal
M=1 and counts down when M=0. The clock signal is applied to all the FFs simultaneously.

Step2: draw the state diagrams: the state diagram of the 3-bit up-down counter is drawn as

Step3: select the type of flip flop and draw the excitation table: JK flip-flops are selected and the
excitation table of a 3-bit up-down counter using JK flip-flops is drawn as shown in fig.

PS mode NS required excitations

Q3 Q2 Q1 M Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
0 0 0 0 1 1 1 1 x 1 x 1 x
0 0 0 1 0 0 1 0 x 0 x 1 x
0 0 1 0 0 0 0 0 x 0 x x 1
0 0 1 1 0 1 0 0 x 1 x x 1
0 1 0 0 0 0 1 0 x x 1 1 x
0 1 0 1 0 1 1 0 x x 0 1 x
0 1 1 0 0 1 0 0 x x 0 x 1
0 1 1 1 1 0 0 1 x x 1 x 1
1 0 0 0 0 1 1 x 1 1 x 1 x
1 0 0 1 1 0 1 x 0 0 x 1 x
1 0 1 0 1 0 0 x 0 0 x x 1
1 0 1 1 1 1 0 x 0 1 x x 1
1 1 0 0 1 0 1 x 0 x 1 1 x
1 1 0 1 1 1 1 x 0 x 0 1 x
1 1 1 0 1 1 0 x 0 x 0 x 1
1 1 1 1 0 0 0 x 1 x 1 x 1

Step4: obtain the minimal expressions: From the excitation table we can conclude that J1=1 and
K1=1, because all the entries for J1and K1 are either X or 1. The K-maps for J3, K3,J2 and K2
based on the excitation table and the minimal expression obtained from them are shown in fig.
 00 01 11 10
Q3Q2 Q1M
1
1
X X X X
X X X X

Step5: draw the logic diagram: a logic diagram using those minimal expressions can be drawn as
shown in fig.

Design of a synchronous modulo-6 gray cod counter:

Step 1: the number of flip-flops: we know that the counting sequence for a modulo-6 gray code
counter is 000, 001, 011, 010, 110, and 111. It requires n=3FFs (N≤2n, i.e., 6≤23). 3 FFs can have
8 states. So the remaining two states 101 and 100 are invalid. The entries for excitation
corresponding to invalid states are don‘t cares.
Step2: the state diagram: the state diagram of the mod-6 gray code converter is drawn as shown
in fig.
Step3: type of flip-flop and the excitation table: T flip-flops are selected and the excitation table
of the mod-6 gray code counter using T-flip-flops is written as shown in fig.

required
PS NS excitations
Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 0 1
0 1 0 1 1 0 1 0 0
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Step4: The minimal expressions: the K-maps for excitations of FFs T3,T2,and T1 in terms of
outputs of FFs Q3,Q2, and Q1, their minimization and the minimal expressions for excitations
obtained from them are shown if fig

Step5: the logic diagram: the logic diagram based on those minimal expressions is drawn as
shown in fig.
Design of a synchronous BCD Up-Down counter using FFs:

Step1: the number of flip-flops: a BCD counter is a mod-10 counter has 10 states (0000 through
1001) and so it requires n=4FFs(N≤2n,, i.e., 10≤24). 4 FFS can have 16 states. So out of 16 states,
six states (1010 through 1111) are invalid. For selecting up and down mode, a control or mode
signal M is required. , it counts up when M=1 and counts down when M=0. The clock signal is
applied to all FFs.

Step2: the state diagram: The state diagram of the mod-10 up-down counter is drawn as shown
in fig.

Step3: types of flip-flops and excitation table: T flip-flops are selected and the excitation table of
the modulo-10 up down counter using T flip-flops is drawn as shown in fig.

The remaining minterms are don‘t cares(∑d(20,21,22,23,24,25,26,37,28,29,30,31)) from

the excitation table we can see that T1=1 and the expression for T4,T3,T2 are as follows.
T4=∑m(0,15,16,19)+d(20,21,22,23,24,25,26,27,28,29,30,31)
T3=∑m(7,15,16,8)+d(20,21,22,23,24,25,26,27,28,29,30,31)
T2=∑m(3,4,7,8,11,12,15,16)+d(20,21,22,23,24,25,26,27,28,29,30,31)

PS NS

mode required excitations

Q4 Q3 Q2 Q1 M Q4 Q3 Q2 Q1 T4 T3 T2 T1
0 0 0 0 0 1 0 0 1 1 0 0 1
0 0 0 0 1 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 0 0 1 0 0 1 1
0 0 1 0 1 0 0 1 1 0 0 0 1
0 0 1 1 0 0 0 1 0 0 0 0 1
0 0 1 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 0 0 1 1 0 1 1 1
0 1 0 0 1 0 1 0 1 0 0 0 1
0 1 0 1 0 0 1 0 0 0 0 0 1
0 1 0 1 1 0 1 1 0 0 0 1 1
0 1 1 0 0 0 1 0 1 0 0 1 1
0 1 1 0 1 0 1 1 1 0 0 0 1
0 1 1 1 0 0 1 1 0 0 0 0 1
0 1 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 1 1 0 0 1 0 0 0 1
1 0 0 1 0 1 0 0 0 0 0 0 1
1 0 0 1 1 0 0 0 0 1 0 0 1
Step4: The minimal expression: since there are 4 state variables and a mode signal, we require 5
variable kmaps. 20 conditions of Q4Q3Q2Q1M are valid and the remaining 12 combinations are
invalid. So the entries for excitations corresponding to those invalid combinations are don‘t
cares. Minimizing K-maps for T2 we get
T 2= Q4Q1‘M+Q4‘Q1M+Q2Q1‘M‘+Q3Q1‘M‘

Step5: the logic diagram: the logic diagram based on the above equation is shown in fig.

Shift register counters:

One of the applications of shift register is that they can be arranged to form several types of
counters. The most widely used shift register counter is ring counter as well as the twisted ring
counter.

Ring counter: this is the simplest shift register counter. The basic ring counter using D flip-
flops is shown in fig. the realization of this counter using JK FFs. The Q output of each stage is
connected to the D flip-flop connected back to the ring counter.

FIGURE: logic diagram of 4-bit ring counter using D flip-flops

Only a single 1 is in the register and is made to circulate around the register as long as clock
pulses are applied. Initially the first FF is present to a 1. So, the initial state is 1000, i.e., Q1=1,
Q2=0,Q3=0,Q4=0. After each clock pulse, the contents of the register are shifted to the right by
one bit and Q4 is shifted back to Q1. The sequence repeats after four clock pulses. The number
of distinct states in the ring counter, i.e., the mod of the ring counter is equal to number of FFs
used in the counter. An n-bit ring counter can count only n bits, where as n-bit ripple counter can
count 2n bits. So, the ring counter is uneconomical compared to a ripple counter but has
advantage of requiring no decoder, since we can read the count by simply noting which FF is set.
Since it is entirely a synchronous operation and requires no gates external FFs, it has the further
advantage of being very fast.

Timing diagram:

Figure: state diagram

Twisted Ring counter (Johnson counter):

This counter is obtained from a serial-in, serial-out shift register by providing feedback
from the inverted output of the last FF to the D input of the first FF. the Q output of each is
connected to the D input of the next stage, but the Q‘ output of the last stage is connected to the
D input of the first stage, therefore, the name twisted ring counter. This feedback arrangement
produces a unique sequence of states.

The logic diagram of a 4-bit Johnson counter using D FF is shown in fig. the realization
of the same using J-K FFs is shown in fig.. The state diagram and the sequence table are shown
in figure. The timing diagram of a Johnson counter is shown in figure.

Let initially all the FFs be reset, i.e., the state of the counter be 0000. After each clock
pulse, the level of Q1 is shifted to Q2, the level of Q2to Q3, Q3 to Q4 and the level of Q4‘to Q1
and the sequences given in fig.

Figure: Johnson counter with JK flip-flops

Figure: timing diagram

State diagram:
after
clock
Q1 Q2 Q3 Q4 pulse
0 0 0 0 0
1 0 0 0 1
1 1 0 0 2
1 1 1 0 3
1 1 1 1 4
0 1 1 1 5
0 0 1 1 6
0 0 0 1 7
0 0 0 0 8
1 0 0 0 9
Excitation table

Synthesis of sequential circuits:

The synchronous or clocked sequential circuits are represented by two models.

1. Moore circuit: in this model, the output depends only on the present state of the flip-
flops
2. Meelay circuit: in this model, the output depends on both present state of the flip-
flop. And the inputs.

Sequential circuits are also called finite state machines (FSMs). This name is due to the fast that
the functional behavior of these circuits can be represented using a finite number of states.

State diagram: the state diagram or state graph is a pictorial representation of the relationships
between the present state, the input, the next state, and the output of a sequential circuit. The
state diagram is a pictorial representation of the behavior of a sequential circuit.

The state represented by a circle also called the node or vertex and the transition between
states is indicated by directed lines connecting circle. a directed line connecting a circle with
itself indicates that the next state is the same as the present state. The binary number inside each
circle identifies the state represented by the circle. The direct lines are labeled with two binary
numbers separated by a symbol. The input value is applied during the present state is labeled
after the symbol.
 NS,O/P
INPUT X
PS X=0 X=1
a a,0 b,0
b b,1 c,0
c d,0 c,1
d d,0 a,1

Fig :a) state diagram (meelay circuit) fig: b) state table

In case of moore circuit ,the directed lines are labeled with only one binary number representing
the input that causes the state transition. The output is indicated with in the circle below the
present state, because the output depends only on the present state and not on the input.

NS
INPUT X
PS X=0 X=1 O/P
a a b 0
b b c 0
c d c 1
d a d 0

Fig: a) state diagram (moore circuit) fig:b) state table

Serial binary adder:

Step1: word statement of the problem: the block diagram of a serial binary adder is shown in
fig. it is a synchronous circuit with two input terminals designated X1and X2 which carry the
two binary numbers to be added and one output terminal Z which represents the sum. The inputs
and outputs consist of fixed-length sequences 0s and 1s.the output of the serial Zi at time tiis a
function of the inputs X1(ti) and X2(ti) at that time ti-1 and of carry which had been generated at ti-
1. The carry which represent the past history of the serial adder may be a 0 or 1. The circuit has
two states. If one state indicates that carry from the previous addition is a 0, the other state
indicates that the carry from the previous addition is a 1
 Figure: block diagram of serial binary adder

Step2 and 3: state diagram and state table: let a designate the state of the serial adder at ti if a
carry 0 was generated at ti-1, and let b designate the state of the serial adder at t i if carry 1 was
generated at ti-1 .the state of the adder at that time when the present inputs are applied is referred
to as the present state(PS) and the state to which the adder goes as a result of the new carry value
is referred to as next state(NS).
The behavior of serial adder may be described by the state diagram and state table.

PS NS ,O/P
X1 X2
0 0 1 1
0 1 0 1
A A,0 B,0 B,1 B,0
B A,1 B,0 B,0 B,1

Figures: serial adder state diagram and state table

If the machine is in state B, i.e., carry from the previous addition is a 1, inputs X 1=0 and X2=1
gives sum, 0 and carry 1. So the machine remains in state B and outputs a 0. Inputs X 1=1 and
X2=0 gives sum, 0 and carry 1. So the machine remains in state B and outputs a 0. Inputs X1=1
and X2=1 gives sum, 1 and carry 0. So the machine remains in state B and outputs a 1. Inputs
X1=0 and X2=0 gives sum, 1 and carry 0. So the machine goes to state A and outputs a 1. The
state table also gives the same information.

Setp4: reduced standard from state table: the machine is already in this form. So no need to
do anything

Step5: state assignment and transition and output table:

The states, A=0 and B=1 have already been assigned. So, the transition and output table is as
shown.
 PS NS O/P
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1

0 0 0 0 1 0 1 1 1
1 0 1 1 1 1 0 0 1

STEP6: choose type of FF and excitation table: to write table, select the memory element the
excitation table is as shown in fig.
PS I/P NS I/P-FF O/P
y x1 x2 Y D Z
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 1 0
1 1 0 1 1 0
1 1 1 1 1 1

Sequence detector:
Step1: word statement of the problem: a sequence detector is a sequential machine which
produces an output 1 every time the desired sequence is detected and an output 0 at all other
times
Suppose we want to design a sequence detector to detect the sequence 1010 and say that
overlapping is permitted i.e., for example, if the input sequence is 01101010 the corresponding
output sequence is 00000101.
Step2 and 3: state diagram and state table: the state diagram and the state table of the sequence
detector. At the time t1, the machine is assumed to be in the initial state designed arbitrarily as A.
while in this state, the machine can receive first bit input, either a 0 o r a 1. If the input bit is 0,
the machine does not start the detection process because the first bit in the desired sequence is a
1. If the input bit is a 1 the detection process starts.

PS NS,Z
X=0 X=1
A A,0 B,0
B C,0 B,0
C A,0 D,0
D C,1 B,0

Figure: state diagram and state table of sequence detector

So, the machine goes to state B and outputs a 0. While in state B, the machinery may receive 0 or
1 bit. If the bit is 0, the machine goes to the next state, say state c, because the previous two bits
are 10 which are a part of the valid sequence, and outputs 0.. if the bit is a 1, the two bits become
11 and this not a part of the valid sequence
Step4: reduced standard form state table: the machine is already in this form. So no need to do
anything.
Step5: state assignment and transition and output table: there are four states therefore two states
variables are required. Two state variables can have a maximum of four states, so, all states are
utilized and thus there are no invalid states. Hence, there are no don‘t cares. Let a=00, B=01,
C=10 and D=11 be the state assignment.

NS(Y1Y2) O/P(z)
PS(y1y2 X=0 X=1 X=0 X=1
A= 0 0 0 0 0 1 0 0
B=0 1 1 0 0 1 0 0
C=1 0 0 0 1 1 0 0
D=1 1 1 1 0 1 1 0

Step6: choose type of flip-flops and form the excitation table: select the D flip-flops as memory
elements and draw the excitation table.

INPUTS -
PS I/P NS FFS O/P
y1 Y2 X Y1 Y2 D1 D2 Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 1 1 1 1 0
1 1 0 1 0 1 0 1
1 1 1 0 1 0 1 0

Step7: K-maps and minimal functions: based on the contents of the excitation table , draw the k-
map and simplify them to obtain the minimal expressions for D1 and D2 in terms of y1, y2 and x
as shown in fig. The expression for z (z=y1,y2) can be obtained directly from table

Step8: implementation: the logic diagram based on these minimal expressions