MAX17701

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MAX17701 4.5V to 60V, Synchronous Step-Down

Supercapacitor Charger Controller
General Description Benefits and Features

The Himalaya series of voltage regulator ICs, power mod- ● Optimized Feature Set for Supercapacitor Charging
ules, and chargers enable cooler, smaller, and simpler • ±4% Charging Current Regulation Accuracy
power supply solutions. The MAX17701 is a high efficien- • ±6% Charging Current Monitor Accuracy (ISMON)
cy, high voltage, Himalaya synchronous, step-down, su- • ±1% Voltage Regulation Accuracy
percapacitor charger controller designed to operate over • Programmable CC Mode Charging Current (ILIM)
an input-voltage range of a 4.5V to 60V. The MAX17701 • Wide 4.5V to 60V Input-Voltage Range
operates over a -40°C to +125°C industrial temperature • Adjustable Output-Voltage Range from 1.25V Up
range and charges a supercapacitor with a ±4% accurate To (VDCIN - 2.1V)
constant current. After the supercapacitor is charged, the • 125kHz to 2.2MHz Adjustable Frequency with
device regulates the no-load output voltage with ±1% ac- External Clock Synchronization (RT/SYNC)
curacy. The output voltage is programmable from 1.25V ● Reliable Operation in Adverse Environmental
up to (VDCIN - 2.1V). Conditions
The MAX17701 supercapacitor charger controller is de- • Input Short-Circuit Protection (GATEN)
signed to provide a holistic application solution requiring • Safety Timer Feature (TMR)
backup energy storage with a precise charging capability. • Output Overvoltage Protection (OVI)
The device uses an external nMOSFET to provide input • Cycle-by-Cycle Overcurrent Limit
supply-side short-circuit protection; thus, preventing su- • Programmable EN/UVLO Threshold
percapacitor discharge. • Status Output Monitoring Using Open-Drain
The MAX17701 provides a safety timer (TMR) feature to Outputs (FLG1 and FLG2)
set the maximum allowed constant current (CC) mode • Complies with CISPR 32 (EN55032) Class B
charging time. The device features an uncommitted com- Conducted and Radiated Emissions
parator, which can be used to detect an output over- • Overtemperature Protection
voltage event (OVI) and prevent the supercapacitor from • Wide -40°C to +125°C Ambient Operating
overcharging. The MAX17701 is available in a 24-pin Temperature Range/ -40°C to +150°C Junction
4mm x 4mm TQFN package with an exposed pad. Temperature Range
Applications
● Peak Power Delivery and Energy Storage
● Backup Power for Industrial Safety
● Ride-Through Last-Gasp Supplies
● Portable Medical Equipment
● Building and Home Automation Backup Power
Simplified Application Circuit

UP TO 60V SUPERCA PA CITOR CHA RGING PROFIL E WITH 10A L OA D
VOUT
CIN C V MO D E
1V/DIV
DCIN GATEN VIN VOUT
FB DH C C MO D E
SUPERCAPACITOR
L RS
LX
VOUT ISMON ICHG
M A X 17701 SYSTEM 5A /DIV
DL LOAD
PGND V OU T
OVI
FLG2 CSP ICHG
FLG1
CSN
TIME SCALE: 20s/DIV
Ordering Information appears at end of data sheet. 19-100772; Rev 6; 6/22
© 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
24 PIN TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAX17701 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAX17701 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-Up/-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Short-Circuit Protection (GATEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Charger Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Charger Timers (TMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Charger Status Outputs (FLG1, FLG2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Hardware Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Linear Regulator (VCC and EXTVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reference Voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Setting the Switching Frequency and External Clock Synchronization (RT/SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Peak Current-Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Charging Current Monitoring (ISMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thermal-Shutdown Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Operating Input-Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CC Mode Charging Current Setting (ILIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Setting the Input Undervoltage-Lockout Level (EN/UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Current Regulation Loop Compensation (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Setting the Output Voltage and Voltage Regulation Loop (FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Output Overvoltage Protection (OVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bootstrap Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bootstrap Diode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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TABLE OF CONTENTS (CONTINUED)

Input Short-Circuit Protection External nMOSFET Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Step-Down Converter nMOSFET Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Device Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
20A Supercapacitor Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

LIST OF FIGURES
Figure 1. Average Current Mode Control Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2. Charger Power-Up/-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. Input Short-Circuit Protection and Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Current-Sense Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. Setting Input-Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. Setting the Supercapacitor Overvoltage Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7. 5V/20A Supercapacitor Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. 2.5V/20A Supercapacitor Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

LIST OF TABLES
Table 1. Status Output Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2. Protection Under System Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Absolute Maximum Ratings

VIN to SGND/EP ..................................................... -0.3V to +65V BST to PGND.......................................................... -0.3V to +70V
DCIN to SGND/EP....................... -0.3V to min(+65V, VIN + 0.6V) DL to PGND ................................................ -0.3V to (VCC+ 0.3V)
GATEN to SGND/EP .... max(-0.3V, DCIN - 0.3V) to (DCIN + 6V) DH to LX .................................................... -0.3V to (BST + 0.3V)
GATEN to DCIN ....................................................... -0.3V to +6V EXTVCC to SGND/EP ............................................ -0.3V to +26V
VCC to SGND/EP .......................... -0.3V to min(+6V, VIN + 0.3V) PGND, IC1 to SGND/EP ........................................ -0.3V to +0.3V
CSN, CSP to SGND/EP .............................. -0.3V to (VIN + 0.6V) Continuous Power Dissipation (TA = +70°C) (TQFN (derate
CSP to CSN .......................................................... -0.3V to +0.3V 27.85mW/°C above +70°C)) ...........................................2222mW
VREF, TMR, ILIM to SGND/EP ................... -0.3V to (VCC + 0.3V) Operating Temperature Range (Note 1) .............-40°C to +125°C
COMP, ISMON, RT/SYNC to SGND/EP .... -0.3V to (VCC + 0.3V) Junction Temperature ....................................................... +150°C
OVI, FB to SGND/EP ............................................... -0.3V to +6V Storage Temperature Range ..............................-65°C to +150°C
FLG1, FLG2, EN/UVLO to SGND/EP ...................... -0.3V to +6V Lead Temperature (soldering, 10s)................................... +300°C
LX to PGND ............................................................ -0.3V to +65V Soldering Temperature (reflow) ........................................ +260°C
BST to LX ................................................................. -0.3V to +6V
Note 1: Junction temperature greater than +125°C degrades operating lifetimes.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Package Information
24 PIN TQFN
Package Code T2444+5C
Outline Number 21-100405
Land Pattern Number 90-100139
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 36ºC/W
Junction to Case (θJC) 3ºC/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VIN = VDCIN = 24V, CVIN = 4.7µF, CDCIN = 100nF, CVCC = 4.7µF, CVREF = 100nF, CBST = 470nF, VEXTVCC = VSGND/EP = VPGND =
VFB = VOVI = VIC1 = 0V, VEN/UVLO = VLX = VTMR = VILIM = VCSN = VCSP = 2.5V, VBST to VLX = 5V, RT/SYNC = DH = DL = GATEN
= COMP = FLG1 = FLG2 = ISMON = Unconnected, TA= -40°C to +125°C, unless otherwise noted. Typical values are at TA= +25°C.
All voltages are referenced to SGND/EP, unless otherwise noted.) (Note 2 )
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
DCIN connected to VIN, External
4.5 60
DCIN Voltage Range nMOSFET not used V
External nMOSFET used 5.5 60
VIN Voltage Range 4.5 60 V
Input Quiescent Current IQNS (VIN - VCSN) > 2.1V, VFB = 1.5V 1.4 2.1 2.8 mA
Input Switching Current IQS 1.7 2.5 3.5 mA
Shutdown Supply
IIN-SH VEN/UVLO = 0V (Shutdown mode) 7 18 μA
Current

Electrical Characteristics (continued)

ENABLE/UVLO (EN/UVLO)
EN/UVLO Rising
VEN_TH_R VEN/UVLO rising 1.22 1.25 1.27 V
Threshold
EN/UVLO Falling
VEN_TH_F 1.07 1.09 1.11 V
Threshold
EN/UVLO Bias Current IEN-BIAS VEN/UVLO = 0.5V 1.4 3.0 6.5 μA
EN/UVLO True VEN/UVLO rising 0.4 0.7 1.1 V
VENT
Shutdown Threshold Hysteresis 60 mV
VCC REGULATORS (INT-LDO AND EXT-LDO)
6V < VIN < 60V, IVCC = 1mA (VCC
5.00 5.15 5.30
supplied from INT-LDO)
VIN = 24V, IVCC = 0mA to 75mA, (VCC
4.95 5.10 5.25
supplied from INT-LDO)
VCC Output Voltage VCC V
6V < VEXTVCC < 24V, IVCC = 1mA (VCC
5.00 5.15 5.30
supplied from EXT-LDO)
VEXTVCC = 12V, IVCC = 0mA to 75 mA,
4.95 5.10 5.25
(VCC supplied from EXT-LDO)
VIN = 8.5V, VCC = 4V (VCC supplied from
80 110 135
VCC Output Current INT-LDO)
IVCC_LIMIT mA
Limit VEXTVCC = 8.5V, VCC = 4V (VCC
80 110 135
VIN = 4.5V, IVCC = 75mA (VCC supplied
370 750
from IN-LDO)
VCC Dropout Voltage VCC-DO mV
VEXTVCC = 4.9V, IVCC = 75mA (VCC
185 350
VCC Undervoltage VCC-UVR VCC rising 4.14 4.20 4.26
V
Threshold VCC-UVF VCC falling 3.74 3.80 3.86
EXTVCC Voltage Range 4.8 24.0 V
EXTVCC Switchover VEXTVCC rising 4.63 4.70 4.77
V
Voltage Hysteresis 0.24
OSCILLATOR (RT/SYNC)
RRT/SYNC = 350 kΩ 118.75 125.00 131.25
RRT/SYNC = Unconnected 332.5 350.0 367.5
Switching Frequency fSW kHz
RRT/SYNC = 110kΩ 380 400 420
RRT/SYNC = 19kΩ 2090 2200 2310
Synchronization 0.9 x 1.1 x
fSYNC kHz
Frequency Range fSW fSW
External Clock
CCOUPLING = 10pF 3 V
Amplitude
SYNC High Pulse-Width 100 ns
SYNC Low Pulse-Width 100 ns


SYNC Input-Leakage
ISYNC_LKG VRT/SYNC = 2.5V, TA= +25ºC -100 +100 nA
Current
GATE DRIVER
DH to BST On-
Source 100mA 0.8 1.2 2.1 Ω
Resistance
DH to LX On-Resistance Sink 100mA 0.3 0.6 1.0 Ω
DL to VCC On-
Source 100mA 0.8 1.2 2.1 Ω
Resistance
DL to PGND On-
Sink 100mA 0.3 0.6 1.0 Ω
Resistance
DH Minimum Controlled
tMIN_ON_DH 60 80 100 ns
On Time
DL Minimum
tMIN_ON_DL 60 80 100 ns
Guaranteed On Time
DH falling to DL rising, CDH-LX = 6nF,
tDT_HL 30
CDL-PGND = 6nF
Dead Time ns
DL falling to DH rising, CDH-LX = 6nF,
tDT_LH 30
CDL-PGND = 6nF
tHR DH rising, CDH-LX = 6nF 25
DH Transition Time ns
tHF DH falling, CDH-LX = 6nF 11
tLR DL rising, CDL-PGND = 6nF 25
DL Transition Time ns
tLF DL falling, CDL-PGND = 6nF 11
REFERENCE VOLTAGE (VREF)
VREF Output Voltage VREF IVREF = 0 to 1mA 2.465 2.500 2.535 V
Reference Current Limit IREF_LIM VREF = 2.45V 1.2 1.8 2.7 mA
CURRENT SENSE (CSP, CSN, ILIM)
CSP, CSN Common
0 (VIN - 2) V
Mode Voltage Range
CSP to CSN Input
VDIFF_CS VDIFF_CS = (VCSP - VCSN) -10 +100 mV
Operating Voltage
VILIM = 1.5V 48 50 52
CSP to CSN Regulation VILIM = 0.75V 23 25 27
VCSREG mV
Voltage Accuracy VILIM = 0.15V 3 5 7
VILIM = VREF 48 50 52
CSP Pin Current CSP source 200 1400 nA


VEN/UVLO = 0V, CSN sink 1.3 2.3
ICHG >
ICHGMAX/10, CSN 250 400 550
CSN Pin Current Charger on, VILIM source μA
= 0.15V to 1.5V
(see Note 3) ICHG <
ICHGMAX/10, CSN 470 700 1000
sink
Current Loop Error
Amplifier gmi (VCSP - VCSN) = VCSNEG ±25mV 275 480 685 μS
Transconductance
ILIM Input-Leakage
VILIM = 1.5V, TA = +25ºC -100 +100 nA
Current
CSN Undervoltage- (VIN - VCSN), rising 1.97 2.04 2.10
VCMUVLO V
Lockout Threshold (VIN - VCSN), falling 1.88 1.95 2.02
VCSPEAK = (VCSP - VCSN), VILIM = 1.5V 70 75 80
Overcurrent Threshold VCSPEAK mV
Hysteresis 10
Zero Cross Threshold VZX (VCSP - VCSN) falling 3 4.5 6 mV
PWM Ramp Amplitude VRAMP fSW = 125kHz to 2.2MHz 1.37 1.44 1.51 V
VOLTAGE REGULATION AMPLIFIER (FB)
FB Reference Voltage VFB_REG 1.237 1.250 1.263 V
FB Input-Leakage
VFB = 1.3V, TA = +25ºC -100 +100 nA
Current
Voltage Loop Error
GV 1.15 1.30 1.42 mV/mV
Amplifier Gain
INPUT SHORT-CIRCUIT PROTECTION (GATEN)
External nMOSFET (VGATEN -
4.65 5.0 5.5 V
Gate Drive Voltage VDCIN)
GATEN Drive Current IGATEN 17 20 23 μA
GATEN Active Pulldown
RGATEN_A IGATEN = 100mA 1.1 2.1 Ω
Resistance
GATEN Passive
RGATEN_P VEN/UVLO = 0V 400 800 Ω
Pulldown Resistance
GATEN-DCIN Threshold VGATEN_OK 3.20 3.55 3.90 V
GATEN OK Delay tGATEN_OK 15 ms
External nMOSFET (VDCIN - VIN) falling -111 -93 -75
Reverse-Blocking VREV mV
Threshold Hysteresis 20
External nMOSFET
CGATEN-DCIN = 10nF, VDCIN < (VIN -
Reverse-Blocking 100 180 ns
93mV) to (VGATEN - VDCIN) < 2V
Response Time
VIN to DCIN Reverse VDCIN = 0V, VIN = VEN/UVLO = 0V 170 260
μA
Leakage Current 60V 230 350


CHARGER FUNCTIONS
Constant Voltage (CV) VILIM = 1.5V, VFB rising 97.15 97.50 97.85 % of
VFB_CV
Mode FB Threshold Hysteresis 0.3 VFB_REG
Overvoltage Comparator VOVI rising 1.245 1.260 1.275

VOVI_TH V
Threshold (OVI) VOVI falling 1.235 1.250 1.265
ISMON Output-Voltage (VCSP - VCSN) = 50mV 1.41 1.50 1.59
V
Accuracy (VCSP - VCSN) = 10mV 0.21 0.30 0.39
ISMON Output
90 kΩ
Resistance
ISMON Output
100 kHz
Bandwidth
CHARGER TIMER (TMR)
CTMR = 33nF, TMR enabled 27
Charger Startup Delay tCH_START ms
TMR disabled 26
TMR Oscillator Upper
VTMR_H 1.47 1.50 1.53 V
Threshold
TMR Oscillator Lower
VTMR_L 0.94 0.96 0.98 V
Threshold
TMR Source/Sink
ITMR 8.9 10 10.9 μA
Current
TMR Disable Threshold VTMR_DIS VTMR > VTMR_DIS (powerup check only) 1.9 2.0 2.1 V
TMR Short to SGND/EP
VTMR_GND VTMR < VTMR_GND (powerup check only) 80 100 120 mV
Fault Threshold
Constant Current (CC) TMR
tFCHG 32767
Mode Timeout CYCLES
TMR Fault Blanking TMR
tBLANK_OFF 131071
Timeout CYCLES
CHARGER STATUS OUTPUTS (FLG1, FLG2)
FLG1/FLG2 Pulldown
IFLG1, IFLG2 = 10mA 500 mV
Voltage
FLG1/FLG2 Leakage
VFLG1, VFLG2 = 5.5V, TA = +25ºC -100 +100 nA
Current
IC THERMAL PROTECTION
Thermal Shutdown Temperature rising 160
°C
Threshold Hysteresis 10
Note 2: Electrical specifications are production tested at TA = +25ºC. Specifications over the entire operating temperature range are
guaranteed by design and characterization.
Note 3: CC mode charging current setting is calculated using this equation:
VCSREG
ICHGMAX =
RS
where RS is the current sense resistor.

Typical Operating Characteristics

(VDCIN = 24V, VSGND/EP = VPGND = 0V, RT/SYNC = unconnected (fSW = 350kHz), TA = +25°C, unless otherwise noted. All voltages
are referenced to SGND/EP, unless otherwise noted.)

Typical Operating Characteristics (continued)


Typical Operating Characteristics (continued)

Pin Configuration
MAX17701
EN/UVLO
DCIN
VREF
TOP VIEW
ILIM
OVI
IC1
18 17 16 15 14 13
GATEN 19 *SGND/EP 12 RT/SYNC
VIN 20 11 TMR
DH 21 10 COMP
M A X 17701
LX 22 9 FB
BST 23 8 FLG1
+
DL 24 7 FLG2
1 2 3 4 5 6
CSN
ISMON
PGND
CSP
EXTVCC
VCC
24-PIN TQFN
4mm x 4mm

Pin Description
PIN NAME FUNCTION
Power Ground. Connect to the return terminal of a VCC bypass capacitor placed close to IC, and
1 PGND the source terminal of external low-side nMOSFET. Refer to the MAX17701 EV kit data sheet for a
PCB layout example.
Internal LDO Output. Connect a minimum of 4.7μF/0805, low-ESR ceramic capacitor between VCC
2 VCC and PGND. VCC supports the IC internal control circuitry and gate drive current for external
nMOSFETs.
External Power-Supply Input for EXT-LDO. To power internal circuitry from an external supply,
3 EXTVCC apply a voltage between 4.8V and 24V to the EXTVCC pin. Connect a minimum of 1μF/0603, low-
ESR ceramic capacitor between EXTVCC and SGND/EP. Leave EXTVCC open when not used.
Inverting Input of the Current Loop Error Amplifier. The CSP and CSN pins measure the voltage
4 CSP
across the current sense resistor RS (see Figure 4).
Non-Inverting Input of the Current Loop Error Amplifier. Connect CSN to the node connecting the
5 CSN output capacitor and current sense resistor RS. Use Kelvin connections and route the CSP and
CSN traces as a differential pair (see Figure 4).
Output of Charging Current Monitor. Bypass ISMON with a 1nF low-ESR ceramic capacitor to
6 ISMON SGND/EP. The voltage on this pin is 30 times the voltage drop across the current sense resistor
RS .
Open-Drain Status Output Pins. Connect a 10kΩ pullup resistor each from VCC to the FLG1 and
7, 8 FLG2, FLG1
FLG2 pins. See the Charger Status Outputs (FLG1, FLG2) section for more details.
Feedback Input. Connect FB to the center node of a resistor-divider from the positive terminal of
9 FB supercapacitor to SGND/EP to set the output voltage. See the Setting the Output Voltage and
Voltage Regulation Loop (FB) section for more details.
Current Loop Error Amplifier Output. Connect a compensation network at this pin to stabilize the
10 COMP inner current loop. See the Current Regulation Loop Compensation (COMP) section for more
details.
Supercapacitor Safety Timer Setting Pin. A capacitor from TMR to SGND/EP sets the charging
11 TMR time in CC mode. Place the timer capacitor close to the TMR pin. Connect TMR to VREF to disable
the timer function. See the Charger Timers (TMR) section for more details.
Switching Frequency Programming/Synchronization Input. Connect a resistor from RT/SYNC to
SGND/EP to set the switching frequency between 125kHz to 2.2MHz. Leave RT/SYNC open for
12 RT/SYNC
the default 350kHz frequency. See the Setting the Switching Frequency and External Clock
Synchronization (RT/SYNC) section for more details.
CC Mode Charging Current Programming Input. Connect ILIM to the center node of a resistor
divider between VREF and SGND/EP to set the CC mode charging current. Connect to VREF for
13 ILIM
default CC mode charging current setting. See the CC Mode Charging Current Setting (ILIM)
section for more details.
2.5V Reference Output. Bypass VREF with a 0.1μF low-ESR ceramic capacitor to SGND/EP. See
14 VREF
the Reference Voltage (VREF) section for more details.
Overvoltage Detection Input. Connect OVI to the center node of a resistor divider from the output
15 OVI voltage node to SGND/EP. If VOVI exceeds VOVI_TH, charging is stopped and the charger enters
into the latched fault.
16 IC1 Internal Connection. Connect to SGND/EP
Enable/Undervoltage Lockout Input. Connect to the center node of a resistor divider between DCIN
and SGND/EP to set the input voltage at which the device turns on. Connect to SGND/EP to
17 EN/UVLO
shutdown the device. See the Setting the Input Undervoltage-Lockout Level (EN/UVLO) section for
more details.

Pin Description (continued)

PIN NAME FUNCTION
Input Supply Voltage Sense Pin. Bypass DCIN with a 0.1μF ceramic capacitor to PGND. The DCIN
and VIN pins measure the voltage across external nMOSFET. Use Kelvin connections and route
18 DCIN the VIN and DCIN traces as differential pair. Refer to the MAX17701 EV kit data sheet for the
recommended PCB layout and routing. If input short-circuit protection feature is not used, connect
DCIN to VIN close to IC.
Gate Drive Output for External nMOSFET. Bypass GATEN with a 2.2nF low-ESR ceramic
capacitor to DCIN. GATEN controls the gate of an external nMOSFET connected between DCIN
19 GATEN
and VIN to prevent supercapacitor discharge when DCIN is shorted to PGND. See the Input Short
Circuit Protection (GATEN) section for more details.
MAX17701 IC Supply Pin. Bypass VIN to PGND with a 0.1μF ceramic capacitor. Refer to the
20 VIN
MAX17701 EV kit data sheet for the recommended PCB layout and routing.
21 DH High Side nMOSFET Gate Driver Output. Connect to the gate of a high-side nMOSFET.
22 LX Switching Node Connection Input. Connect to the switching node of the converter.
Bootstrap Capacitor Connection Input. Connect a 0.1μF (min) capacitor between the BST and LX
23 BST pins. Connect a Schottky diode from VCC to the BST pin. See the Bootstrap Capacitor Selection
and Bootstrap Diode Selection sections for more details.
24 DL Low-Side nMOSFET Gate Driver Output. Connect to the gate of a low-side nMOSFET.
Signal Ground, Exposed Pad. Refer to the MAX17701 EV kit data sheet recommended method for
— SGND/EP
the PCB layout, routing, and thermal vias.

Functional Diagrams
MAX17701 Block Diagram
MAX17701
TMR
±10µA TIMER COUNT (TC)
OSCILLATOR
BST
TMR
CLK
S Q
OSCILLATOR DH
RT/SYNC VRAMP
125kHz-2200kHz R
PWM
CMLO VCC CONTROL LX
INPUT SHORT LOGIC
CHARGE CIRCUIT VCC
DCIN PUMP PROTECTION -93mV
AND COMPARATOR VIN ENOK
GATE
CONTROL DCIN
GATEN DL
CIRCUIT
PGND
VIN INT-LDO VCC
2.04V
VIN
CMLO
EXTVCC EXT-LDO BIAS SELECT CSN
PWM
COMPARATOR COMP
VRAMP
VCC
CURRENT-LOOP
ERROR AMPLIFIER
REFERENCE VIN gmi = 480µS
VREF
VOLTAGE
CSP
gmi VREFI
PEAK CURRENT
IEN-BIAS COMPARATOR CSN
EN/UVLO ENOK
1.25V
1 330µS ISMON
VILIM DIFFERENTIAL 90kΩ

ILIM 1/30 1.5
AMPLIFIER
FLG2
LIMIT FB
FLG1
CHARGER STATUS
FB VREFI ENOK LOGIC AND
GV FAULTS DETECTION
1.250V
(VFB_REG) TIMER COUNT (TC) OVI
VOLTAGE LOOP
ERROR 1.26V
AMPLIFIER
SGND/EP
GV = 1.30mV/mV OVERVOLTAGE
COMPARATOR

Detailed Description
The MAX17701 is a 4.5V to 60V, synchronous, step-down, supercapacitor charger controller designed to operate over a
-40°C to +125°C temperature range. It charges a supercapacitor with constant charging current with up to ±4% accuracy.
After the supercapacitor is charged, the device regulates the no load output voltage with ±1% accuracy. The MAX17701
supports a wide output-voltage range of 1.25V to (VDCIN - 2.1V).
The MAX17701 features a constant frequency, average current-mode control architecture shown in Figure 1. An internal
current loop consists of a transconductance amplifier gmi that senses the inductor current flowing through current sense
resistor RS as a voltage drop across the CSP and CSN pins. The current sense voltage is compared with a current
loop reference voltage (VREFI), which is set by the outer voltage loop error amplifier (GV) and limited by the voltage
programmed at the ILIM pin (VILIM). The voltage at the COMP pin is compared with a 1.44V (typ) ramp using a PWM
comparator to set the duty cycle of the converter. The required compensation to stabilize the current loop is applied at
the COMP pin using RZ, CZ, and CP. Under steady-state conditions, the inner current loop forces the voltage drop across
RS equal to VREFI.
The output voltage is monitored by the voltage error amplifier GV with a resistor divider (RTOP, RBOT) connected across
the positive and negative supercapacitor terminals with the center node connected to the FB pin. The voltage at the FB
pin (VFB) is compared with the FB reference voltage (VFB_REG). The voltage loop error amplifier sets the current loop
[ ]
VILIM VILIM
reference voltage (VREFI). VREFI is limited to 30
until VFB ≤ VFB_REG − 30 × G . This results in a constant current
V
[ ]
VILIM
through RS. When the output voltage rises, such that VFB > VFB_REG − 30 × G , VREFI; hence, the output load current
V
(ILOAD) proportionately reduces. The steady-state FB regulation voltage, and consequently the output voltage depend
on the load (ILOAD) connected across the supercapacitor, as given by the following equation:
[ ] [ ]
ILOAD × RS RTOP + RBOT
VOUT_LOAD = VFB_REG − GV
× RBOT
where,
VFB_REG = FB reference voltage
VOUT_LOAD = Steady-state output voltage for a given load current
ILOAD = Output load current of the charger
RTOP, RBOT = Output voltage feedback voltage divider resistors
GV = Voltage loop error amplifier gain (1.30mV/mV)
The MAX17701 provides input short-circuit protection, and prevents supercapacitor discharging for input supply-side
short-circuit events by means of an external nMOSFET. A safety timer (TMR) sets the maximum allowed CC mode
charging time to improve system safety. The device features an uncommitted comparator, which can be used to detect an
output overvoltage (OVI), which improves the safety of load circuitry, and prevents the supercapacitor from overcharging.
The switching frequency of the device can be programmed from 125kHz to 2.2 MHz using a resistor at the RT/SYNC
pin. The RT/SYNC also provides an external clock synchronization feature. Input undervoltage lockout is implemented
using the EN/UVLO pin. Two open-drain status outputs (FLG1 and FLG2) indicate the supercapacitor charger status.
The system current can be monitored using the ISMON pin.

1 VIN
tS = DH
M A X 17701 f SW
VRAMP
LX
DL
PWM
COMPARATOR
COMP L
RZ
CP
ILIM CZ
VILIM CURRENT-LOOP
1/30
ERROR AMPLIFIER
gmi = 480µS CSP R1
gmi VREFI C1 RS
LIMIT
CSN
VREFI VOUT
FB RTOP
GV 1.250V (TYP) CFB COUT SYSTEM

RBOT
(VFB_REG) SUPERCAPACITOR LOAD
VOLTAGE LOOP
ERROR AMPLIFIER
GV = 1.30mV/mV
Figure 1. Average Current Mode Control Loop
Power-Up/-Down Sequence
Figure 2 shows the MAX17701 power-up/-down sequence when DCIN voltage is applied/removed. When DCIN voltage
reaches a level such that VEN/UVLO is around 0.7V (VENT) the INT-LDO regulator is enabled and VCC rises. When VCC
rises above 4.2V (VCC-UVR) and VEN/UVLO rises above 1.25V (VEN_TH_R), the MAX17701 initiates EN/UVLO debounce
and checks for hardware faults. If there are no hardware faults (see the Hardware Faults section) detected at power-
up, the MAX17701 enables internal blocks during charger startup delay time tCH_START. After this delay, the charger
initiates LX switching and enters CC mode. In CC mode, the current is regulated at the CC mode charging current setting
(ICHGMAX). The safety timer counts the charging time in CC mode and if the output voltage reaches constant voltage
mode (VFB > VFB_CV) within the safety timer setting (tSC_TMR), the charger enters constant voltage (CV) mode and
continues to operate.
When VEN/UVLO falls below 1.09V (VEN_TH_F), the MAX17701 initiates a shutdown sequence with a debounce time of
2ms (typ). If the input voltage decreases such that (VIN - VCSN) falls below the current loop error amplifier undervoltage
lockout falling threshold 1.95V (VCMUVLO), the MAX17701 initiates a shutdown sequence immediately. The converter
stops switching, and GATEN is pulled down with 1.1Ω (RGATEN_A) to DCIN to turn off the external nMOSFET. The
COMP is pulled low after a debounce time of 100μs (typ).
If VEN/UVLO falls below 0.64V (VENT), the MAX17701 initiates a shutdown sequence with a debounce time of 10μs (typ).
During this shutdown sequence, the MAX17701 pulls down the GATEN with 1.1Ω (RGATEN_A) to DCIN to turn off the
external nMOSFET. See the Setting the Input Undervoltage-Lockout Level (EN/UVLO) section for more details.

POWER-UP TIMER COUNT STOPS POWER-DOWN

CHARGER ON AND
START GATEN ENABLE AND RESETS START
VDCIN TIMER COUNT START
VEN/UVLO t
VEN_TH_R (1.25V)
VEN_TH_F (1.09V)
VENT (0.7V RISING)
VENT (0.64V FALLING)
VCC t
VCC_UVR (4.2V)
t
tCH_START (27ms)
(VGATEN - VDCIN)
5V
6ms EN/UVLO t
DEBOUNCE
VTMR TIME (2ms)
1.5V
0.96V
tSC_TMR
t
24ms tTC < tSC_TMR
VOUT, VFB
VOUT
VFB_CV (1.219V) VFB
VFB = VFB_CV
IOUT or ICHG
CC MODE CV MODE t
ICHGMAX 80%
t
CHARGER OFF CHARGER ON CHARGER OFF
FLG1
HIGH-Z LOW LOW HIGH-Z

FLG2 t
HIGH-Z LOW HIGH-Z

HIGH-Z
t
NOTE: NOT TO SCALE
Figure 2. Charger Power-Up/-Down Sequence
Input Short-Circuit Protection (GATEN)

The MAX17701 provides gate drive output (GATEN) that drives a logic-level gate threshold external nMOSFET, which
turns off and prevents supercapacitor discharging for input supply short-circuit events. The GATEN is pulled up with
20μA (IGATEN) when VIN is 2.04V (VCMUVLO) above VCSN. If VGATEN does not reach 3.55V (VGATEN_OK) within 15ms
(tGATEN_OK), MAX17701 enters latched hardware fault.
Figure 3 depicts the MAX17701 behavior when DCIN is shorted to PGND. When VDCIN is 93mV (VREV) below VIN,

GATEN is pulled down with 1.1Ω (RGATEN_A) and the external nMOSFET is turned off within 100ns (typ). When VEN/
UVLO goes below 0.64V (VENT), the MAX17701 shuts down with 10μs (typ) debounce time. When DCIN-to-PGND short
is removed, the power-up sequence is initiated (see the Power-Up/Down Sequence section).
Measure the differential voltage between the source and drain terminals of the input short-circuit protection external
nMOSFET using a Kelvin connection. Shield DCIN, VIN and GATEN signal traces using static ground plane on either
side of the traces and on the adjacent layers of PCB. Place the 0.1μF decoupling capacitors on DCIN and VIN pins close
to MAX17701. The MAX17701 EV kit depicts the recommended layout and routing of DCIN, VIN and GATEN traces.
When the input short-circuit protection is not used, connect a 2.2nF capacitor between GATEN and DCIN, and short
DCIN to VIN.
EXTERNAL nMOSFET
TURNS OFF CHARGING STOPS VGATEN_OK CHECK
DCIN SHORTED TO PGND CHARGING STARTS
DCIN SHORT TO PGND

FAULT RECOVERY
VDCIN
VEN/UVLO t
VEN_TH_R (1.25V)
VENT (0.7V)
t
(VDCIN - VIN) VD OF EXTERNAL
10µs nMOSFET
0mV
t
VREV (-93mV)
(VGATEN - VDCIN) tREV (100ns)

5V 5V
2V VGATEN_OK (3.55V)
6ms tGATEN_OK t
VCC (15ms)
VCC_UVR (4.2V)
VLX t
tCH_START
(27ms)
t
NOTE: NOT TO SCALE
Figure 3. Input Short-Circuit Protection and Recovery Timing Diagram

Charger Operation
MAX17701 offers constant current (CC) mode and constant voltage (CV) mode for charging a supercapacitor. In CC
mode, the charging current is regulated to the CC mode charging current (ICHGMAX) proportional to VILIM. The safety
timer starts counting when the device enters CC mode. When VFB goes above 1.219V (VFB_CV) within the CC mode
timeout period (tSC_TMR), the charger enters CV mode and the safety timer stops counting (see Charger Timers (TMR)
section). The safety timer count resets when the device enters CV mode. In CV mode, the device continues to charge
the supercapacitor until VFB reaches 1.250V (VFB_REG). The charger regulates VFB at VFB_REG at no load. When VFB
drops below 1.215V (VFB_CV), the charger exits CV mode, enters CC mode, and the timer count restarts.

Charger Timers (TMR)

The MAX17701 offers a programmable timer feature to provide additional safety to the supercapacitor and the connected
load. Connect a capacitor from TMR to SGND/EP to enable the timer feature. Connect TMR to VREF to disable the timer
feature. The timer counts the charging time in CC mode. If VFB does not reach 1.219V (VFB_CV) within CC mode timeout
period (tSC_TMR), the charger turns off. The charger restarts after 4 times tSC_TMR. The MAX17701 supports 470pF to
10μF capacitance on TMR, translating into a CC mode timeout period range of 1.5 second to 9 hours.
The safety timer is programmed based on maximum supercapacitor value (CSUP), output voltage (VOUT), and CC mode
charging current setting (ICHGMAX). Refer to the CC Mode Charging Current Setting (ILIM) section.
Choose the required safety timer period using the following equation:
CSUP × VOUT
tSC_TMR ≥ I
CHGMAX − ILOAD
where ILOAD is the system load during the supercapacitor charging period
Select ICHGMAX ≥ 1.5 × ILOAD to ensure the charger enters CV mode
Use the following equation to calculate CTMR for the required tSC_TMR:
( ) ( )
tSC_TMR ITMR
CTMR ≥ 1.15 × 2 × t - 1.2 × 10 − 6 × V
FCHG TMR_H − VTMR_L
where
tSC_TMR = Desired safety timer timeout setting in seconds
CTMR = TMR capacitor in Farad
tFCHG = Number of TMR cycles in CC mode (32767)
VTMR_H = TMR oscillator upper threshold (1.5V)
VTMR_L = TMR oscillator lower threshold (0.96V)
ITMR = TMR pin source/sink current (10μA)
Charger Status Outputs (FLG1, FLG2)

The MAX17701 features two open-drain status output pins (FLG1 and FLG2) to indicate the status of the charger. Table
1 shows the status flag summary.
Table 1. Status Output Indications
CHARGER STATUS FLG (FLG2
FLG2 FLG1 CHARGER STATUS
and FLG1)
Open drain in Hi- Open drain in Hi-
11 Charger Off
Impedance (1) Impedance (1)
Open drain in Hi-
10 Open drain pulls low (0) CC Mode
Impedance (1)
00 Open drain pulls low (0) Open drain pulls low (0) CV Mode
Open drain in Hi- Hardware Fault or Safety Timer
01 Open drain pulls low (0)
Impedance (1) Timeout

Hardware Faults
The MAX17701 features hardware fault checks at power-up and during normal operation. Table 2 provides various fault
detection features available and their behaviors in MAX17701.
Table 2. Protection Under System Faults
FAULT CONDITION FAULT MONITOR STATE FAULT BEHAVIOR
RT/SYNC to SGND/EP short
GATEN to DCIN short
TMR pin left unconnected
TMR to SGND/EP short Power-up check
VREF to SGND/EP short
Output overvoltage (VOVI > Latched fault, need to recycle power or EN/UVLO to restart
VOVI_TH) the device
(VGATEN - VDCIN) <

VGATEN_OK
Continuous, during normal
VREF < 1.95V or VREF > 3.05V
operation
Output overvoltage (VOVI >
VOVI_TH)
Linear Regulator (VCC and EXTVCC)

The MAX17701 integrates two internal low-dropout (LDO) linear regulators INT-LDO and EXT-LDO that power VCC.
VCC powers gate drivers and internal control circuitry. INT-LDO is powered from VIN and turns on when VEN/UVLO
> VENT (0.7V). EXT-LDO is powered from EXTVCC. At any time, only one of these two linear regulators operates,
depending on the EXTVCC voltage. If VEXTVCC > 4.7V (typ) then VCC is powered from EXT-LDO. If VEXTVCC <
4.46V(typ), then VCC is powered from INT-LDO. Powering VCC from EXTVCC reduces on-chip dissipation and increases
efficiency at higher input voltages. Connect EXTVCC to VOUT for applications with VOUT ≥ 4.8V. The maximum voltage
limit on EXTVCC is 24V. Bypass EXTVCC with a 1μF ceramic capacitor to SGND/EP. Leave EXTVCC open when not
used. Bypass VCC to PGND with at least a 4.7µF/0805, low-ESR ceramic capacitor.
Reference Voltage (VREF)

The MAX17701 provides a 2.5V reference voltage on the VREF pin with ±1.4% accuracy. VREF can be used to program
VILIM to set the CC mode charging current (ICHGMAX). Connect a minimum 0.1μF low-ESR ceramic capacitor between
VREF and SGND/EP. See the CC Mode Charging Current Setting (ILIM) section for more details.
Setting the Switching Frequency and External Clock Synchronization (RT/SYNC)

The switching frequency of the device can be programmed from 125kHz to 2.2MHz by using a resistor (RRT/SYNC)
connected from the RT/SYNC pin to SGND/EP. RRT/SYNC can be calculated using the following equation:
44830
RRT/SYNC = f − 1.205
SW
Where RRT/SYNC is in kΩ and fSW is in kHz. Leave the RT/SYNC pin unconnected to operate the device at 350kHz
default switching frequency.
The MAX17701 can be synchronized to an external clock coupled to the RT/SYNC pin through a 10pF ceramic capacitor.
The external clock is detected after checking the rising edge for 112 cycles of the internal clock (set by RT/SYNC). If
the external clock frequency is within the allowed SYNC frequency range (±10% of nominal internal clock frequency), the
device stops switching for 2 switching time periods and then restarts with an external clock. When the external clock is
removed, the device stops switching for 10 switching time periods and then restarts with an internal clock.
The minimum external clock pulse-width should be greater than 100ns. The off-time duration of the external clock should
be at least 100ns.

Peak Current-Limit
The MAX17701 provides a cycle-by-cycle overcurrent protection by limiting the peak current-sense voltage (VCSP
- VCSN) across the current sense pins. When an overcurrent event ((VCSP - VCSN) > VCSPEAK) is detected, the
overcurrent comparator in the MAX17701 terminates the DH pulse and limits the peak current. The overcurrent fault is
not latched.
Charging Current Monitoring (ISMON)

The output charge current can be monitored by observing the voltage at the ISMON pin. Connect a 1nF ceramic capacitor
on ISMON to filter out the switching frequency component in the ISMON voltage. The charging current is given by the
following equation:
VISMON
ICHG = 30 × R
S
where,
ICHG = Charging current
VISMON = Voltage at the ISMON pin
RS = Current-sense resistance
Thermal-Shutdown Protection
Thermal-shutdown protection limits junction temperature of the device. When the junction temperature of the device
exceeds +160ºC, an on-chip thermal sensor shuts down the device, allowing the device to cool. The device turns on after
the junction temperature reduces by 10ºC. Carefully evaluate the total power dissipation to avoid unwanted triggering of
the thermal shutdown during normal operation (see the Device Power Dissipation section).

Applications Information
Inductor Selection
Three key inductor parameters must be specified for operation with the device: inductance value (L), DC resistance
(RDCR), and inductor saturation current (ISAT).
The required inductance is calculated based on the inductor current ripple ratio (LIR), i.e., ratio of peak-to-peak ripple
current (ΔIL) to CC mode charging current (ICHGMAX). A good compromise between size and loss is an LIR of 0.3.
The inductance value (L) is given by the higher value of the two calculated inductances:
VOUT x (1-D)
L1 = LIR × I
CHGMAX x fSW
VOUT
L2 = 600000 × I
CHGMAX
where:
VOUT = Desired voltage across supercapacitor
ICHGMAX = CC mode charging current
D = Duty cycle of the converter, VOUT/VIN
VIN = Nominal input voltage
fSW = Switching frequency in Hz
Select an inductor that is nearest to the calculated value. The inductor RMS-current rating should be more than the CC
mode charging current. Select a low-loss inductor with acceptable dimensions and the lowest possible DC resistance.
The saturation current rating (ISAT) of the inductor must be high enough to ensure that saturation can occur only above
the overcurrent threshold corresponding to VCSPEAK.
Output Capacitor Selection

Supercapacitors have significant equivalent series resistance (ESRSUP). The switching ripple component of charger
output current flows into this ESRSUP and results in a large output-voltage ripple. To reduce the voltage ripple across the
supercapacitor, additional X7R ceramic capacitors and/or low-ESR POSCAP capacitors can be used at the output of the
charger.
X7R ceramic output capacitors are preferred due to their stability over temperature in industrial applications. For higher
values of output capacitance, low-ESR POSCAP capacitors can be used in parallel with ceramic capacitors.
Calculate the required output capacitance (COUT) based on the following equation:
25 × ICHGMAX
COUT = fSW× VOUT
where:
ICHGMAX = CC mode charging current setting
VOUT = Desired voltage across the supercapacitor
Derating of ceramic capacitors with DC-bias voltage must be considered while selecting the capacitors, using the
manufacturer data sheet. The selected output capacitor COUT_SEL and its equivalent series resistance (ESRCOUT) affect
the output-voltage ripple (ΔVOUT). Estimate the resultant ΔVOUT using the following equation:
(
ΔVOUT ≈ ΔIL × ESRCOUT + 8 × f
1
SW × COUT_SEL )
where ΔIL is the inductor peak-to-peak ripple current.

In applications with a long cable between the charger output and the supercapacitor, to dampen the oscillations caused
by the interaction of the cable inductance with the low ESR output capacitors of the charger circuit, an electrolytic
capacitor with appropriate ESR (equivalent series resistance) may be used. Choose an electrolytic capacitor equal to
1.5 times the value of COUT_SEL. Select an electrolytic capacitor with an equivalent series resistance (ESRELCO) as
calculated below:
√
LCABLE
ESRELCO = COUT_SEL
where LCABLE is the output cable inductance.
Input Capacitor Selection

The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on
the input caused by the switching converter. Calculate the required input capacitance at VIN (CVIN) using the following
equation:
CVIN =
ICHGMAX × D × 1 − D( )
η × fSW × ∆VIN
where:
VOUT
D= V is the duty ratio of the converter
IN
ΔVIN = Allowable input-voltage ripple
η = Efficiency of the converter
ICHGMAX = CC mode charging current
Choose ΔVIN ≤ 0.5V to minimize voltage ripple across the external nMOSFET and to provide robust operation during
input short-circuit events.
The input capacitor RMS current (IRMS) is calculated using the following equation:
IRMS = ICHGMAX × √VOUT × [VIN − VOUT]

VIN
Choose low-ESR ceramic input capacitors that exhibit less than a +10°C temperature rise at IRMS for optimal long-term
reliability. X7R capacitors are recommended in industrial applications for their temperature stability. Derating of ceramic
capacitors with DC-bias voltage must be considered while selecting the capacitors using the manufacturer data sheet.
Choose an electrolytic capacitor at DCIN in order to prevent the DCIN voltage from being less than -0.3V during input
short events. An electrolytic capacitor also provides the damping for potential oscillations caused by inductance of the
longer input power path and input ceramic capacitor (CVIN). Additionally, if required, add a Schottky diode at DCIN in
parallel with the electrolytic capacitor.
Operating Input-Voltage Range

The following equations are used to calculate the operating input-voltage range for a given output voltage and CC mode
charging current setting. The minimum operating input voltage on the DCIN pin is given by the higher value from the two
calculated voltages:
VDCIN(MIN1) =
(( (
VDCIN(MIN2) = VOUT + 2.1V
(
(
VOUT + ICHGMAX × RDS_ON LS + RDCR MAX
( ) ( )
1 − 1.05 × fSW × tDT_HL + tMIN_ON_DL MAX

( )
) +I
) ))
(
CHGMAX × RDS_ON(HS) − RDS_ON(LS)
)
)
where:

VDCIN(MIN1), VDCIN(MIN2) = Minimum operating input voltages; the higher of the two values is the minimum operating
input voltage (VDCIN(MIN))
VOUT = Desired regulation voltage across the supercapacitor
ICHGMAX = CC mode charging current setting
RDCR(MAX) = Worst-case DC resistance of the inductor in Ω
RDS_ON(HS), RDS_ON(LS) = Maximum on-state resistances of high-side and low-side MOSFETs in Ω, respectively
tDT_HL = Dead time (30ns)
tMIN_ON_DL(MAX) = Worst-case DL minimum controlled on-time (100ns).
The maximum operating input voltage on the DCIN pin is calculated as follows:
VOUT
VDCIN(MAX) =
(1.05 × fSW × tMIN_ON_DH(MAX))
where tMIN_ON_DH(MAX) is the worst-case DH minimum controlled on-time (100ns).
CC Mode Charging Current Setting (ILIM)

The CC mode charge current setting involves setting up a voltage on the ILIM pin (VILIM) and choice of current sense
resistor RS. Selection of RS involves a trade-off between power loss and charging current accuracy. The best MAX17701
charging current accuracy is obtained with a voltage drop (VCSP - VCSN) of 50mV across RS. (VCSP - VCSN) can be
reduced at the expense of the charging current accuracy to reduce power loss. The recommended range for voltage
across RS is 25mV (±8% charging current accuracy) to 50mV (±4% charging current accuracy). RS can be calculated
using the following equation:
RS =
(VCSP − VCSN)
ICHGMAX
Once RS is selected, VILIM can be calculated using the following equation:

VILIM = 30 × RS × ICHGMAX
A resistor divider from VREF to SGND/EP can be used to program VILIM, as shown in Figure 4. The resistor-divider
values are calculated as follows:
RLIM1 = 20 × (VREF − VILIM)kΩ
RLIM2 = 20 × VILIMkΩ
The permitted voltage range for the VILIM setting is 0.15V to 1.5V. The MAX17701 can be set to the default ICHGMAX
setting corresponding to (VCSP - VCSN) = 50mV across RS by connecting ILIM to VREF.
Connect an R-C filter in the current-sense signal path as shown in Figure 4 to attenuate switching noise while preserving
accuracy and bandwidth. The R-C filter corner frequency should be 5 times the switching frequency. The recommended
filter resistance (R1) is 40Ω for minimal impact on the current-sense accuracy. The filter should be placed close to the
CSP and CSN pins. Calculate the value of filter capacitor C1 using the following equation:
1
C1 = 2πxR1x5xf
SW
where fSW = Switching frequency in Hz

VIN
DH
ICHG
L RS
LX
COUT SUPERCAPACITOR SYSTEM
LOAD
VREF
DL
M A X 17701
RLIM1
PGND
ILIM ICHG
CSP RS
RLIM2 R1
C1
SGND/EP CSN
To CSP TO CSN
CURRENT-SENSE RESISTOR LAYOUT
Figure 4. Current-Sense Circuit
Setting the Input Undervoltage-Lockout Level (EN/UVLO)

The MAX17701 offers an adjustable input undervoltage-lockout level using the EN/UVLO pin. Pulling the EN/UVLO pin
below 1.09V (typ) stops charger operation. Pulling EN/UVLO below 0.64V (typ) causes the MAX17701 to shut down. In
this state, the device draws IIN-SH (7μA) quiescent current. Figure 5 shows the recommended EN/UVLO configuration
based on the required input-voltage range.
Connect EN/UVLO to the center node of a resistor divider from the DCIN to SGND/EP to set the input voltage at which
the device turns on. Choose R1 as follows:
R1 ≤ (10000 × VDCIN(MIN))
where VDCIN(MIN) is the voltage at which the device is required to turn on.
Calculate the value of R2 using the following equation:
VEN_TH_R × R1
R2 = (V
DCIN(MIN) − VEN_TH_R + (IEN − BIAS × R1))
where:
IEN-BIAS = Internal bias pullup current on the EN/ULVO pin (3μA)
VEN_TH_R = EN/UVLO rising threshold voltage (1.25V)
VDCIN(MIN) TO VDCIN(MAX)
DCIN
MAX17701
R1
IEN-BIAS
VDCIN(MAX)
USE D1 WHEN > 4.4 EN/UVLO
VDCIN(MIN)
D1
4.7V R2
(OPTIONAL)
SGND/EP
Figure 5. Setting Input-Undervoltage Lockout

Current Regulation Loop Compensation (COMP)

The MAX17701 features a COMP pin to tune the current loop control performance of the average current mode controller.
Refer to Figure 1 for a depiction of the compensation network on the COMP pin using RZ, CZ, and CP. The choice of the
compensation component values depends on the chosen inductor (L) and its DC resistance (RDCR), switching frequency
(fSW), current-sense resistor (RS), maximum operating input voltage (VDCIN(MAX)), the desired regulation voltage across
supercapacitor (VOUT), the worst-case maximum ESR of the supercapacitor (ESRSUP), the maximum on-resistances of
the step-down converter nMOSFETs (RDS_ON(HS) and RDS_ON(LS)) and the maximum cabling and contact resistances
(RCONNECTION) in the charging path.
Calculate the compensation resistor RZ using the following equation:
3000 × L × fSW
RZ = V
DCIN(MAX) × RS
Calculate the compensation capacitor CZ using the following equation:
0.8 × L
CZ = R × R
Z E
where
RE = [RDCR + RS + RDS_ON(HS) × DMIN + RDS_ON(LS) × (1 − DMIN) + ESRSUP + RCONNECTION]
VOUT
DMIN = V
DCIN(MAX)
Calculate the high frequency pole capacitor CP using the following equation:
0.35
CP = R × f
Z SW
Setting the Output Voltage and Voltage Regulation Loop (FB)

The MAX17701 features a FB pin to regulate the voltage across the supercapacitor to a desired level. Connect a
feedback resistor divider (RTOP and RBOT) with a compensating capacitor (CFB), as depicted in Figure 1. The choice
of feedback components depends on the desired regulation voltage across the supercapacitor (VOUT), the chosen
switching frequency (fSW), and the operating input-voltage range (VDCIN(MAX) and VDCIN(MIN)).
Calculate RTOP and RBOT using the following equations:
RTOP = 10 × VOUT kΩ
RTOP
RBOT = kΩ
( )
VOUT
-1
VFB_REG
where VFB_REG is the FB reference voltage.

Calculate CFB using the following equation:
1
CFB =
1.5 × 106 × RPAR
where
RTOP × RBOT
RPAR = R in kΩ.
TOP + RBOT

Output Overvoltage Protection (OVI)

The MAX17701 provides an overvoltage detection comparator at the OVI pin. The overvoltage level for the
supercapacitor can be set by connecting OVI to the midpoint of a resistor-divider from output to SGND/EP as shown in
Figure 6.
Select R1 in the range of 50kΩ to 100kΩ.
Calculate resistor R2 from the following equation:
R1
R2 =
( )
VOUT_OV
−1
VOVI_TH
where
VOUT_OV = Overvoltage level of the supercapacitor
VOVI_TH = Overvoltage comparator threshold (1.26V)
VOUT
R1
OVI
R2
SGND/EP
Figure 6. Setting the Supercapacitor Overvoltage Level
Bootstrap Capacitor Selection

Bootstrap capacitance (CBST) value is determined by the selection of the high-side nMOSFET(s). Choose CBST using
the following equation:
∆ QG
CBST≥ ∆ V
BST
where:
ΔQG = Total gate charge of the high-side nMOSFET(s)
ΔVBST = Voltage variation allowed on the high-side nMOSFET(s) driver after turn-on
Choose ΔVBST ≤ 100mV to select CBST. The bootstrap capacitor should be a low-ESR ceramic capacitor. A minimum
value of 0.1μF is recommended.
Bootstrap Diode Selection

Select a Schottky diode with the following ratings:
● Reverse voltage rating ≥ (Maximum input operating voltage + 10V)
● Average forward current rating ≥ 1A
Choose a diode with low forward-voltage drop and low reverse-leakage current across the operating temperature range.

Input Short-Circuit Protection External nMOSFET Selection

The MAX17701 is designed to control an external logic level nMOSFET that turns Off in less than 100ns and isolates
the VIN node from input short-circuit events. This feature prevents discharge of the supercapacitor into the input during
input (DCIN) short-circuit events. The external nMOSFET used for this feature only turns On once during power-up
and turns Off during shutdown; therefore, the nMOSFET does not need to be optimized for switching performance.
This external nMOSFET should therefore be selected with low RDS-ON for low forward path conduction losses. The
MAX17701 supports external nMOSFETs with gate charge up to 250nC at VGS = 3.9V. Using larger values results in a
gate charging time larger than 15ms (tGATEN_OK) and causes the MAX17701 to enter a latched Fault condition.
Step-Down Converter nMOSFET Selection

The MAX17701 drives two external logic-level nMOSFETs to implement the step-down converter high-side and low-side
switches. These nMOSFETs must be logic-level compatible with guaranteed on-resistance specifications provided at
VGS = 4.5V. The key selection parameters to choose these MOSFETs include:
● On-resistance (RDS-ON)
● Maximum drain-to-source voltage (VDS(MAX))
● Miller Plateau voltage on the nMOSFET Gate (VMIL)
● Total gate charge (QG)
● Output capacitance (COSS)
● Power-dissipation rating and package thermal resistance
● Maximum operating junction temperature
For the step-down converter, nMOSFETs should be chosen in such a way that the switching losses and conduction
losses are balanced and optimized. The duty cycles for the high-side and low-side external nMOSFETs can be calculated
as follows:
VOUT
D= V
IN
High-side nMOSFET duty cycle: D
Low-side nMOSFET duty cycle: 1 - D
High-side nMOSFET losses can be estimated using the following formula:
PHS-MOSFET = PHS-MOSFET_CONDUCTION + PHS-MOSFET_SWITCHING
PHS − MOSFET_CONDUCTION = ICHG2 × RDS − ON(HS) × D
([ ] ] + [ 12 × COSSLS × VIN2])
VIN × ICHG QSW × RDR
PHS − MOSFET_SWITCHING = fSW × 2
× V −V
CC MIL
[1
+ [VIN × Qrr]+ 2 × COSSHS × VIN2
where:
ICHG = Charging current
QSW = Switching charge of the high-side nMOSFET from the nMOSFET data sheet,
RDR = Sum of the DH pin driver pullup resistance and the high-side nMOSFET internal gate resistance,
VMIL = VGS of the high-side nMOSFET that corresponds to ID = ICHGMAX on the VGS vs. ID curve in the nMOSFET data
sheet
Qrr = Reverse-recovery charge of low-side nMOSFET(s) body diode
COSSHS = Effective output capacitance of the high-side nMOSFET(s)
COSSLS = Effective output capacitance of the low-side nMOSFET(s)
Low-side nMOSFET losses can be estimated using the following formula:
(
PLS − MOSFET = ICHG2 × RDS − ON(LS) × (1 − D) + VD × ICHG × tDT × fSW × 2 )
where:
VD = Forward-drop of the low-side nMOSFET(s) body diode

tDT = Dead time (30ns)

Take RDS-ON variation with respect to temperature into account while calculating the power losses and ensure that
the losses of each nMOSFET do not exceed their power rating and operate within a safe junction temperature rating.
When parallel nMOSFETs are used, it is recommended to use appropriate independent series gate resistors for each
nMOSFET to account for gate charge variation from one nMOSFET to another.
Device Power Dissipation

The MAX17701 must dissipate losses due to quiescent current consumption and the internal gate driver.
If VCC is powered from VIN, use the following equation to calculate the approximate IC losses:
[
PMAX17701 = VIN × [QG × fSW] + IQNS ]
When VOUT is used to power VCC by connecting the EXTVCC pin to an output voltage greater than 4.8V, use the
following equation to calculate the approximate IC losses:
[
PMAX17701=VEXTVCC × [QG × fSW] + IQNS ]
where:
QG = Total gate charge of high-side and low-side nMOSFETs,
IQNS = Input Quiescent current (2.1mA)
Calculate the junction temperature using the following equation and ensure that it does not exceed +125°C.
TJ = TA(MAX) + (θJA × PMAX17701)
where:
TJ = Junction temperature
PMAX17701 = Power loss in the device
θJA = Junction-to-ambient thermal resistance
TA(MAX) = Maximum ambient temperature
PCB Layout Guidelines

Careful PCB layout is critical to achieve low losses and low EMI emissions. Use the following guidelines for PCB layout:
● Place ceramic input filter capacitors as close as possible across the drain of the high-side nMOSFET and source of
the low-side nMOSFET.
● Use Kelvin connections and route the VIN and DCIN traces from input short-circuit protection nMOSFET source and
drain terminals as a differential pair and connect to VIN and DCIN pins of the device. Place VIN and DCIN bypass
capacitors close to VIN and DCIN pins, respectively.
● Place VCC and EXTVCC bypass capacitors and the BST capacitor near the respective pins.
● Place GATEN-to-DCIN bypass capacitor close to the GATEN, DCIN pins of the device.
● Place the bootstrap capacitor close to the BST and LX pins of the device.
● Route the bootstrap diode connections from the VCC capacitor and to the bootstrap capacitor as short as possible to
minimize the loop inductance.
● Route switching traces (BST, LX, DH, and DL) away from sensitive signal traces (RT/SYNC, COMP, CSP, CSN and
FB).
● The gate current traces must be short in length. Use multiple vias to route these signals if routed from one layer of the
PCB to another layer.
● Route current-sense traces as a differential pair to minimize the loop inductance and avoid differential noise.
● Place a current-sense filter resistor and capacitor near the CSP and CSN pins.
● Place feedback and compensation components close to the device and connect to the SGND/EP copper area.
● Place all power components on the top side of the board and run the power-stage currents using traces or copper fills
on the top side only without adding vias wherever possible.

● Keep the power traces and load connections short. Use multilayer, thick copper PCBs (2oz or higher) to enhance
efficiency and minimize trace inductance and resistance.
● Allocate a large PGND copper area for the output node and connect the return terminals of the input filter capacitors,
output capacitors, and the source terminals of the low-side nMOSFET(s) to that area.
● Refer to the MAX17701 EV kit data sheet for recommended PCB layout and routing.
Typical Application Circuit
20A Supercapacitor Charger
GATEN
7.1V TO 60V INPUT
Q1
Q1: SIR170DP-T1-RE3
L1: XAL1010-222ME
R13 C2
C1 C1: EEV-FK2A680Q
64.9kΩ 7 x 4.7μF
68μF C2: GRM31CZ72A475KE11
100V C3: GRM32ER71A476KE15
100V C13 C14
Z1 R14 C4: 6TCE220MI
4.7V 14kΩ 0.1μF 0.1μF
C11:GRM21BR71C475KE51
100V 100V
GATEN D1: DFLS1100-7
C17 fSW: 350kHz
2.2nF FOR VDCINMAX = 60V: Q2–Q5: SIR826ADP-T1-GE3
VCC FOR VDCINMAX = 48V:
R11 GATEN DCIN VIN
EN/UVLO Q2–Q3: NVMFS5C673NLWFAFT1G
ILP 40Ω
CSP Q4–Q5: NVMFS5C645NLWFAFT1G
BST
C9 D1
ILN
ILP
2.2nF
Q2,
ILN DH
Q3
CSN
C5 VOUT
ILIM 5V/20A
0.47μF L1 IOUT
VOUT RS
VREF LX
C8 2.2μH
2.5mΩ
R7 0.1μF
93.1kΩ SUPERCAPACITOR SYSTEM
M A X 17701 Q4, C3 C4 200F, 15mΩ
OVI DL LOAD
VOUT Q5 2 x 47μF 220μF
R8 10V 6.3V
28.7kΩ
C16 EXTVCC
PGND
1μF VOUT
R1
VCC 52.3kΩ
FB
VCC
C11
4.7μF ISMON
C12 R2
47nF 17.4kΩ
ISMON
C15
COMP 1nF
R6
RT/SYNC TMR IC1 SGND/EP FLG2 FLG1
15.8kΩ C10
68pF FLG2 FLG1
C7 C6
4.7nF 33nF R15 R16
10kΩ 10kΩ VCC
Figure 7. 5V/20A Supercapacitor Charger

Typical Application Circuit (continued)
GATEN
5.5V TO 36V INPUT
Q1
Q1: NTMFS5H419NL
R13 C2 Q2: NTMFS5C468NL
49.9kΩ C1
5 x 4.7μF Q3, Q4: NTMFS5C456NL
47μF
50V L1: XAL8080-102ME
50V C14
Z1 R14 C13 C1: EEEFK1H470P
4.7V 15kΩ 0.1μF 0.1μF C2: GRM31CR71H475KA12
100V 100V C3: GRM32ER71A476KE15
GATEN
C16 C4: 6TCE220MI
2.2nF C11:GRM21BR71C475KE51
D1: DFLS1100-7
VCC
R11 fSW: 350kHz
EN/UVLO GATEN DCIN VIN
ILP 40Ω
CSP BST
C9 D1
ILN
ILP
2.2nF
ILN DH Q2
CSN VOUT
C5 2.5V/20A
ILIM IOUT
0.47μF L1
VOUT RS
VREF LX
C8 1μH 2.5mΩ
R7 0.1μF
93.1kΩ SUPERCAPACITOR SYSTEM
M A X 17701 Q3, C3 C4 400F, 8mΩ
OVI DL LOAD
Q4 3 x 47μF 2 x 220μF
R8 10V 6.3V
78.7kΩ
EXTVCC PGND
R1 VOUT
VCC 24.9kΩ
FB
VCC
C11
ISMON C12 R2
4.7μF
47nF 24.9kΩ
ISMON
C15
COMP
1nF
R6 FLG1
RT/SYNC TMR IC1 SGND/EP FLG2
12.1kΩ C10
82pF FLG2 FLG1
C7 C6
3.3nF 15nF R15 R16
10kΩ 10kΩ VCC
Figure 8. 2.5V/20A Supercapacitor Charger

Ordering Information
PART NUMBER TEMPERATURE RANGE PIN-PACKAGE
MAX17701ATG+ -40ºC to +125ºC 24 TQFN-EP
MAX17701ATG+T -40ºC to +125ºC 24 TQFN-EP
+ Denotes a lead(Pb)-free/RoHS-compliant package.
T Denotes tape-and-reel.

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 4/20 Initial release —

Updated the General Description, Benefit and Features, Simplified Application
Circuit, Absolute Maximum Ratings, Electrical Characteristics, Detailed Description, 1–2, 6, 13,
1 6/20 Operating Input-Voltage Range, CC Mode Charging Current Settings (ILIM), Step- 21–23,
Down Converter nMOSFET Selection, and Typical Application Circuit (Figures 7 and 27, 29–30
8) sections
Updated the Pin Description, Charger Timers, PCB Layout Guidelines and Typical
8, 11, 17–18,
2 11/20 Application Circuit (Figures 7 and 8) sections, and Table 1; replaced TOC01 with
27–29
new TOC01a and TOC01b in the Typical Operating Characteristics section
Updated the General Description, Benefits and Features, Simplified Application
Circuit, Absolute Maximum Ratings, Electrical Characteristics, Pin Configuration, Pin
Description, MAX17701 Block Diagram, Detailed Description, Power-Up/-Down
Sequence, Input Short-Circuit Protection (GATEN), Charger Operation, Charger 1–2, 4–6, 9,
3 3/21 Timers (TMR), Hardware Faults, Linear Regulator (VCC and EXTVCC), Peak 11–24, 26–27,
Current-Limit, Inductor Selection, Operating Input-Voltage Range, CC Mode 29–31
Charging Current Setting (ILIM), PCB Layout Guidelines, and the Typical Application
Circuit sections; updated TOC14 in Typical Operating Characteristics section; added
the Charger Status Outputs (FLG1, FLG2) and Bootstrap Diode Selection sections
Updated Electrical Characteristics, Pin Description, Detailed Description, Typical
Operating Characteristics TOC1a, TOC1b, TOC2, TOC5, TOC7, TOC12, TOC17,
Input Short-Circuit Protection (GATEN), Inductor Selection, Output Capacitor
Selection, Input Capacitor Selection, Operating Input-Voltage Range, CC Mode 5, 8, 9, 12, 17
4 12/21 Charging Current Setting (ILIM), Setting the Input Undervoltage-Lockout Level (EN/ 21–25, 27, 28,
UVLO), Current Regulation Loop Compensation (COMP), Setting the Output Voltage 30, 31
and Voltage Regulation Loop (FB), Input Short-Circuit Protection External nMOSFET
Selection, Device Power Dissipation, PCB Layout Guidelines, and Typical
Application Circuit, 20A Supercapacitor Charger sections
5 02/22 Updated MAX17701 Block Diagram 12
Updated Benefits and Features section, added TOC19 and TOC20 in Typical
6 6/22 1, 9
Operating Characteristics section
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of
their respective owners.
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MAX17701 4.5V to 60V, Synchronous Step-Down

General Description Benefits and Features

Simplified Application Circuit

Ordering Information appears at end of data sheet. 19-100772; Rev 6; 6/22

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TABLE OF CONTENTS (CONTINUED)

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Absolute Maximum Ratings

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

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Electrical Characteristics (continued)

Overvoltage Comparator VOVI rising 1.245 1.260 1.275

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Typical Operating Characteristics

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Typical Operating Characteristics (continued)

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Typical Operating Characteristics (continued)

GATEN 19 *SGND/EP 12 RT/SYNC

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Pin Description (continued)

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VILIM DIFFERENTIAL 90kΩ

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GV 1.250V (TYP) CFB COUT SYSTEM

Figure 1. Average Current Mode Control Loop

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POWER-UP TIMER COUNT STOPS POWER-DOWN

VFB_CV (1.219V) VFB

HIGH-Z LOW LOW HIGH-Z

HIGH-Z LOW HIGH-Z

Figure 2. Charger Power-Up/-Down Sequence

Input Short-Circuit Protection (GATEN)

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DCIN SHORT TO PGND

(VGATEN - VDCIN) tREV (100ns)

Figure 3. Input Short-Circuit Protection and Recovery Timing Diagram

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Charger Timers (TMR)

Charger Status Outputs (FLG1, FLG2)

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(VGATEN - VDCIN) <

Linear Regulator (VCC and EXTVCC)

Reference Voltage (VREF)

Setting the Switching Frequency and External Clock Synchronization (RT/SYNC)

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Charging Current Monitoring (ISMON)

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Output Capacitor Selection