Chapterd Intel 8085 Microprocessor Introduction Microprocessor Architecture Pin Configuration The 8085 Machine Cycles and Bus Timings Instruction Execution in 8085 Generating Control Signals Instructions Types in 8085 Brief Introduction to 8085 Instruction Set Instruction Format and Assembly Language Programming of 8085 Instructions, Hex Codes, Machine Cycle and T States of 8085 Timing Diagram of Various Instructions Addressing Modes Instruction Set VO Execution Stack and Subroutines Interrupts in 8085 Serial Communication in 8085 Direct Memory Access (DMA) with 8085 Time Delay Generation Assembly Language Programs62 MICROPROCESSORS AND MICROCONTROLLERS. 3.1 INTRODUCTION In this chapter, we will discuss the Intel 8085 microprocessor. As we know 8085 microprocessor is a programmable device which consists of register array, arithmetic, logical and control units. It is a 40-pin IC and the data bus consists of 8-bit, that is why, this microprocessor is called 8-bit microprocessor. The 8085 is an enhanced version of its predecessor, the 8080A, ie., all instructions of 8080A can be executed in 8085 although these are not pin compatible. 3.2. MICROPROCESSOR ARCHITECTURE Intel 8085 is an. 8-bit, NMOS microprocessor. It is a 40-pin IC package fabricated on a single LSI chip. The Intel $085 uses a single +5 V DC supply for its operation. Its clock speed is about 3 MHz and the clock cycle is of 320 ns. The time for the clock cycle of the Intel 8085AH-2, version is 200 ns. It has 74 basic instructions and 256 opcodes. It consists of three main sections an arithmetic and logic unit, timing: and control unit and a set of registers. These important sections are described in the subsequent sections. This process of data manipulation and communication is determined by the logic design of the microprocessor, called the architecture. The microprocessor can be programmed to perform functions on the given data by selecting necessary instructions from its set. These instructions are given to the microprocessor by writing them into its memory. Writing (or entering) instructions and data are done through an input device such as a keyboard. The microprocessor reads or transfers one instruction at a time, matches it with its instruction set, and performs the data manipulation, as indicated by the instruction. The result can be stored in memory or sent to output devices such as LEDs or a CRT terminal. In addition, the microprocessor can respond to external signals. It can be interrupted, reset, or asked to wait to synchronize with slower peripherals. To perform these functions, the microprocessor requires a group of logic circuits and a set of signals called control signals. However, eatly processors did not have the necessary circuitry on one chip, the complete units were made up of more than one chip. Therefore, the tem microprocessing unit (MPU) is defined here as a group of devices, that can perform these functions with the necessary set of control signals. 3.2.1 Register Section The segister section includes all the register that are required during the execution of the programs by microprocessor. 8085 microprocessor contains several registers named as (@) One 8-bit accumulator (ACC), ie., register A (ii) Six 8-bit general-purpose registers (B.C, D, E, H and L) (iii) One 16-bit stack pointer, SP (iv) One 16-bit program counter. PC (v) Instructions register (vi) Temporary register Accumulator (ACC): The accumulator is an 8-bit register associated with the ALU. The register “A’ in the 8085 is an accumulator. It is used to hold one of the operands of an arithmetic or logical operation. It serves as one input to the ALU. The other operand for an arithmetic orINTEL 8085 MICROPROCESSOR 63 gS a ee a8 ® § 3 2 BR & gt Sh Interrupt contrat pba a ee eee Li] ts Tainporary - rege HP) Erencao 7 el ey | | reper || 8 @fc @ | 3e us 5 @leE @ Hi © | - @ | decoding and | [Steck oe a) machine cysts | | Program counter (PC) (1 \enoading circuit) | fperementer/Decrementer = 8 £8 on [Firming anc contro! circuitry: Tam eee |r| | EO SE eta it | tT eee Day ERE EEOSE TE Ha: ‘ri a SF * 2 | Aish (AD, - AD,) Fig. 3.1. Microprocessor Architecture. Erin eae ghost | ol i E ob @e (8) 8 natruction decoder @ ele & ,_slTemporary register] Program counter (PC) (iej] wey 218) B-bitdata lines 16-bit address fines — Ug Fig. 3.2 Register Architecture logical operation may be stored either in the memory or in one of the general-purpose registers. The final result of an arithmetic or logical operation is placed in the accumulator. These above descriptions are tre for general cases, not for some typical or exceptional cases. For example, there are some logical instructions which need only one operand. It is held in the accunmlator.64 MICROPROCESSORS AND MICROCONTROLLERS. The result is placed in the accumulator. Such instructions do not require any other register or memory location because there is no other operand. General-Purpose Registers: The 8085 microprocessor contains six 8-bit general-purpose registers. They are: B. C, D, E, H and L registers. To hold 16-bit data, a combination of two 8-bit registers can be employed. The combination of two 8-bit registers is known as a register- pair. The valid register-pairs in the 8085 are: B-C, D-E and H-L. The programmer cannot form a register-pair by selecting any two registers of his choice. The H-L pair is used to act as memory pointer and for this purpose it holds the 16-bit address of a memory location. The general-purpose registers and the accumulator are accessible to the programmer. He can store data in these registers during writing his program. Program Counter (PC): It is a 16-bit special-purpose register. It is used to hold the memory address of next instruction to be executed. It keeps the track of memory addresses of the instructions in a program while they are being executed. The microprocessor increments the content of the program counter during the execution of an instruction so that it points to the address of the next instruction in the program at the end of the execution of the current instruction. Stack Pointer (SP): It is a 16-bit special-fimction register which holds the address of the topmost filled stack memory. The stack is a sequence of memory locations set aside by a programmer to store/retrieve the contents of accumulator, flags, program counter and general-purpose registers during the execution of a program. Usually the topmost memory location is initialized for stack. Since the stack works on LIFO (last-in-first-out) principle, its operation is faster compared to normal store/retrieve of memory locations. During the execution of a program, sometimes it becomes necessary to save the contents of some registers which are needed for some other operations in the subsequent the program. The contents of such zegisters are saved in the stack Then the registers are used for some other operations. After completing the needed operations, the contents which were saved in the stack are brought back to the registers. The contents of only those registers are saved, which are needed in the later part of the program. The stack pointer (SP) controls addressing of the stack. The stack is defined and the stack pointer is initialized by the programmer at the beginning of a program which needs stack operation, Stack is also used ‘by the microprocessor. For example, it stores the contents of program counter when it jumps to a subroutine using CALL instruction Instruction Register: The instruction register holds the opcode (operation code or instruction code) of the instruction which is being decoded and executed. Temporary Register: There are two 8-bit registers associated with the ALU. They hold data during an arithmetic/logical operation temporarily. They are used by the microprocessor and are not accessible to programmer. These are named W and Z registers. These registers are used to hold &-bit data during the execution of some instructions. However, because they are used internally, they are not available to the programmer. Flags: In addition to the above-mentioned registers, the 8085 microprocessor contains a set of five flip-flops which serve as flags (or status flags). A flag is a flip-flop which indicates some condition which arises after the execution of an arithmetic of logical instruction. The five status flags of Intel 8085 areINTEL 8085 MICROPROCESSOR 65 , a Dy D, D, D, , 2 Leaew [ac Tx p [ x oy S - Sign flag Z— Zero flag C — Auxiliary flag P — Parity flag CY - Carry flag X — Don't care S-Sign flag: After the execution of an arithmetic or logic operation, if bit D, of the result (usually in the accumulator) is 1, the sign flag is set. This flag is used with signed numbers. In arithmetic operations with signed numbers, bit D, is reserved for indicating the sign, and the remaining seven bits are used to represent the magnitude of a number. In a given byte. if D, is 1, the number will be viewed as a negative number; if it is 0, the number will be considered positive. The sign flag has its significance only when signed arithmetic operation is performed. For unsigned arithmetic operation, all the 8 bits are used to represent the magnitude of the number. After the execution of an arithmetic operation, all the 8 bits of the result represent its magnitude. Therefore, the sign flag has no significance in unsigned arithmetic operation. Also, for logical operation sign bit has no significance. Since the sign flag is set or reset according to the MSB of the result, it is set or reset on the value of MSB of the result of logical operation also. Z-Lero flag: The zero fiag is set if the ALU operation results in 0, and the flag is reset if the result is not 0. This flag is modified by the results in the accumulator as well as in the other registers. AC-Auxiliary Carry flag: In an arithmetic operation, when a carry is generated by digit D, and passed on to digit D,. the AC flag is set. The flag is used only internally for BCD (Binary Coded Decimal) operations and is not available for the programmer to use with conditional instructions. P-Parity flag: After an arithmetic or logical operation, if the result has an even number of Is, the flag is set. If it has an odd number of Is, the flag is reset. (For example, the data byte 00000101 has even parity even if the magnitude of the number is odd.) C¥-Carry flag: If an arithmetic operation results in a carry, the carry flag is set; otherwise it is seset. The carry flag also serves as a borrow flag for subtraction. The bit positions reserved for these flags in the flag register are as follows: STATUS FLAG REGISTER PSW (Program status word): | The PSW is a register pair of 16-bit. This includes accumulator register and flag register. The accumulator is used to store the sesult during the execution of the instructions and flag are affected by the current status of accumulator register. It is possible to push the PSW onto the stack, do whatever operations are needed, then POP it off of the stack. BD; | D, | D; | B, | B, s 2] xX |ac| x P| x | cy ales s Accumulator Flag register Program Status Word66 MICROPROCESSORS AND MICROCONTROLLERS. 3.2.2 Arithmetic and Logical Unit The most important unit of a microprocessor is ALU. All the arithmetic and logical operations are performed by ALU on the operands for the implementation of data transformation. As already discussed that one operand that is to be used for the operation must be in accumulator and the result that comes out by certain processing by ALU is stored in the accumulator. The block diagram of ALU is shown in Fig. 3.3, the main components of ALU are accumulator, and other logic circuitry. It carries several operations such as binary addition, subtraction and logical operations, ie, AND, OR, NOT, XOR, increment, decrement, shift, clear, etc. Other certain mathematical operations (division, multiplication) are also perfommed by the ALU but they are performed by making programs, ie. for multiplication we use a counter and using addition repeatedly with the help of a counter. Control signale—*} Shift rotate ‘eout _n| Antimetic Data trom operand| Input register J \ ov] : eee logi unit | stats gio Data fr rand] put register |] ata fram oper I fond I pet I Operation control signal Fig. 3.3 Arithmetic and Logic Unit 3.3 PIN CONFIGURATION The architecture of 8085 indicates the internal circuitry of microprocessor but as it is a 40-pin IC, so each pin performs a certain function, on the basis of the pin diagram, we further classify pin into seven groups. L. Data Pins 2. Address Pins 3. Interrupt and other Peripheral Signal Pins 4. Serial IN/OUT Signal Pins 5. Control and Status Signal Pins 6. Power Supply and GND Pins 7. Oscillator Pins The description of various pins as shown in Figure 3.4 is as follows:INTEL 8085 MICROPROCESSOR 67 Glock Fx, AR a9 veo storal Ly, lie 39 ~~ HOLD’, DMA request AST ae 3 $8 -~ HLDA | signal rsop=| 4 37 > CLK OUT Serial port “sip +l 5 36 ~~ ASTIN | TRAP —+| § READY AST7.5 —»| 7 interrupt | AST6.5— @ signals RST.5 > 9 Calais INTR = 0 ‘signal L INTA=—| 11 ~ ADs >| 12 8085 AD, =<+) 18 AD, <>} 14 AD, =+! 4 Multiplexed lower yp? | ce Higher order address/dala bus pe sy address bus AD ++ 18 AD, <>; 19 “Gnb +) 20 Fig. 3.4 Pin Diagram of 8085. The pins can functions as either input pin or output pin but some pins perform both operations at different clock periods these pins are called bidirectional pins. A,A,, (Output): These are address bus used for the most significant bits of the memory address or & bits of /O address. AD,-AD, (mputOutput): These are the time multiplexed address/data buses, ie., they serve dual purpose. They are used for the least significant & bits of the memory address or /O address during the first clock cycle of a machine cycle, Again they are used for data during second and third clock cycles ALE: It is an address latch enable signal. It goes high during first clock cycle of every machine cycle and enables the lower 8 bits of the address to be latched either into the memory of external Latch. IO/M: It is a status signal which distinguishes whether the address is for memory or I/O. ‘When it goes high the address on the address bus is for an /O device and when it goes low the address on the address bus is for a memory location. RD: It is a signal to control READ operation. When it goes low the selected memory or I/O device is read. WR: It is a signal to control WRITE operation. When it goes low the data on the data bus is written into the selected memery or I/O location. Sy Si: These are the status signals sent by the microprocessor to distinguish the various types of operations given in Table 3.1.68 MICROPROCESSORS AND MICROCONTROLLERS. READY: It is used by the microprocessor to sense whether a peripheral is ready to transfer the data or not. A slow peripheral may be connected to the microprocessor through READY line. If READY is high the peripheral is ready. If it is low the microprocessor waits till it goes high Table 3.1. Status of machine cycle [ Machine Cycle ioM g 6 Operations ‘Opeode Fetch Q 1 1 Read Memory Read o 1 a Read Memory Write Q a 1 Write VO Read 1 1 a Read VO Write 1 o 1 Write Interrupt Acknowledge 1 1 a INTA Halt Zz 0 O AD Hold Zz x x Reset Zz x x INTA HOLD: Itindicates that another device is requesting for the use of the address and the data bus. ‘Affer receiving a Hold request the microprocessor relinquishes the use of the buses as soon as the current machine cycle is completed. Internal processing may continue. The processor regains the bus after the removal of the Hold signal. When a Hold is acknowledged, address bus, Data bus, RD, WR and 10/M are ti-stated. Hold is sampled in T, clock cycle. HLDA: Its a signal for hold acknowledgement. It indicates that the Hold request has been received. After the removal of a Hold request the HLDA goes low. The CPU takes over the buses half clock cycle after the HLDA goes low. INTR: It is an interrupt request signal. Among interrupts it has the lowest priority. When it goes high the program counter does not increment its content. The microprocessor suspends its normal sequence of instructions. After completing the instruction at hand it attends the interrupting device. The INTR line is sampled in the last state of the last machine cycle of an instruction. The microprocessor acknowledges the interrupt signal and issues INTA signal. The INTR is enabled or disabled by the software. An interrupt is used by /O devices to transfer data to the microprocessor without wasting its time. If CPU is in Hold state or interrupt enable flip-flop is reset, an interrupt request is not processed. ENTA: It is an intermpt acknowledgement sent by the microprocessor after INTR is received. RST 5.5, 65, 7.5, and TRAP: These are interrupts, When an interrupt is recognized the next instruction is executed from a fixed focation in the memory as given below: RST 5.5: It is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to OX2CH (hexadecimal) address RST 6.5: It is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 0X34H (hexadecimal) address. It is only level triggered interrupt.INTEL 8085 MICROPROCESSOR 69 RST 7.5: It is a maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 0X3CH (hexadecimal) address. It is only edge triggered interrupt. TRAP: It is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the PC register into stack and branches to 24H (hexadecimal) address. It is both edge and level triggered interrupt. The order of priority of interrupts is as follows: Table 3.2. Various interrupts in 8085 [ interrupt im Prony: [ Vector adress | Maskabienvon-maskable | TRAP ‘Highest priosity 24H Non-maskable RST 75 2 acH Maskabie FST 65 3 sa Maskabie RSTSS 4 2CH Maskabie INTR 5 Non Vectored Maskabie RESET IN: It resets the program counter to zero. It also resets interrupt enable and HLDA (Hold Acknowledgement) flip-flops. It does not affect any other flag or register except the instruction register. The CPU is held in reset condition as long as RESET is applied. RESET OUT: It indicates that the CPU is being reset. It can be used to reset other devices. XI, X2: These are the terminals to be connected to an extemal crystal oscillator which drives the intemal circuitry of the microprocessor to produce a suitable clock for the operation of the microprocessor. CLK: It is a clock output for user, which can be used for the other digital IC’s. The frequency of clock is same at which the processor operates SID: It is a data line Zor serial input. The data on this line is loaded into the 7th bit of the accumulator when RIM instruction is executed. SOD: It is a data line for serial output. The 7th bit of the accumulator is the output on SOD line when SIM instruction is executed. Vee: +5 Volts supply. Vss: Ground Reference. 3.3.1. Demultiplexing the Address and Data Bus The 8085 uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first cycle the address is sent out. The lower $-bits are latched into the peripherals by the Address Latch Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory or UO data. The need for demultiplexing the bus AD,-AD, becomes easier to understand after examining. Figure 3.5 shows the connection for multiplexed address and data buses.70 MICROPROCESSORS AND MICROCONTROLLERS. High-order address bus 8085 Microprocessor Loworder address bus PPP PEPE Data bus PIP PEPE P Fig. 3.5(a) Demuttipexing of Address and Data Bus. Figure 3.5(b) shows that the address on the high-order bus (20 H) remains on the bus for three clock periods. However, the low-order address (05 H) is lost after the first clock period. This address needs to be latched and used for identifying the memory address. If the bus AD,-AD, is used to identify the memory location (2005 H), the lower order multiplexed address will change to 4FH data after the first clock period. Figure 3.5(a) shows a schematic that uses a latch and the ALE signal to demultiplexing the bus. The bus AD,-AD, is connected as the input to the latch 74L$373 __ The ALE signal is connected to the Enable (G) pin of the latch, and the Output Control (OC) signal of the latch is grounded. The ALE goes high during T,. When the ALE is high, the latch is twansparent; this means that the output changes according to input data. During T, the out-put of the latch is 05 H. When the ALE goes low, the data byte 05 H is latched until the next ALE and the output of the latch represent the low-order address bus A.-A, after the latching operation. Intel has circumvented the problem of demultiplexing the low-order bus by designing special devices such as the 8155 (256 bytes of RAW memory + I/O's), which is compatible with the 8085 multiplexed bus. These devices internally demmltiplex the bus using the ALE signal. After carefully examining the Figure 3.5(b), we can make the following observationsINTEL 8085 MICROPROCESSOR 71. _Opeode tech 1 Ts 1 —_— 7 +) y Tigh-ordae 1 i att J. Unsoetd | 0,| foworder | |} oo |-{ 4FH opcode ab, Ee =e : | Memory address | 7 \ TOM = 6.8, = 1,8, = 1 | Opcode fetch Fig. 2.5(0) | Dernuttiplexing Timing Diagram. 1. The machine code 4FH (0100 1000) is a one-byte instruction that copies the contents of the accumulator into register C for instruction MOV C: A. 2, The 8085 microprocessor requires one external operation-fetching a machine code from memory location 2005 H. 3. The entire operation—fetching, decoding, and executing—requires four clock periods. Decoding and executing an instruction after it has been fetched can be illustrated with the following example. Example: Assume that the accumulator contains data byte 82 H, and the instruction MOV B, ‘A (42H) is fetched, List the steps in decoding and executing the instruction. Solution: In this example, we have the contents of the accumulator opcode 47. To decode and execute the instruction, the following steps are performed. L. The contents of the data bus (42H) are placed in the instruction register and decoded. 2. The contents of the accumulator (82H) are transferred to the temporary segister in the ALU. 3, The contents of the temporary register are transferred to register B.72 MICROPROCESSORS AND MICROCONTROLLERS. 3.4 THE 8085 MACHINE CYCLES AND BUS TIMINGS The 8085 microprocessor is designed to execute 74 different instruction types. Each instriction hhas two parts: operation code, known as opcode, and operand. The opcode is a command such as Add, and the operand is an object to be operated on, such as a byte or the contents of a register. Some instructions are 1-byte instructions and some are multi-byte instructions The first machine cycle is opcode fetch where the opcode of the instruction is fetched and decoded. After decoding, to execute an instruction, the 8085 needs to perforin various operations, such as Memory Read/Write and /O Read/Write etc. However, there is no direct relationship, between the number of bytes of an instruction and the mumber of operations the 8085 has to perform. All instructions are divided into a few basic machine cycles and these machine cycles are further divided into precise system clock periods. Basically, the microprocessor extemal communication functions can be divided into three categories 1. Opcode fetch (memory read plus opcode decode) 2. Memory Read and Write 3. UO Read and Write ‘Now we can define three terms; instruction cyele, machine cycle and T-state and use these terms later for examining timings of various 8085 operations. Instruction cycle is defined as the time required in completing the execution of an instruction. The 8085 instruction cycle consists of one to five machine cycles or one to five operations. Machine cycle is defined as the time required to complete one operation of accessing memory, VO. or acknowledging an extemal request. This cycle may consist of three to six T-states. T-state is defined as one subdivision of the operation performed in one clock period. These subdivisions are intemal states synchronized with the system clock, and each state is precisely equal to one clock period. The terms T-state and. clock period are often used synonymously. Instruction cycle A Machine cycles up to 5 (M1 + M2 ...... MB) £x TSiate (3-6) 3.4.1 Opcode Fetch Machine Cycle The first operation in any instruction is Opeode Fetch. The microprocessor needs to get (fetch) this machine code from the memory register where it is stored before the microprocessor can begin to execute the instruction. We discussed this operation in example. Figure 3.5(a) shows how the 8085 fetches the machine code, using the address and the data buses and the control signal, and also shows the timing of the Opcode Fetch machine cycle in relation to the system's clock. However. to differentiate an opcode from a data byte or an address, this machine cycle is identified as the Opcode Fetch cycle by the status signals (O/M = 0, S, = 1, S, = 1): the activeINTEL 8085 MICROPROCESSOR 73 low 1O/M signal indicates that it is a memory operation, and S, and S, being high indicate that it is an Opcode Fetch cycle. This Opcode Fetch cycle is called the M cycle and has 3-6 T-states. The 8085 uses the first three states T,-T, to fetch the code and T, ; to decode the opcode. In the 8085 instruction set, some instructions have opcode with six T-states, we may find that these two operations (Opcode Fetch and Memory/Read) are almost identical except that the Memory Read Cycle has three T-states. 3.4.2. Memory Read Machine Cycle To illustrate the Memory Read machine cycle, we need to examine the execution of a 2-byte or a 3-byte instruction because in a I-byte instruction the machine code is an opcode: therefore, the operation is always an Opcode Fetch. The execution of a 2-byte instruction is illustrated in the next example Example: Two machine codes—0011 1110 GEH) and 001100 10 (32 H) are’stored in memory locations 2000 H and 2001 H, respectively, as shown below. The first machine code (3EH) represents the opcode to load a data byte in the accumulator, and the second code (32 H) rep- resents the data byte to be loaded in the accumulator. We have to calculate the time required to execute the Opcode Fetch and the Memory Read cycles and the entire instruction cycle if the clock frequency is 3 MHz Memory Location Machine Code Instruction Comment 2000 H EH MVEA 82H Load Byte 82 H in the accumulator 2001 H 2H Solution: This instruction consists of two bytes; the first is the opcode and the second is the data byte. The 8085 needs to read these bytes first from memory and thus requires at least two machine cycles. The first machine cycle is Opcode Fetch and the second machine cycle is Memory Read, as shown in Figure 3.6; this instruction requires seven T-states for these two machine cycles. The timings of the machine cycles are described in the following paragraphs. 1. The first machine cycle M1 (Opcode Fetch) is identical in ‘bus timings with the machine cycle illustrated in example, except for the bus contents. At T,, the microprocessor identifies that it is an Opcode Fetch cycle by placing O11 om the status signals (O/M = 0, S, = 1 and S, = 1). It places the memory address 2000 H) from the program counter on the address bus, 20 H on A,,-A,, and 00 H on AD,-AD, and increments the program counter to 2001 H to point to the next machine code. The ALE signal goes high during T,, which is used to latch the low-order address 00 H from the bus AD,-AD,. At, the 8085 asserts the RD control signal, which enables the memory, and the memory places the byte 3FH from location 2000 H on the data bus. Then the 8085 places the opcode in the instruction register and decodes the RD signal. The fetch cycle is completed in state T,, During T,, the 8085 decodes the opcode and finds out that a second byte needs to be read. After the T, state, the contents of the bus A,,-A, are unknown, and the data bus AD,-AD, goes into high impedance.74 MICROPROCESSORS AND MICROCONTROLLERS. ii pecs oer) Tenant) High order memory 1 High order memory ‘eieosas | Unspectied (20H ‘ee Lower order oi 2 Haat * * Memory address toma # 1, 8= 1 Opcode | \ §\-8. fetch’ { ‘a i | | H| 4 — ii ‘a L ‘ | Fig. 3.6. Timing of the Instruction MVI A, 32 H. 2. After completion of the Opcode fetch cycle, the 8085 places the address 2001 H on the address bus and increments the program counter to the next address 2002 H. The second machine cycle M, is identified as the Memory Read cycle (IO/M = 0, S, = 1, and S, = 0) and the ALE is asserted. At T,, the RD signal becomes active and enables the memory chip. 3. At the rising edge of T,, the 8085 activates the data bus as an input bus; memory places the data byte 32 H on the data bus, and the 8085 reads and stores the byte in the accumulator during T,. The execution times of the Memory Read machine cycle and the instruction cycle are calculated as follows: * Clock frequency f = 3 MHz + Tstate = clock period (/f) = 0.33 ps + Execution time for Opcode Fetch: (4 T) x 0.33 = 13 3ps + Execution time for Memory Read: (3 T) x 0.33 = 0.3267 ps + Execution time for Instruction: (7 T) ¥ 0.33 = 2.21 psINTEL 8085 MICROPROCESSOR 75 3.5 INSTRUCTION EXECUTION IN 8085: To understand the functions of various signals of the 8085, we should examine the process of communication between the microprocessor and memory and the timings of these signals in relation to the system clock The approach to designing an interfacing circuit for an I/O: device is determined primarily by the instructions to be used for data transfer An VO device can be interfaced with the 8085 microprocessor either as a peripheral VO or as 2 memory-mapped UO. In the peripheral V/O, the instructions IN/OUT are used for data transfer, and the device is identified by an 8-bit address. In the memory-mapped I/O, memory-related instructions are used for data transfer, and the device is identified by a 16-bit address. However, the basic concepts in interfacing /O devices are similar in both methods. Peripheral I/O and the memory-mapped V/O are described in the following section. Memory Memory Ader | Content| —! ox8000H | 42H L Data bus 7 TT T ey } oy |] [Temporary Instruction [Reon] gee] (Eger 0x 8002H ty Ee 0x 8001H | 00H | Tirning and |__-control unit Fig. 3.7 Instruction Decoding and Execution. Decoding and executing an instruction after it has been fetched can be illustrated with the following example Example: Assume that the accumulator contains data byte 82 H, and the instruction MOV B, A 42H) is fetched, List the steps in decoding and executing the instruction. Solution: In this example, we have the contents of the accumulator opcode 47. To decode and execute the instruction, the following steps are performed. L. The contents of the data bus (42H) are placed in the instruction register and decoded. 2. The contents of the accumulator (42H) ate transferred to the temporary segister in the ALU. 3. The contents of the temporary register are transferred to register B. 3.6 GENERATING CONTROL SIGNALS Figure 3.8 shows the RD (Read) as a control signal. Because this signal is used both for reading memory and for reading an input device, it is necessary to generate two different Read signals76 MICROPROCESSORS AND MICROCONTROLLERS. one for memory and another for input. Similarly, two separate Write signals must be generated. Figure shows that four different control signals are generated by combining the signals RD, WR, and JO/M. The signal IO/M goes low for the memory operation. This signal is ANDed with RD and WR signals by using the 74LS32 quadruple two input OR gates. The OR gates are fanctionally connected. as negative NAND gates. When both input signals go low, the outputs of the gates go low and generate MEMR (Memory Read) and MEMW (Memory Write) control signals. When the 1O/M signal goes high, it indicates the peripheral VO operation: This signal is complemented using the Hex inverter 74LSO4 and ANDed with the RD and WR signals to generate TOR (/O Read) and IOW (V/O Write) control signals 8085 1m + 1 mi Rp wie | pe - LEST }—in oo 2} iw Fig. 3.8 Schematic to Generate Read/Write Control Signals for Memory and UO. 3.6.1 Timing and Control Unit This unit synchronizes all the microprocessor operations with the clock and generates the control signals necessary for communication between the microprocessor and peripherals. The control signals are similar to a syne pulse in an oscilloscope. The RD and WR signals are syne pulses indicating the availability of the data on the data bus. 3.6.2 Important Concepts L. The 8085 microprocessor has a multiplexed bus AD,-AD, used.as the lower-order address bus and the data bus, 2. The bus AD,-AD, can be demultiplexed by using a Latch and the ALE signal 3. The 8085 has a status signal 10/M and two control signals RD and WR. By ANDing The 8085 MPU transfers data from memory locations to the microprocessor by using the control signal Memory Read (MEMR-active low). This is also called reading from memory. The term data refers to any byte that is placed on the data bus; the byte can be an instruction code. data, or an addressINTEL 8085 MICROPROCESSOR 77 4, Transfer data from the microprocessor to memory by using the control signal memory write (MEMW-active low). This is also called writing into memory. 5. Accept data from input devices by using the control signal /O Read (IOR-active low). 6. Sends data to output devices by using the control signal /O Write. This is also known as writing to an output port To execute an instruction, the MPU + Places the memory address of the instruction on the address bus. * Indicates the operation status om the status lines. + Executes the instruction, 3.7 INSTRUCTION TYPES IN 8085 3.7.1 One-Byte Instructions ‘A L-byte instruction includes the Opcode and the operand in the same byte. If the instruction does ‘not contain any immediate byte (data), it is one byte instruction. For example: [ase Mnemonic Operand, Hex code Copy the contents of the accumulator in MoV oA aFH register C ‘Add the contents of register B to the ADD 8 a0H contents of the accumulator ian ie an FH These instructions are 1-byte instructions performing three different tasks. In the first instruction, both operand registers are specified. In the second instruction, the operand B is specified and the accunmulator is assumed. Similarly, in the third instruction, the accunmlator is assumed to be the implicit operand. These instructions ase stored in S-bit binary format in memory: each requires one memory location. 3.7.2 Two-Byte Instructions TE the instruction contains 8 bits (data), it is 2-byte instruction. In a 2-byte instruction, the first byte specifies the operation code and the second byte specifies the operand. For example, assume the data byte is 32 H. The assembly language instruction is written as Mnemonics MVI.A, Hex Code 32H 3EH, 32 H. This instruction would require two memory locations to store in memory. 3.7.3 Three-Byte Instructions If the instruction contains 16 bits (data), it is 3-byte instruction. In a 3-byte instruction, the first byte specifies the opcode, and the following two bytes specify the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-order address. For example:ih) MICROPROCESSORS AND MICROCONTROLLERS. Task Mnemonic Operand Hex code ‘Transfer the program sequence to the MP 2085 H C3 First Byte memory location 2086 H 85+ Second byte 20- Third Byte 3.8 BRIEF INTRODUCTION TO 8085 INSTRUCTION SET The 8085 important instructions are explained in this section to make reader familiar with basic operation performed by 8085 1. Data Transfer Instructions MOV regX, reg ie MOVBA Copy the content of regY into segX; content of regY remains unchanged. MVI reg, 8-bit data (immediate data) ie. MVIA 32H Copy the immediate data given into reg. LDA 16-bit address ie LDA CO 05 Load the Accumulator with the content of the memory location specified by 16-bit Address STA 16-bit address ie STA CO 05 Store the content of accummlator to the memory location specified by the 16-bit Address. LDAX Rp (Rp = Register pair) ie LDAXB (Load the accumulator with a data contained in a memory location where the 16-bit memory location is stored in the BC segister pair) STAX Rp (Rp = Register pair) ie STAXB (Store the content of the accumulator to a memory location where the 16-bit memory location is stored in the BC register pair) IN portaddr ie. IN 00 (Reads data from the Input Switch, 00 represents the port address of the input switch) OUT portaddr ie. OUT 00 (Writes data to the Display device where 00 represents the Port address of the display)INTEL 8085 MICROPROCESSOR 79 2, Arithmetic Instructions ADD reg Add the content of given register to accumulator. Result is stored in accumulator. ie ADD B [A] = [AP Bl] ADI 8-bit data ‘Add the given 8-bit data to accumulator. Result is stored in accumulator. ie ADI 47H [AF [AF 478 SUB reg Subtract the content of given register from accumulator. Result is stored in accumulator. ie. SUB C [Al = [4] - [¢] SUL reg Subtract the given 8-bit data from accumulator. Result is stored in accumulator. ie. SUL SFH : [A] = [A] — 5F INR reg Increment the Content of a Register specified by reg. ie INRB Increments the Content of Register B by 1 DCR reg Decrement the Content of a Register specified by reg. ie DCRD Decrements the Content of Register D by 1 INK Rp Increment the Content of a Register pair specified by Rp ie: INXB Increments the Content of Register pair BC by 1 DCX Rp Decrement the Content of a Register pair specified by Rp ie: DCXB Decrement the Content of Register pair BC by 1 3. Logical Instructions ORA reg Performs the logical OR operation of given reg with accumplator. Result is stored in accumulators.80 MICROPROCESSORS AND MICROCONTROLLERS. ie ORAB Perform the OR operation of register B with accumulator. ORI 8-bit data Performs the logical OR operation of given 8-bit data with accumulator. Result is stored im accumulator. ie ORA 12H Perform the OR operation of 12H with Accumulator. ANA reg Performs the logical AND operation of given reg with accumulator, Result is stored in accumulator. ie ANAB Perform the AND operation of register B with accumulator. ANT 8-bit data Performs the logical AND operation of given 8-bit data with accumulator. Result is stored in accumulator ie ANA B Perform the AND operation of register B with accumulator. XRA reg Performs the logical XOR operation of given reg with accumulator. Result is stored in accumulator. ie. XORB Perform the XOR operation of register B with accumnlator. XRI &-bit data Performs the logical XOR operation of given 8-bit data with accummilator. Result is stored in accumulator ie XOR 12H Perform the XOR operation of 12H with accumulator. CMA Complements the Content of the accumulator (Performs the NOT Operation) CMP reg Compares the Content of the accumulator with the register specified by “reg” If (B) > (A) , then Cary flag is set If (B) = (A), then Zero flag is set IE (A) > B), then No flag is set CPL &-bit data Compares the content of the accumulator with the immediate data specified by the 8-bit dataINTEL 8085 MICROPROCESSOR 81. 4, Branching Instructions IMP 16-bit address [Unconditional Jump] The program sequence jumps unconditionally to a memory location defined by 16-bit address. JC 16-bit address [Conditional Jump] The program sequence jumps to a memory location defined by 16-bit address if the Carry Flag is set: INC 16-bit address [Conditional Jump] The program sequence jumps to a memory location defined by 16-bit address if the Carry Flag is not set. IZ 16-bit address [Conditional Jump] The program sequence jumps to a memory location defined by 16-bit address if the Zero Flag is set: INZ 16-bit address [Conditional Jump] The program sequence jumps to a memory location defined by 16-bit address if the Zero Flag is not set. 5. Machine Control Instruetions HLT Stop program execution. NOP Do not perform any operation. 3.9 INSTRUCTION FORMAT AND ASSEMBLY LANGUAGE PROGRAMMING IN 8085 3.9.1 Assembler Instruction Format The general format of an assembler instruction is Memory Sponde! [abet Mnemonics | Operands | {Comments Address | Hex code _ | The inclusion of spaces between label, mnemonics, operands and comments are arbitrary, except that at least one space must be inserted. No space would lead to an ambiguity. There can ‘be no space within a mnemonic or identifier. Each statement in the program is consists of fields. (a) Label: It is an identifier that is assigned the address of the first byte of the instruction in which it appears. A label appears in a program to identify the name of a memory location storing data and for other purposes. The presence of a label in an instruction is optional, but if present, the label provides a symbolic name that can be used in branch instruction to branch fo the instruction. A colon must be placed at the end of the Label, if there is no label, then the colon must not be entered. All labels begin with a letter or one of the following special character: @, $, _ or ?. A label may be of any length from 1 to 35 characters.82 MICROPROCESSORS AND MICROCONTROLLERS. (b) Mnemonics: Mnemonics is a name assigned to a machine function. The mnemonic specifies the operation to be executed. The assembler converts these mnemonics into actual processor instructions and associated data All instructions must contain a mnemonic. (©) Operands: The presence of the operands depends on the instruction. Some instructions have no operands, some have one operand, and some have two. If there are two operands, they are separated by a comma. (d) Comments: The comment field is for commenting the program and may contain any combination of the characters. It is optional in programming. A comment may appear on a line by itself provided that the first character on the line is a semicolon. Example 1: Place 05 in register A; then move it to segister B. Assume that the starting address of program in 0x8000H Program: Address Opcode / Hex code Mnemonics Operands Comments 8000 3E, 05 MVI ALS :Get 05 in register A. 3002 47 MOV BA ;Transfer 05 from A to B. 8003 16 HLT :Stop the program execution. Explanation: Here it is assumed that the program is loaded from memory Iocation 8000H. The RAM memory on the kit on which this program is loaded. should start from 8000H. Each opcode is loaded into memory one after another. After loading all the opcode the program can be executed. 3.9.2 Writing Assembly Language Program for 8085 To write a program for 8085 following steps are needed 1. Analyze the problem 2. Develop program Logic 3. Write an. Algorithm 4. Make a Flow Chart 5. Write program Instructions using Assembly language of 8085 Example: Program 8085 in Assembly language to add two 8-bit numbers and store 8-bit result in register C. 1, Analyze the problem — Addition of two 8-bit numbers to be done 2. Program Logic — Add two numbers — Store result in register C ~ Example 10011001 (99H) A + 00111001 (9H) D 11010010 (D2H) CINTEL 8085 MICROPROCESSOR 83 3. Algorithm Operations Translation te 8025 operations 4. Get two numbers Load 1* no. in register D Lead 2 no. in register © 2. Add them Copy register D to A Add register E to A 3. Store result Copy A to register 4 Slop Stop processing 4. Make a Flow Chart Stat) ae Se. y Load Register 0, & y i r y | Copy Dio A i u aasnande | [emane | ti Stop.) 5, Assembly Language Program ‘S.No. | Qperatione to be pertommed ‘neiructions 1__| Get two numbers (@) Load 1 no. in register D MVID, 2H (@) Load 2 no. in register E MVLE, 3H 2_| Add them (a) Gony regisier D to A. wOV AD (0) Add register E to A ADDE Store result (a) Gopy A to register G Stop (@) Stop provessing HLT84 MICROPROCESSORS AND MICROCONTROLLERS. 3.10 INSTRUCTIONS, HEX CODES, MACHINE CYCLE AND T STATES OF 8085 The summary of 8085 instruction set, opcode, machine cycle and T state is given in the Table 3.3 shown below. This can be used for the obtaining hex code to perform experiment on 8085 trainer kit. The machine cycle is useful in calculated time delay associated with each instruction whereas T states are helpful in calculating exact time delay for each instruction. Table 3.3. Mnemonics, Hex code, Machine cycle and T-state of 8085 Mnemonics | Hex Code | Wnemonics | Hex Code | Machine | 7 State gyete Acegt [CE 2 7 [ero test [e+ 28 ‘921 ADC A oF 1 4 cziest__ [oc 28 221 ADC B 38 1 4 DAA oT 1 4 ADC C 29 1 4 DAD B 9 1 a ‘ADC D aA 1 4 DAD D 79 1 3 ADC E 38 1 4 DAD H 29 1 3 ADC H 8c i 4 DAD SP [08 1 a ADS L [ao 1 4 DCA A 3D i 4 ADC M aE 2 Z DCR B 5 1 4 ADD A a7 7 4 DCR C 0D 1 4 ‘ADO B 30 1 4 DGR D 15 1 4 ADD C a 1 4 DCR E 1D 1 4 ADD D a 7 4 DCR H 25 1 4 ‘ADO E 8 7 4 DoRL 2D 1 4 ADD H 4 1 4 DCAM [95 3 10 ADDL 35 7 4 DOCK B 08 fl é ‘ADD M 86 2 7 DCX D 18 1 é ADIGE | C6 2 7 DCX H 2B 1 6 ANA A ar 1 4 DcK SP [9B 1 6 ANA 8 ao i 4 DI FS 1 4 ANAC Al 1 4 al FB 1 4 ANA D 22 1 4 HET 78 Zor more | 5 or more ANA E 48 7 4 INeBt [DB 3 7 ANA H aM 1 4 INRA 1 4 ANAL 25 1 4 INR B 4 1 4 ANA M 46 2 7 INR og 1 4 AN 6-5 [ES 2 7 TNR D 4 1 4 CALL 168% [CD 5 18 INRE 7¢ 1 4 ceiest [pe Zor |oorta| [INAH 28 1 4 CM i6B [FC 2 7 TRL 26 1 4INTEL 8085 MICROPROCESSOR 85 Conta. MA oF fl 4 INA M 34 3 uc oF 1 4 INK a 1 6 ‘CMP A BF 1 4 INK D 13 1 6 CMP B Ba 1 4 INX H 23 1 6 GMPC Ba i 4 IN SP 38 1 6 ‘GMP D BA 1 4 wwe [DA 25 7,10 CMP E BB i 4 MT6B [FA 2.6 7.44 GaP BC 1 4 MP 168% [Cs 3 70 | OMP L BD 1 4 wNZ 168% | D2 25 7.10 Me BE 1 4 wz 1eBt [Gz 26 7 cnc 1661 [Da 25 8 weieet [Fe 25 7,10 onz 16B% | G4 28 919 wPE 166i | EA 28 7a crit | Fa 27 9.20 Poteet [ez a7 712 CPE 1eB [EC 28 921 Zest [ea 28 7.18 cPest | FE 2 7 LDA TéBt | 3A 4 18 [iDax [oA 2 7 WOVE M [SE 2 7 LDAX D 1A 2 Z wovi a |67 i 4 LHLD 166i [2A 5 6 MOVH.B [60 1 4 Die ieBt [1 3 10 wOvH.C | 61 1 4 vapiset [11 a 0 wovHD [62 1 4 LAH eit [21 3 10 MOVHE [63 1 4 ba $168 [31 3 30 MOVHH [64 1 4 MOVALA [JF 1 4 MOvH.L [65 1 4 MOVAB [78 1 4 MovHM | 66 2 7 MovA,c [79 1 4 MOVLLA [ar 1 4 MOVAD [7A 1 4 woviB [68 1 4 MOVA.E [78 a 4 wovi.c [6s 1 4 MOVA,H [76 i 4 wovE,.o [6A 1 a MOVAL [7D 1 4 MOVLE [68 i 4 MOVAM [TE 2 7 MoviLH [ec 1 4 MOVB.A [47 1 4 MOVEL |e 1 4 MOVE.B [40 1 4 MOVLM | 6E 2 7 MOvB,C [41 1 4 Mov A [a7 2 7 move,o [42 1 4 wovM,.e [70 2 7 MOVB.E [48 i 4 wOvM.G [71 2 7 MOvB,H [44 1 4 wovM,D_ [72 2 7 move,t [45 7 4 wOVME |78 2 Z MOVB.M [46 2 7 MOvM.H [74 z 7 |86 MICROPROCESSORS AND MICROCONTROLLERS. Conte. MOVGA [4F 1 4 NOVM.L [75 2 7 move.B (48 1 4 MVIA 8H | SE 2 7 Move.¢ [49 1 4 MVIB 6-Bt [6 2 7 MOVC.D [4A 7 4 MVC Bit [OE 2 7 MOVCE [48 1 4 MVD eat | 16 2 7 MOVG.H [4G 1 4 NOV E, 88H [1E 2 7 wove,t [4D i 4 MH Beit [36 2 7 MOVE.M [4 2 7 NOVHA [67 1 4 MOVD.A [57 1 4 vil, ot | 2E 2 7 MovD,B [50 i 4 MviM, eR | 36 3 70 wovo.c [St i 4 NOP a 1 4 MOVD,D [52 7 4 ORAA 57 7 4 MOVD,E [53 7 4 ORAS Ey 1 4 MOVD.H [54 1 4 ORAG 81 1 4 MOVD.L [55 1 4 ‘OFA D Be 7 4 [MOVD,M [56 2 Z ORAE a 7 4 MOVE.A [SF 1 4 OPRAH Bt 1 4 MOVE.B [58 i 4 ORAL aS i 4 MOVE,c [59 i 4 ORAM 36 2 7 MOVED [5A 1 4 On eBt _| FB 2 7 MOVE,E [58 i 4 cures [03 3 70 MOVE,H_[5C i 4 PCHL EF i 6 MOVE.L [5D i 4 POP B a 3 70 POP D Di 3 70 SUB a1 i 4 POP H a 3 70 SUBD 2 1 4 POP PSW [Fi 3 FD) SUBE 3 1 4 PUSH [C5 3 2 SUB H a i 4 PUSHD [D5 3 2 sBieet | DE 2 7 PUSHH [ES 3 2 SHLD 166i | 22 3 16 PUSH PEW [FS 3 2 SIM 20 i 4 RAL 7 1 4 SPHL Fo 1 é RAR 1F i 4 STA 16Bt [2 4 8 RC DB i 4 staxe [2 2 7 AM Fa 1s [ei STAXD [72 2 7 RNC Do 13 (612 STC 37 i 4 ANG a 13 (612 SUB A 7 1 4 RP FO 18 [612 ‘SUB B 20 1 4 RPE Ey 13 [612 svaxe [2 2 7INTEL 8085 MICROPROCESSOR 87 Contd. FPO Eo 12 612 sTaxo [12 2 7 FRG oF 1 4 STC a 1 4 RSTO ea 3 2 SUB A 97 1 4 RST 1 oF a 2 SUB 8 90 1 4 RST 2 BF 3 @ SUB C a i 4 RST S DF 3 2 SUB D 2 1 4 RST 4 E7 a 2 SUB E 9 1 4 RST S EF 3 2 SUB H 94 1 4 AST 3 2 SUB L s 1 4 RST 7 FE 3 % SUB M 36 2 7 RZ ca 13 612 suli6-Bt [D6 2 7 | S88 A oF 1 4 CHG eB 1 4 856 B 8 1 BAA AF 1 4 S85 C 99 1 4 XRA B AB 1 4 888 D En 1 4 XAA CG Ag 1 4 BBB E 35 1 4 [XRA D AA 1 4 S85 H 8c 1 4 XRAE AB 1 4 S88 L 3D 1 4 XBA H ag 1 4 S55 M = 2 z RAL aD 1 4 slept | DE 2 7 XRAM aE 2 7 SHLD 16H [22 3 6 xAleet [EE 2 7 ‘SIM Ey 1 4 XTHL eS 5 16 3.11 TIMING DIAGRAM OF VARIOUS INSTRUCTIONS Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals 10/M, Si, and SO. All actions in the microprocessor are controlled by either leading or trailing edge of the clock. The clock signal determines the time taken by the microprocessor to execute any instruction. The 3-status signals: IO/M, $1, and SO are generated at the beginning of each machine cycle. The unique combination of these 3-status signals identify read or write operation and remain valid for the duration of the cycle The execution of instruction always requires read and write operations to transfer data to or from the uP and memory or V/O devices. Each read/write operation constitutes one machine cycle (MC) as indicated in Table 3.4 shown below. Some instructions are explained with examples. Table 3.4 Machine cycle status and control signals Machine eyele | Staiue | OM Ss. NTA ‘Opcode Fetch (OF) 0 1 1 1 Memory Read a 1 oO oO 1 188 MICROPROCESSORS AND MICROCONTROLLERS. Memory Write UO: Read (VOR) UO Write wow) Acknowledge of INTR (NTA) BUS Idle (BI) : DAD ‘AGK of AST, TRAP 1 HALT Zz HOLD Zz | 0 1 1 i waa eabon | sallcrlean] ae fase alul2| s)he] she ninfa{afofole}a nlo}=loa}—a|alo}a x}o}-|4|-/ol4}o 1. ADC M Function: Add the contents of memory location M whose address is in HL register pair in the contents of accumulator along with canry bit and zesult is stored in accumulator. Example: The opcode for ADC M is 8E which is located at the address 8000H. Let HL contains the address memory 8001H. The data at $000H is 23H and Accumulator has content 01H. Carry is zero. Program: 8000H 8E ‘Memory Address ae (a) The first machine will fetch the opcode from memory address 8000H. In the second machine cycle the HL pair will leads to memory address 8001H whose contents will be added to accumulator along with carry. The result will be 32H+01H=24H will remain in accumulator. 2. HLT Function: This instruction is used to stop the execution of the processor. Example: Let assume that the opcode for HLT instruction is written at memory location 8000H. Timing Diagram 3. CALL iébit address Function: This instruction is used for unconditional CALL to the subroutine identified by 16- bit operand. Before branching to subroutine, addresses of PC are saved on stack. 4, RET Function: This instruction is used at the end of a subroutine. The execution of RET instruction brings back the saved address from the stack to program counter. Program jumps to the next instruction of the main program which is next to CALL instruction. Example: We want to read the 8-bit data from a memory location and add 30H into given data and then want to store the result on a memory location. The CALL instruction is written at memory address 2013H.INTEL 8085 MICROPROCESSOR 89 Memory read ALE \ | RDF ME x IOIMB = 08,245, =4 Ve jon 08, 08,04 pM =08,=18,= J 1OMs=08,-05,« wae Fig. 89 Timing Diagram of AG M Insuction Opcode fetch Ty Ty Ta Ty wl PLS Aan As i SoH X 7% ADo=AD, XH 78 \ moan ROF \ | iN j OMe =0,$)21.8,=1 wre Timing Diagram of HLT Instruction,90 MICROPROCESSORS AND MICROCONTROLLERS. Main Program: Address Hex code © Label Mnemonics Operands Comments 2009 3A, 08, 20 LDA 8200 Get Hexa Data 2012 47 MOV BA ; Move data into accumnlator 2013 €D.1A,20 CALL ADDI Call subroutine to add 30H 2016 32, OA, 20 STA 8200 ‘Store the result 2019 76 HLT Stop the execution Subroutine to add 30H: Address Hexcode Label Mnemonics Operands Comments 201A FE, 0A ADDI: ADI 30H :Add 30H to accumulator 201C co RET xretum to main program Timing Diagram of CALL instruction: (a) In first machine cycle (M1), the contents of program counter (2013H) are placed on the address bus and instruction code CD is fetched using the data bus. (b) In M2 and M3, memory read operation is done. In this 16 bit address (201A H) of CALL instruction is fetched. (©) In machine cycle M4 and M5, storing of Program counter is done Timing Diagram of RET instruction: (@) In first machine cycle (M1), the contents of program counter (2023H) are placed on the address bus and instruction code C9 is fetched using the data bus. (b) In. machine cycle M2 and M3, storing of Program counter is done. The program execution will start from the main program from the next instruction after the CALL instruction ie. from memory location 2016H. 3.12 ADDRESSING MODES The instructions consist of two parts opcode and operands. The opcode determines the operation to be performed and the operand determines the data to be operated on, The manner in which operand is specified in the instruction is called addressing mode. Intel 8085 uses the following addressing modes: 1. Direct addressing 2. Register addressing 3. Register indirect addressing 4. Immediate addressing 5. Implicit addressing 3.12.1 Direct Addressing In this mode of addressing, the address of the operand (data) is given in the instruction itself Examples are:re Bia piss —o= Hor) | TEs t= 's'L=°s ‘0= sor mT | \ Jao #0 \ [aw (wm) | Hoa) Co) A Mh) ppp (@ en “av—fav oe eX 02} | paysedsuny ‘7 LL ey apt Pay Pay boy Tey Pay SUA AOWOR] — OU KlowOWY peel KowoYy a es pee! Asowoy) LALLA Ye A, pHa) epoodg, Pyne92 MICROPROCESSORS AND MICROCONTROLLERS. Opcode fetch Memory read ‘Memory read Th!) Te Gk Tt cax\ | f Lt fy chen hag 20 ¥ 20 tomas = 0, Fig. 3.11(b) Timing diagram of RET instruction. Mnemonics | Opcode Function STA 2600 H_ | 32, 00, 26 |; Store the content of the accumulator in the memory location 2600 H. In this instruction 2600 H is the memory address where data is to be stored. It is given in the instruction itself. The 2nd and 3rd bytes of the instruction specify’ the address of the memory location. Here, it is understood that the source of the data is accumulator. Mnemonics ‘Opcode Function INO DB, 04 Read data from the port C. In this instruction 04 is the address of the port C of an I/O port from where the data is to be read. Here, it is implied that the destination is the accumulator. The 2nd byte of the instruction specifies the address of the port. 3.12.2 Register Addressing In register addressing mode the operand is in one of the general-purpose registers. The opcode specifies the address of the register(s), in addition to the operation to be performed.INTEL 8085 MICROPROCESSOR 93 Examples are: S.No. [Mnemonics | Opcode [Function 1 MOV A,B 88 Move the content of register B to register A. 2 |ADDB 80 ‘Add the content of register B to the content of register A In Example 1 the opcode for MOV A. B is 88 H. Besides the operation to be performed, the opcode also specifies source and destination registers. The opcode 88 H can be written in binary form as 10001000. The first two bits, ie. 10 are for MOV operation, the next three bits 001 are the binary code for register A, and the last three bits 000 are the binary code for segister B. In Example 2 the opcode for ADD B is 80 H. In this instruction one of the operands is register B (its content is one of the data) which is indicated in the instruction itself. In this type of instruction (arithmetic group) it is understood that the other operand is in the accumulator. The opcode 80 H in the binary form is 10000000. The first five bits, ie., 10000 specify the operation to be performed, ie., ADD. The last three bits 000 are the binary code for register B for 8085 microprocessor. 3.12.3 Register Indirect Addressing In this mode of addressing the address of the operand is specified by a register pair. Examples are: [ Mnemonics ‘Opeode [Function LXI H, 2500 H Load H-L pair with 2500 H. MOV A.M Move the content of the memory location, whose address is in HLL Pair (e., 2500 H) to the accumulator. HLT [Stop the execution of the program In the above program, the instruction MOV A. M is an example of register indirect addressing. For this instruction the operand is in the memory. The address of the memory is not directly given in the instruction. The address of the memory resides in H-L pair and this has already been specified by an earlier instruction in the program, ie., LXI H, 2500 H ‘Mnemonics Opcode | Function LXI H, 2500 H Load the H-L pair with 2500 H ADD M ‘Add the content of the memory location, whose address is in HLL pair (.e., 2500 H) to the content of the accumulator HLT Stop the execution of the program Jn this program, the instruction ADD M shows how register indirect addressing is used. 3.12.4 Immediate Addressing In immediate addressing mode the operand is specified within the instruction itself. examples are’94 MICROPROCESSORS AND MICROCONTROLLERS. S.No. | Mnemonics Opcode Function 1. MVIA, 05 3E, 05 Move 05 in register A 2 ADI 06 C6, 06 Add 06 to the content of the accumulator. Jn these instructions the 2nd byte specifies data. 3.12.5 Implicit Addressing If address of source of data as well as address of destination of result is fixed, then there is no need to give any operand along with the instruction, The instruction itself specifies the type of operation and location of data to be operated. This type of instruction does not have any address, register name, immediate data specified along with it. For example CMA is the operation (Complement accumulator) A is the source and A is the destination. Some other examples are RAR, RAL, RLC, RRC, etc. 3.13 INSTRUCTION SET An instruction is a command given to the computer to perform a specified operation on given data. The instruction set of a microprocessor is the collection of the instructions that the microprocessor is designed to execute. The instructions described in this chapter are of INTEL 8085. The programmer can write a program in assembly language using these instructions. There are 74 valid instructions in the complete set of 8085 instructions. These instructions have been classified into the following groups. L. Data Transfer Group 2. Arithmetic Group 3. Logical Group 4. Branch Control Group 5. VO and Machine Control Group. 3.13.1 Data Transfer Group Instructions which are used fo transfer data from one register to another register, from memory to register or register to memory, come under this group. Examples are; MOV, MVI, LXI, LDA, STA, etc. When an instruction of data transfer group is executed, data is transferred from the source to the destination without altering the contents of the source. For example, when MOV A, B is executed the content of the register B is copied into the register A. and the content of register B remains unaltered. Similarly, when LDA 3500 is executed the content of the memory location 3500 is loaded into the accumulator, but the content of the memory location 3500 remains unaltered. S, | Instruction | Register Details Addressing | Instruction No ‘Transfer Logic Mode Tength 1 [MOV 5. 2 | fq] — [e] Contents of register r, are moved | Register | 1 Byte to register rl. Register ri/t2 may be any register out of six GPR*s ABCGDEHLMOV 5, M i] — (eb) INTEL 8085 MICROPROCESSOR Contents of memory location whose address is in HL register pair are moved to register r. Indirect Register 1 Byte 95 MOV M. r (GHL)] = Ee] Contents of register “r” are moved to memory location whose address is in HL register pair Indirect Register 1 Byte MVIs, data [] — data ‘Move 8-bit data specified in the instruction to register r Immediate. 2.Byte MVIM, data(8) [GHD] = data ‘Move S.bit data specified in the instruction to memory location whose address is in register pair HL. Immediate 3-Byte datal6 [rp] data Load segister pair with 16-bit data. Immediate LDA ade [A] — [addr] ‘Load accumulator direetly with contents of memory location whose address is specified in the instruction itself. Direct STA addr [addr] + [A] Store contents of memory location whose address is specified in the instruction itself in accumulator. Direct 3-Byte LHLD addr IL] — [addr] [HI + [addr + 1] Load the contents of memory location whose address is specified in the instruction into register L and next memory location into register H. Direct 3.Byte 10 SHLD addr [addr] = [L] [addr +1] —[H] Store the contents of register L into: memory location whose address is specified in the instruction and contents of register H into next memory location. 3.Byte i LDAK p [Al — [Gp)] Load accumulator indirect Contents of memory location whose address is in register pair sp is loaded into accumulator. Register pair used is either BC or DE but not HL. Register Indirect 1 Byte 2 STAX ip (pa) — [AT Store contents of accumulator into memory location whose address is in register pair rp. Register pair used is either BC or DE but not HL. Register Indirect 2.Byte96 MICROPROCESSORS AND MICROCONTROLLERS. 13 IN addr(8) | [A]—[port addr] Read data byte from input device whose 8-bit port address is specified in instruction into accumulator. Direct 3-Byte 14 | OUT adds(8) [port addr] — [A] Send data byte from accumulator to output device whose 3-bit port address is specified in instruction. Direct 2.Byte i) xXcHG | [HJ-ID] Lis] Tt exchanges the content of H-L register pair with that of D-E Register register pairs. 1 Byte 3.13.2 Arithmetic Group The instructions of this group perform arithmetic operations such as addition, subtraction: increment or decrement of the content of a register or memory. Examples are: ADD, SUB, INR, DAD. etc. 'S. | Insteuetion | Register ‘Arithmetic Group Details “Addressing | Instruction | Flags No. transfer logic Mode length _| affected 1 /ADDr [fA] — TA] + | Add the contents ofregisier rim the | Register [One Byte | All ol contents of accumulator and result is stored im accunmlator. Register T may be any register out of six GPRe A, B,C, D, E, HL 2 ADDM [[A]—IA]+ |Add the contents of memory | Register | Two-Byte | All (el) location M whose address is in | Indirect HLL register pair in the contents of accumulator and result is stored in accumulator 3 JaDCr [fA] — [AT + | Add the contents of register r in| Register | Three-byte | All [i +{CY] | the contents of accumulator along with camry bit and result is stored in accumulator. Register r may be ‘any register out of six GPRs A, B, CDEHL 4 ]ADCM [[A]—[A]+ |Add the contents of memory | Register |Four-Byte | All (HL) + location M whose address is in | Indirect (cy) HL register pair in the contents of accumulator along with cary bit and result is stored im accumulator. 5 | ADI data [[A] — [A] + |Add the 8-bit data specified im the | Immediate |Two-Byte | All B-bit data —_| contents of accumulator and result is stored in accumulator.